712ec27916
Add the GOT base for R_386_GOT32/R_386_GOT32X relocations against IFUNC symbols if there is no base register and disallow them for PIC. bfd/ PR ld/20244 * elf32-i386.c (elf_i386_relocate_section): Add the .got.plt section address for R_386_GOT32/R_386_GOT32X relocations against IFUNC symbols if there is no base register and return error for PIC. ld/ PR ld/20244 * testsuite/ld-i386/i386.exp: Run pr20244-2a, pr20244-2b, pr20244-2c and pr20244-2d. * testsuite/ld-i386/no-plt.exp: Run pr20244-3a and pr20244-3b. * testsuite/ld-i386/pr20244-2.s: New file. * testsuite/ld-i386/pr20244-2a.d: Likewise. * testsuite/ld-i386/pr20244-2b.d: Likewise. * testsuite/ld-i386/pr20244-2c.d: Likewise. * testsuite/ld-i386/pr20244-2d.d: Likewise. * testsuite/ld-i386/pr20244-3a.c: Likewise. * testsuite/ld-i386/pr20244-3b.S: Likewise. * testsuite/ld-i386/pr20244-3c.S: Likewise. * testsuite/ld-i386/pr20244-3d.S: Likewise.
43 lines
1.1 KiB
Makefile
43 lines
1.1 KiB
Makefile
#source: pr20244-2.s
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#as: --32
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#ld: -m elf_i386
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#objdump: --sym -dw
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#notarget: i?86-*-nacl* x86_64-*-nacl*
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.*: +file format .*
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SYMBOL TABLE:
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#...
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0+80480b1 l i .text 00000000 bar
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#...
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0+80480b2 g F .text 00000000 _start
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#...
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0+80480b0 g i .text 00000000 foo
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#...
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Disassembly of section .plt:
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0+8048090 <.plt>:
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+[a-f0-9]+: ff 25 e0 90 04 08 jmp \*0x80490e0
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+[a-f0-9]+: 68 00 00 00 00 push \$0x0
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+[a-f0-9]+: e9 00 00 00 00 jmp 80480a0 <foo-0x10>
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+[a-f0-9]+: ff 25 e4 90 04 08 jmp \*0x80490e4
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+[a-f0-9]+: 68 00 00 00 00 push \$0x0
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+[a-f0-9]+: e9 00 00 00 00 jmp 80480b0 <foo>
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Disassembly of section .text:
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0+80480b0 <foo>:
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+[a-f0-9]+: c3 ret
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0+80480b1 <bar>:
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+[a-f0-9]+: c3 ret
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0+80480b2 <_start>:
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+[a-f0-9]+: ff 15 e0 90 04 08 call \*0x80490e0
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+[a-f0-9]+: ff 25 e4 90 04 08 jmp \*0x80490e4
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+[a-f0-9]+: c7 05 e4 90 04 08 00 00 00 00 movl \$0x0,0x80490e4
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+[a-f0-9]+: 83 3d e0 90 04 08 00 cmpl \$0x0,0x80490e0
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+[a-f0-9]+: b9 10 00 00 00 mov \$0x10,%ecx
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#pass
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