144 lines
3.3 KiB
C
144 lines
3.3 KiB
C
/* This file is part of the program psim.
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Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/* What does the instruction look like - bit ordering, size, widths or offesets */
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extern int hi_bit_nr;
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extern int insn_bit_size;
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extern int insn_specifying_widths;
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/* what should global names be prefixed with? */
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extern const char *global_name_prefix;
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extern const char *global_uname_prefix;
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/* generation options: */
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enum {
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generate_with_direct_access = 0x1,
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generate_with_icache = 0x2,
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generate_with_semantic_icache = 0x4,
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generate_with_insn_in_icache = 0x8,
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generate_with_semantic_returning_modified_nia_only = 0x010,
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generate_with_semantic_conditional_issue = 0x020,
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generate_with_idecode_slot_verification = 0x040,
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generate_with_semantic_delayed_branch = 0x080,
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generate_with_semantic_zero_r0 = 0x100
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};
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typedef enum {
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/* Transfer control to an instructions semantic code using the the
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standard call/return mechanism */
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generate_calls = 0x1000,
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/* Transfer control to an instructions semantic code using
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(computed) goto's instead of the more conventional call/return
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mechanism */
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generate_jumps = 0x2000,
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} igen_code;
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extern int code;
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extern int icache_size;
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/* Instruction expansion?
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Should the semantic code for each instruction, when the oportunity
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arrises, be expanded according to the variable opcode files that
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the instruction decode process renders constant */
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extern int generate_expanded_instructions;
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/* SMP?
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Should the generated code include SMP support (>0) and if so, for
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how many processors? */
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extern int generate_smp;
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/* Misc junk */
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/* Function header definitions */
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/* Cache functions: */
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extern int print_icache_function_formal
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(lf *file);
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extern int print_icache_function_actual
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(lf *file);
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extern int print_icache_function_type
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(lf *file);
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extern int print_semantic_function_formal
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(lf *file);
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extern int print_semantic_function_actual
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(lf *file);
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extern int print_semantic_function_type
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(lf *file);
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extern void print_my_defines
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(lf *file,
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insn_bits *expanded_bits,
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table_entry *file_entry);
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extern void print_itrace
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(lf *file,
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table_entry *file_entry,
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int idecode);
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typedef enum {
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function_name_prefix_semantics,
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function_name_prefix_idecode,
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function_name_prefix_itable,
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function_name_prefix_icache,
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function_name_prefix_none
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} lf_function_name_prefixes;
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extern int print_function_name
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(lf *file,
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const char *basename,
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insn_bits *expanded_bits,
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lf_function_name_prefixes prefix);
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