933786524e
* README.txt: New. * config.h (CYCLE_ACCURATE, CYCLE_STATS): New. * configure.in (--enable-cycle-accurate, --enable-cycle-stats): New. Default to enabled. * configure: Regenerate. * cpu.h (regs_type): Add cycle tracking info. (reset_pipeline_stats): Declare. (halt_pipeline_stats): Declare. (pipeline_stats): Declare. * main.c (done): Call pipeline_stats(). * mem.h (rx_mem_ptr): Moved to here ... * mem.c (mem_ptr): ... from here. Rename throughout. (mem_put_byte): Move LEDs to Port A. Add Port B to control cycle statistics. Move UART to SCI4. (mem_put_hi): Add TPU 1-2. TPU 1 and 2 count CPU cycles. * reg.c (init_regs): Set Rt reg to -1 (no reg). * rx.c: Add cycle counting and statistics throughout. (rx_get_byte): Optimize for speed. (decode_opcode): Likewise. (reset_pipeline_stats): New. (halt_pipeline_stats): New. (pipeline_stats): New. * trace.c (sim_disasm_one): Print cycle count. [include/opcode] * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
558 lines
11 KiB
C
558 lines
11 KiB
C
/* reg.c --- register set model for RX simulator.
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Copyright (C) 2005, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
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Contributed by Red Hat, Inc.
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This file is part of the GNU simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "config.h"
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "cpu.h"
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#include "bfd.h"
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#include "trace.h"
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int verbose = 0;
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int trace = 0;
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int enable_counting = 0;
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int rx_in_gdb = 1;
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int rx_flagmask;
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int rx_flagand;
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int rx_flagor;
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int rx_big_endian;
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regs_type regs;
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int step_result;
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unsigned int heapbottom = 0;
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unsigned int heaptop = 0;
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char *reg_names[] = {
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/* general registers */
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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/* control register */
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"psw", "pc", "usp", "fpsw", "RES", "RES", "RES", "RES",
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"bpsw", "bpc", "isp", "fintv", "intb", "RES", "RES", "RES",
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"RES", "RES", "RES", "RES", "RES", "RES", "RES", "RES",
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"RES", "RES", "RES", "RES", "RES", "RES", "RES", "RES",
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"temp", "acc", "acchi", "accmi", "acclo"
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};
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unsigned int b2mask[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
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unsigned int b2signbit[] = { 0, (1 << 7), (1 << 15), (1 << 24), (1 << 31) };
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int b2maxsigned[] = { 0, 0x7f, 0x7fff, 0x7fffff, 0x7fffffff };
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int b2minsigned[] = { 0, -128, -32768, -8388608, -2147483647 - 1 };
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static regs_type oldregs;
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void
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init_regs (void)
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{
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memset (®s, 0, sizeof (regs));
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memset (&oldregs, 0, sizeof (oldregs));
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#ifdef CYCLE_ACCURATE
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regs.rt = -1;
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oldregs.rt = -1;
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#endif
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}
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static unsigned int
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get_reg_i (int id)
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{
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if (id == 0)
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return regs.r_psw & FLAGBIT_U ? regs.r_usp : regs.r_isp;
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if (id >= 1 && id <= 15)
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return regs.r[id];
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switch (id)
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{
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case psw:
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return regs.r_psw;
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case fpsw:
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return regs.r_fpsw;
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case isp:
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return regs.r_isp;
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case usp:
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return regs.r_usp;
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case bpc:
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return regs.r_bpc;
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case bpsw:
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return regs.r_bpsw;
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case fintv:
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return regs.r_fintv;
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case intb:
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return regs.r_intb;
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case pc:
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return regs.r_pc;
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case r_temp_idx:
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return regs.r_temp;
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case acchi:
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return (SI)(regs.r_acc >> 32);
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case accmi:
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return (SI)(regs.r_acc >> 16);
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case acclo:
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return (SI)regs.r_acc;
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}
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abort();
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}
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unsigned int
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get_reg (int id)
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{
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unsigned int rv = get_reg_i (id);
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if (trace > ((id != pc && id != sp) ? 0 : 1))
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printf ("get_reg (%s) = %08x\n", reg_names[id], rv);
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return rv;
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}
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static unsigned long long
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get_reg64_i (int id)
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{
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switch (id)
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{
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case acc64:
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return regs.r_acc;
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default:
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abort ();
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}
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}
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unsigned long long
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get_reg64 (int id)
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{
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unsigned long long rv = get_reg64_i (id);
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if (trace > ((id != pc && id != sp) ? 0 : 1))
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printf ("get_reg (%s) = %016llx\n", reg_names[id], rv);
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return rv;
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}
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static int highest_sp = 0, lowest_sp = 0xffffff;
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void
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stack_heap_stats ()
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{
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if (heapbottom < heaptop)
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printf ("heap: %08x - %08x (%d bytes)\n", heapbottom, heaptop,
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heaptop - heapbottom);
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if (lowest_sp < highest_sp)
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printf ("stack: %08x - %08x (%d bytes)\n", lowest_sp, highest_sp,
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highest_sp - lowest_sp);
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}
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void
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put_reg (int id, unsigned int v)
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{
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if (trace > ((id != pc) ? 0 : 1))
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printf ("put_reg (%s) = %08x\n", reg_names[id], v);
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switch (id)
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{
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case psw:
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regs.r_psw = v;
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break;
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case fpsw:
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{
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SI anded;
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/* This is an odd one - The Cx flags are AND'd, and the FS flag
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is synthetic. */
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anded = regs.r_fpsw & v;
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anded |= ~ FPSWBITS_CMASK;
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regs.r_fpsw = v & anded;
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if (regs.r_fpsw & FPSWBITS_FMASK)
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regs.r_fpsw |= FPSWBITS_FSUM;
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else
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regs.r_fpsw &= ~FPSWBITS_FSUM;
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}
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break;
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case isp:
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regs.r_isp = v;
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break;
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case usp:
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regs.r_usp = v;
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break;
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case bpc:
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regs.r_bpc = v;
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break;
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case bpsw:
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regs.r_bpsw = v;
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break;
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case fintv:
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regs.r_fintv = v;
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break;
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case intb:
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regs.r_intb = v;
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break;
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case pc:
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regs.r_pc = v;
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break;
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case acchi:
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regs.r_acc = (regs.r_acc & 0xffffffffULL) | ((DI)v << 32);
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break;
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case accmi:
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regs.r_acc = (regs.r_acc & ~0xffffffff0000ULL) | ((DI)v << 16);
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break;
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case acclo:
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regs.r_acc = (regs.r_acc & ~0xffffffffULL) | ((DI)v);
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break;
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case 0: /* Stack pointer is "in" R0. */
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{
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if (v < heaptop)
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{
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unsigned int line;
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const char * dummy;
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const char * fname = NULL;
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sim_get_current_source_location (& dummy, & fname, &line);
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/* The setjmp and longjmp functions play tricks with the stack pointer. */
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if (fname == NULL
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|| (strcmp (fname, "_setjmp") != 0
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&& strcmp (fname, "_longjmp") != 0))
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{
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printf ("collision in %s: pc %08x heap %08x stack %08x\n",
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fname, (unsigned int) regs.r_pc, heaptop, v);
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exit (1);
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}
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}
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else
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{
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if (v < lowest_sp)
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lowest_sp = v;
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if (v > highest_sp)
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highest_sp = v;
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}
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if (regs.r_psw & FLAGBIT_U)
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regs.r_usp = v;
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else
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regs.r_isp = v;
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break;
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}
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default:
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if (id >= 1 || id <= 15)
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regs.r[id] = v;
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else
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abort ();
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}
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}
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void
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put_reg64 (int id, unsigned long long v)
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{
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if (trace > ((id != pc) ? 0 : 1))
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printf ("put_reg (%s) = %016llx\n", reg_names[id], v);
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switch (id)
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{
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case acc64:
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regs.r_acc = v;
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break;
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default:
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abort ();
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}
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}
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int
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condition_true (int cond_id)
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{
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int f;
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static const char *cond_name[] = {
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"Z",
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"!Z",
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"C",
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"!C",
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"C&!Z",
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"!(C&!Z)",
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"!S",
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"S",
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"!(S^O)",
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"S^O",
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"!((S^O)|Z)",
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"(S^O)|Z",
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"O",
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"!O",
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"always",
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"never"
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};
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switch (cond_id & 15)
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{
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case 0:
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f = FLAG_Z;
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break; /* EQ/Z */
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case 1:
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f = !FLAG_Z;
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break; /* NE/NZ */
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case 2:
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f = FLAG_C;
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break; /* GEU/C */
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case 3:
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f = !FLAG_C;
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break; /* LTU/NC */
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case 4:
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f = FLAG_C & !FLAG_Z;
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break; /* GTU */
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case 5:
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f = !(FLAG_C & !FLAG_Z);
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break; /* LEU */
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case 6:
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f = !FLAG_S;
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break; /* PZ */
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case 7:
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f = FLAG_S;
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break; /* N */
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case 8:
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f = !(FLAG_S ^ FLAG_O);
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break; /* GE */
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case 9:
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f = FLAG_S ^ FLAG_O;
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break; /* LT */
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case 10:
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f = !((FLAG_S ^ FLAG_O) | FLAG_Z);
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break; /* GT */
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case 11:
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f = (FLAG_S ^ FLAG_O) | FLAG_Z;
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break; /* LE */
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case 12:
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f = FLAG_O;
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break; /* O */
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case 13:
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f = !FLAG_O;
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break; /* NO */
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case 14:
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f = 1; /* always */
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break;
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default:
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f = 0; /* never */
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break;
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}
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if (trace && ((cond_id & 15) != 14))
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printf ("cond[%d] %s = %s\n", cond_id, cond_name[cond_id & 15],
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f ? "true" : "false");
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return f;
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}
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void
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set_flags (int mask, int newbits)
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{
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regs.r_psw &= rx_flagand;
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regs.r_psw |= rx_flagor;
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regs.r_psw |= (newbits & mask & rx_flagmask);
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if (trace)
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{
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int i;
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printf ("flags now \033[32m %d", (int)((regs.r_psw >> 24) & 7));
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for (i = 17; i >= 0; i--)
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if (0x3000f & (1 << i))
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{
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if (regs.r_psw & (1 << i))
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putchar ("CZSO------------IU"[i]);
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else
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putchar ('-');
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}
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printf ("\033[0m\n");
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}
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}
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void
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set_oszc (long long value, int b, int c)
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{
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unsigned int mask = b2mask[b];
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int f = 0;
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if (c)
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f |= FLAGBIT_C;
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if ((value & mask) == 0)
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f |= FLAGBIT_Z;
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if (value & b2signbit[b])
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f |= FLAGBIT_S;
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if ((value > b2maxsigned[b]) || (value < b2minsigned[b]))
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f |= FLAGBIT_O;
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set_flags (FLAGBIT_Z | FLAGBIT_S | FLAGBIT_O | FLAGBIT_C, f);
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}
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void
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set_szc (long long value, int b, int c)
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{
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unsigned int mask = b2mask[b];
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int f = 0;
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if (c)
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f |= FLAGBIT_C;
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if ((value & mask) == 0)
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f |= FLAGBIT_Z;
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if (value & b2signbit[b])
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f |= FLAGBIT_S;
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set_flags (FLAGBIT_Z | FLAGBIT_S | FLAGBIT_C, f);
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}
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void
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set_osz (long long value, int b)
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{
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unsigned int mask = b2mask[b];
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int f = 0;
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if ((value & mask) == 0)
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f |= FLAGBIT_Z;
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if (value & b2signbit[b])
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f |= FLAGBIT_S;
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if ((value > b2maxsigned[b]) || (value < b2minsigned[b]))
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f |= FLAGBIT_O;
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set_flags (FLAGBIT_Z | FLAGBIT_S | FLAGBIT_O, f);
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}
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void
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set_sz (long long value, int b)
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{
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unsigned int mask = b2mask[b];
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int f = 0;
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if ((value & mask) == 0)
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f |= FLAGBIT_Z;
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if (value & b2signbit[b])
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f |= FLAGBIT_S;
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set_flags (FLAGBIT_Z | FLAGBIT_S, f);
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}
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void
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set_zc (int z, int c)
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{
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set_flags (FLAGBIT_C | FLAGBIT_Z,
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(c ? FLAGBIT_C : 0) | (z ? FLAGBIT_Z : 0));
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}
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void
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set_c (int c)
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{
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set_flags (FLAGBIT_C, c ? FLAGBIT_C : 0);
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}
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static char *
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psw2str(int rpsw)
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{
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static char buf[10];
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char *bp = buf;
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int i, ipl;
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ipl = (rpsw & FLAGBITS_IPL) >> FLAGSHIFT_IPL;
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if (ipl > 9)
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{
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*bp++ = (ipl / 10) + '0';
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ipl %= 10;
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}
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*bp++ = ipl + '0';
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for (i = 20; i >= 0; i--)
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if (0x13000f & (1 << i))
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{
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if (rpsw & (1 << i))
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*bp++ = "CZSO------------IU--P"[i];
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else
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*bp++ = '-';
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}
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*bp = 0;
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return buf;
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}
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static char *
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fpsw2str(int rpsw)
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{
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static char buf[100];
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char *bp = buf;
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int i; /* ---+---+---+---+---+---+---+---+ */
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const char s1[] = "FFFFFF-----------EEEEE-DCCCCCCRR";
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const char s2[] = "SXUZOV-----------XUZOV-NEXUZOV01";
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const char rm[4][3] = { "RC", "RZ", "RP", "RN" };
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for (i = 31; i >= 0; i--)
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if (0xfc007dfc & (1 << i))
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{
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if (rpsw & (1 << i))
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{
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if (bp > buf)
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*bp++ = '.';
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*bp++ = s1[31-i];
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*bp++ = s2[31-i];
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}
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}
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if (bp > buf)
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*bp++ = '.';
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strcpy (bp, rm[rpsw&3]);
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return buf;
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}
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#define TRC(f,n) \
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if (oldregs.f != regs.f) \
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{ \
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if (tag) { printf (tag); tag = 0; } \
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printf(" %s %08x:%08x", n, \
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(unsigned int)oldregs.f, \
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(unsigned int)regs.f); \
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oldregs.f = regs.f; \
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}
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void
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trace_register_changes (void)
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{
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char *tag = "\033[36mREGS:";
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int i;
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if (!trace)
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return;
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for (i=1; i<16; i++)
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TRC (r[i], reg_names[i]);
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TRC (r_intb, "intb");
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TRC (r_usp, "usp");
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TRC (r_isp, "isp");
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if (oldregs.r_psw != regs.r_psw)
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{
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if (tag) { printf (tag); tag = 0; }
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printf(" psw %s:", psw2str(oldregs.r_psw));
|
|
printf("%s", psw2str(regs.r_psw));
|
|
oldregs.r_psw = regs.r_psw;
|
|
}
|
|
|
|
if (oldregs.r_fpsw != regs.r_fpsw)
|
|
{
|
|
if (tag) { printf (tag); tag = 0; }
|
|
printf(" fpsw %s:", fpsw2str(oldregs.r_fpsw));
|
|
printf("%s", fpsw2str(regs.r_fpsw));
|
|
oldregs.r_fpsw = regs.r_fpsw;
|
|
}
|
|
|
|
if (oldregs.r_acc != regs.r_acc)
|
|
{
|
|
if (tag) { printf (tag); tag = 0; }
|
|
printf(" acc %016llx:", oldregs.r_acc);
|
|
printf("%016llx", regs.r_acc);
|
|
oldregs.r_acc = regs.r_acc;
|
|
}
|
|
|
|
if (tag == 0)
|
|
printf ("\033[0m\n");
|
|
}
|