423 lines
9.5 KiB
C
423 lines
9.5 KiB
C
/* fr30 simulator support code
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Copyright (C) 1998, 1999 Free Software Foundation, Inc.
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Contributed by Cygnus Solutions.
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This file is part of the GNU simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#define WANT_CPU
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#define WANT_CPU_FR30BF
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#include "sim-main.h"
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#include "cgen-mem.h"
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#include "cgen-ops.h"
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/* Convert gdb dedicated register number to actual dr reg number. */
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static int
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decode_gdb_dr_regnum (int gdb_regnum)
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{
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switch (gdb_regnum)
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{
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case TBR_REGNUM : return H_DR_TBR;
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case RP_REGNUM : return H_DR_RP;
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case SSP_REGNUM : return H_DR_SSP;
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case USP_REGNUM : return H_DR_USP;
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case MDH_REGNUM : return H_DR_MDH;
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case MDL_REGNUM : return H_DR_MDL;
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}
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abort ();
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}
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/* The contents of BUF are in target byte order. */
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int
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fr30bf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
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{
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if (rn < 16)
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SETTWI (buf, fr30bf_h_gr_get (current_cpu, rn));
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else
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switch (rn)
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{
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case PC_REGNUM :
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SETTWI (buf, fr30bf_h_pc_get (current_cpu));
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break;
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case PS_REGNUM :
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SETTWI (buf, fr30bf_h_ps_get (current_cpu));
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break;
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case TBR_REGNUM :
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case RP_REGNUM :
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case SSP_REGNUM :
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case USP_REGNUM :
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case MDH_REGNUM :
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case MDL_REGNUM :
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SETTWI (buf, fr30bf_h_dr_get (current_cpu,
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decode_gdb_dr_regnum (rn)));
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break;
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default :
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return 0;
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}
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return -1; /*FIXME*/
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}
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/* The contents of BUF are in target byte order. */
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int
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fr30bf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
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{
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if (rn < 16)
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fr30bf_h_gr_set (current_cpu, rn, GETTWI (buf));
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else
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switch (rn)
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{
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case PC_REGNUM :
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fr30bf_h_pc_set (current_cpu, GETTWI (buf));
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break;
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case PS_REGNUM :
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fr30bf_h_ps_set (current_cpu, GETTWI (buf));
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break;
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case TBR_REGNUM :
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case RP_REGNUM :
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case SSP_REGNUM :
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case USP_REGNUM :
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case MDH_REGNUM :
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case MDL_REGNUM :
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fr30bf_h_dr_set (current_cpu,
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decode_gdb_dr_regnum (rn),
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GETTWI (buf));
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break;
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default :
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return 0;
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}
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return -1; /*FIXME*/
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}
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/* Cover fns to access the ccr bits. */
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BI
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fr30bf_h_sbit_get_handler (SIM_CPU *current_cpu)
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{
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return CPU (h_sbit);
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}
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void
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fr30bf_h_sbit_set_handler (SIM_CPU *current_cpu, BI newval)
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{
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int old_sbit = CPU (h_sbit);
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int new_sbit = (newval != 0);
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CPU (h_sbit) = new_sbit;
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/* When switching stack modes, update the registers. */
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if (old_sbit != new_sbit)
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{
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if (old_sbit)
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{
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/* Switching user -> system. */
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CPU (h_dr[H_DR_USP]) = CPU (h_gr[H_GR_SP]);
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CPU (h_gr[H_GR_SP]) = CPU (h_dr[H_DR_SSP]);
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}
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else
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{
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/* Switching system -> user. */
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CPU (h_dr[H_DR_SSP]) = CPU (h_gr[H_GR_SP]);
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CPU (h_gr[H_GR_SP]) = CPU (h_dr[H_DR_USP]);
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}
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}
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/* TODO: r15 interlock */
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}
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/* Cover fns to access the ccr bits. */
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UQI
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fr30bf_h_ccr_get_handler (SIM_CPU *current_cpu)
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{
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int ccr = ( (GET_H_CBIT () << 0)
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| (GET_H_VBIT () << 1)
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| (GET_H_ZBIT () << 2)
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| (GET_H_NBIT () << 3)
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| (GET_H_IBIT () << 4)
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| (GET_H_SBIT () << 5));
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return ccr;
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}
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void
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fr30bf_h_ccr_set_handler (SIM_CPU *current_cpu, UQI newval)
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{
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int ccr = newval & 0x3f;
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SET_H_CBIT ((ccr & 1) != 0);
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SET_H_VBIT ((ccr & 2) != 0);
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SET_H_ZBIT ((ccr & 4) != 0);
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SET_H_NBIT ((ccr & 8) != 0);
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SET_H_IBIT ((ccr & 0x10) != 0);
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SET_H_SBIT ((ccr & 0x20) != 0);
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}
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/* Cover fns to access the scr bits. */
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UQI
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fr30bf_h_scr_get_handler (SIM_CPU *current_cpu)
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{
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int scr = ( (GET_H_TBIT () << 0)
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| (GET_H_D0BIT () << 1)
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| (GET_H_D1BIT () << 2));
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return scr;
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}
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void
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fr30bf_h_scr_set_handler (SIM_CPU *current_cpu, UQI newval)
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{
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int scr = newval & 7;
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SET_H_TBIT ((scr & 1) != 0);
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SET_H_D0BIT ((scr & 2) != 0);
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SET_H_D1BIT ((scr & 4) != 0);
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}
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/* Cover fns to access the ilm bits. */
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UQI
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fr30bf_h_ilm_get_handler (SIM_CPU *current_cpu)
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{
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return CPU (h_ilm);
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}
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void
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fr30bf_h_ilm_set_handler (SIM_CPU *current_cpu, UQI newval)
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{
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int ilm = newval & 0x1f;
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int current_ilm = CPU (h_ilm);
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/* We can only set new ilm values < 16 if the current ilm is < 16. Otherwise
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we add 16 to the value we are given. */
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if (current_ilm >= 16 && ilm < 16)
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ilm += 16;
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CPU (h_ilm) = ilm;
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}
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/* Cover fns to access the ps register. */
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USI
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fr30bf_h_ps_get_handler (SIM_CPU *current_cpu)
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{
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int ccr = GET_H_CCR ();
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int scr = GET_H_SCR ();
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int ilm = GET_H_ILM ();
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return ccr | (scr << 8) | (ilm << 16);
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}
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void
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fr30bf_h_ps_set_handler (SIM_CPU *current_cpu, USI newval)
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{
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int ccr = newval & 0xff;
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int scr = (newval >> 8) & 7;
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int ilm = (newval >> 16) & 0x1f;
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SET_H_CCR (ccr);
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SET_H_SCR (scr);
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SET_H_ILM (ilm);
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}
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/* Cover fns to access the dedicated registers. */
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SI
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fr30bf_h_dr_get_handler (SIM_CPU *current_cpu, UINT dr)
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{
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switch (dr)
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{
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case H_DR_SSP :
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if (! GET_H_SBIT ())
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return GET_H_GR (H_GR_SP);
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else
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return CPU (h_dr[H_DR_SSP]);
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case H_DR_USP :
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if (GET_H_SBIT ())
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return GET_H_GR (H_GR_SP);
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else
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return CPU (h_dr[H_DR_USP]);
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case H_DR_TBR :
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case H_DR_RP :
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case H_DR_MDH :
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case H_DR_MDL :
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return CPU (h_dr[dr]);
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}
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return 0;
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}
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void
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fr30bf_h_dr_set_handler (SIM_CPU *current_cpu, UINT dr, SI newval)
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{
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switch (dr)
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{
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case H_DR_SSP :
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if (! GET_H_SBIT ())
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SET_H_GR (H_GR_SP, newval);
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else
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CPU (h_dr[H_DR_SSP]) = newval;
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break;
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case H_DR_USP :
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if (GET_H_SBIT ())
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SET_H_GR (H_GR_SP, newval);
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else
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CPU (h_dr[H_DR_USP]) = newval;
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break;
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case H_DR_TBR :
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case H_DR_RP :
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case H_DR_MDH :
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case H_DR_MDL :
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CPU (h_dr[dr]) = newval;
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break;
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}
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}
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#if WITH_PROFILE_MODEL_P
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/* FIXME: Some of these should be inline or macros. Later. */
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/* Initialize cycle counting for an insn.
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FIRST_P is non-zero if this is the first insn in a set of parallel
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insns. */
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void
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fr30bf_model_insn_before (SIM_CPU *cpu, int first_p)
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{
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MODEL_FR30_1_DATA *d = CPU_MODEL_DATA (cpu);
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d->load_regs_pending = 0;
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}
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/* Record the cycles computed for an insn.
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LAST_P is non-zero if this is the last insn in a set of parallel insns,
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and we update the total cycle count.
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CYCLES is the cycle count of the insn. */
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void
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fr30bf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
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{
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PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
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MODEL_FR30_1_DATA *d = CPU_MODEL_DATA (cpu);
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PROFILE_MODEL_TOTAL_CYCLES (p) += cycles;
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PROFILE_MODEL_CUR_INSN_CYCLES (p) = cycles;
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d->load_regs = d->load_regs_pending;
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}
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static INLINE int
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check_load_stall (SIM_CPU *cpu, int regno)
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{
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const MODEL_FR30_1_DATA *d = CPU_MODEL_DATA (cpu);
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UINT load_regs = d->load_regs;
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if (regno != -1
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&& (load_regs & (1 << regno)) != 0)
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{
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PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
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++ PROFILE_MODEL_LOAD_STALL_CYCLES (p);
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if (TRACE_INSN_P (cpu))
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cgen_trace_printf (cpu, " ; Load stall.");
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return 1;
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}
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else
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return 0;
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}
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int
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fr30bf_model_fr30_1_u_exec (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_Ri, INT in_Rj, INT out_Ri)
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{
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int cycles = idesc->timing->units[unit_num].done;
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cycles += check_load_stall (cpu, in_Ri);
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cycles += check_load_stall (cpu, in_Rj);
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return cycles;
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}
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int
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fr30bf_model_fr30_1_u_cti (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_Ri)
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{
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PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
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/* (1 << 1): The pc is the 2nd element in inputs, outputs.
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??? can be cleaned up */
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int taken_p = (referenced & (1 << 1)) != 0;
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int cycles = idesc->timing->units[unit_num].done;
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int delay_slot_p = CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_DELAY_SLOT);
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cycles += check_load_stall (cpu, in_Ri);
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if (taken_p)
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{
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/* ??? Handling cti's without delay slots this way will run afoul of
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accurate system simulation. Later. */
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if (! delay_slot_p)
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{
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++cycles;
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++PROFILE_MODEL_CTI_STALL_CYCLES (p);
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}
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++PROFILE_MODEL_TAKEN_COUNT (p);
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}
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else
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++PROFILE_MODEL_UNTAKEN_COUNT (p);
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return cycles;
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}
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int
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fr30bf_model_fr30_1_u_load (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_Rj, INT out_Ri)
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{
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MODEL_FR30_1_DATA *d = CPU_MODEL_DATA (cpu);
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int cycles = idesc->timing->units[unit_num].done;
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d->load_regs_pending |= 1 << out_Ri;
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cycles += check_load_stall (cpu, in_Rj);
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return cycles;
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}
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int
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fr30bf_model_fr30_1_u_store (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT in_Ri, INT in_Rj)
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{
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int cycles = idesc->timing->units[unit_num].done;
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cycles += check_load_stall (cpu, in_Ri);
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cycles += check_load_stall (cpu, in_Rj);
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return cycles;
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}
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int
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fr30bf_model_fr30_1_u_ldm (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT reglist)
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{
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return idesc->timing->units[unit_num].done;
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}
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int
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fr30bf_model_fr30_1_u_stm (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced,
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INT reglist)
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{
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return idesc->timing->units[unit_num].done;
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}
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#endif /* WITH_PROFILE_MODEL_P */
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