7eed1055b8
This avoids using global variables to hold the cpu state so we can better integrate with the sim common code. There's also a minor fix here where we move the pc register back into the state that is accessible by the asints array. When it was pulled out previously, the reg store/fetch functions broke, but no one really noticed as the mcore gdb port was dropped a while back.
79 lines
2.2 KiB
C
79 lines
2.2 KiB
C
/* Simulator for Motorola's MCore processor
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Copyright (C) 2009-2015 Free Software Foundation, Inc.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef SIM_MAIN_H
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#define SIM_MAIN_H
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#include "sim-basics.h"
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typedef long int word;
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typedef unsigned long int uword;
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#include "sim-base.h"
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#include "bfd.h"
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/* The machine state.
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This state is maintained in host byte order. The
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fetch/store register functions must translate between host
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byte order and the target processor byte order.
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Keeping this data in target byte order simplifies the register
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read/write functions. Keeping this data in native order improves
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the performance of the simulator. Simulation speed is deemed more
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important. */
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/* The ordering of the mcore_regset structure is matched in the
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gdb/config/mcore/tm-mcore.h file in the REGISTER_NAMES macro. */
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struct mcore_regset
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{
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word gregs[16]; /* primary registers */
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word alt_gregs[16]; /* alt register file */
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word cregs[32]; /* control registers */
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word pc;
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};
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#define LAST_VALID_CREG 32 /* only 0..12 implemented */
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#define NUM_MCORE_REGS (16 + 16 + LAST_VALID_CREG + 1)
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struct _sim_cpu {
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union
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{
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struct mcore_regset regs;
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/* Used by the fetch/store reg helpers to access registers linearly. */
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word asints[NUM_MCORE_REGS];
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};
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/* Used to switch between gregs/alt_gregs based on the control state. */
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word *active_gregs;
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int ticks;
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int stalls;
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int cycles;
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int insts;
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sim_cpu_base base;
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};
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struct sim_state {
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sim_cpu *cpu[MAX_NR_PROCESSORS];
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sim_state_base base;
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};
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#endif
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