746 lines
18 KiB
C
746 lines
18 KiB
C
/* Disassembler code for CRX.
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Copyright 2004 Free Software Foundation, Inc.
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Contributed by Tomer Levi, NSC, Israel.
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Written by Tomer Levi.
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This file is part of the GNU binutils and GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "dis-asm.h"
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#include "sysdep.h"
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#include "opcode/crx.h"
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/* String to print when opcode was not matched. */
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#define ILLEGAL "illegal"
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/* Escape to 16-bit immediate. */
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#define ESCAPE_16_BIT 0xE
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/* Extract 'n_bits' from 'a' starting from offset 'offs'. */
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#define EXTRACT(a, offs, n_bits) \
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(n_bits == 32 ? (((a) >> (offs)) & ~0L) \
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: (((a) >> (offs)) & ((1 << (n_bits)) -1)))
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/* Set Bit Mask - a mask to set all bits starting from offset 'offs'. */
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#define SBM(offs) ((((1 << (32 - offs)) -1) << (offs)))
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typedef unsigned long dwordU;
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typedef unsigned short wordU;
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typedef struct
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{
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dwordU val;
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int nbits;
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} parameter;
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/* Structure to hold valid 'cinv' instruction options. */
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typedef struct
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{
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/* Cinv printed string. */
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char *str;
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/* Value corresponding to the string. */
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unsigned int value;
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}
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cinv_entry;
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/* CRX 'cinv' options. */
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const cinv_entry crx_cinvs[] =
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{
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{"[i]", 2}, {"[i,u]", 3}, {"[d]", 4}, {"[d,u]", 5},
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{"[d,i]", 6}, {"[d,i,u]", 7}, {"[b]", 8},
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{"[b,i]", 10}, {"[b,i,u]", 11}, {"[b,d]", 12},
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{"[b,d,u]", 13}, {"[b,d,i]", 14}, {"[b,d,i,u]", 15}
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};
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/* Enum to distinguish different registers argument types. */
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typedef enum REG_ARG_TYPE
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{
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/* General purpose register (r<N>). */
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REG_ARG = 0,
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/* User register (u<N>). */
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USER_REG_ARG,
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/* CO-Processor register (c<N>). */
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COP_ARG,
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/* CO-Processor special register (cs<N>). */
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COPS_ARG
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}
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REG_ARG_TYPE;
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/* Number of valid 'cinv' instruction options. */
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int NUMCINVS = ((sizeof crx_cinvs)/(sizeof crx_cinvs[0]));
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/* Current opcode table entry we're disassembling. */
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const inst *instruction;
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/* Current instruction we're disassembling. */
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ins currInsn;
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/* The current instruction is read into 3 consecutive words. */
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wordU words[3];
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/* Contains all words in appropriate order. */
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ULONGLONG allWords;
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/* Holds the current processed argument number. */
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int processing_argument_number;
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/* Nonzero means a CST4 instruction. */
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int cst4flag;
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/* Nonzero means the instruction's original size is
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incremented (escape sequence is used). */
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int size_changed;
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static int get_number_of_operands (void);
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static argtype getargtype (operand_type);
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static int getbits (operand_type);
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static char *getregname (reg);
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static char *getcopregname (copreg, reg_type);
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static char * getprocregname (int);
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static char *gettrapstring (unsigned);
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static char *getcinvstring (unsigned);
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static void getregliststring (int, char *, enum REG_ARG_TYPE);
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static wordU get_word_at_PC (bfd_vma, struct disassemble_info *);
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static void get_words_at_PC (bfd_vma, struct disassemble_info *);
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static unsigned long build_mask (void);
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static int powerof2 (int);
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static int match_opcode (void);
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static void make_instruction (void);
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static void print_arguments (ins *, struct disassemble_info *);
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static void print_arg (argument *, struct disassemble_info *);
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/* Retrieve the number of operands for the current assembled instruction. */
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static int
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get_number_of_operands (void)
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{
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int i;
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for (i = 0; instruction->operands[i].op_type && i < MAX_OPERANDS; i++)
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;
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return i;
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}
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/* Return the bit size for a given operand. */
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static int
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getbits (operand_type op)
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{
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if (op < MAX_OPRD)
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return crx_optab[op].bit_size;
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else
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return 0;
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}
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/* Return the argument type of a given operand. */
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static argtype
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getargtype (operand_type op)
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{
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if (op < MAX_OPRD)
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return crx_optab[op].arg_type;
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else
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return nullargs;
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}
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/* Given the trap index in dispatch table, return its name.
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This routine is used when disassembling the 'excp' instruction. */
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static char *
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gettrapstring (unsigned int index)
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{
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const trap_entry *trap;
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for (trap = crx_traps; trap < crx_traps + NUMTRAPS; trap++)
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if (trap->entry == index)
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return trap->name;
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return ILLEGAL;
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}
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/* Given a 'cinv' instruction constant operand, return its corresponding string.
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This routine is used when disassembling the 'cinv' instruction. */
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static char *
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getcinvstring (unsigned int num)
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{
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const cinv_entry *cinv;
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for (cinv = crx_cinvs; cinv < (crx_cinvs + NUMCINVS); cinv++)
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if (cinv->value == num)
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return cinv->str;
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return ILLEGAL;
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}
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/* Given a register enum value, retrieve its name. */
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char *
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getregname (reg r)
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{
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const reg_entry *reg = &crx_regtab[r];
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if (reg->type != CRX_R_REGTYPE)
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return ILLEGAL;
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else
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return reg->name;
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}
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/* Given a coprocessor register enum value, retrieve its name. */
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char *
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getcopregname (copreg r, reg_type type)
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{
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const reg_entry *reg;
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if (type == CRX_C_REGTYPE)
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reg = &crx_copregtab[r];
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else if (type == CRX_CS_REGTYPE)
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reg = &crx_copregtab[r+(cs0-c0)];
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else
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return ILLEGAL;
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return reg->name;
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}
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/* Getting a processor register name. */
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static char *
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getprocregname (int index)
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{
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const reg_entry *r;
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for (r = crx_regtab; r < crx_regtab + NUMREGS; r++)
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if (r->image == index)
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return r->name;
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return "ILLEGAL REGISTER";
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}
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/* Get the power of two for a given integer. */
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static int
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powerof2 (int x)
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{
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int product, i;
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for (i = 0, product = 1; i < x; i++)
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product *= 2;
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return product;
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}
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/* Transform a register bit mask to a register list. */
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void
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getregliststring (int mask, char *string, enum REG_ARG_TYPE core_cop)
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{
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char temp_string[5];
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int i;
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string[0] = '{';
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string[1] = '\0';
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/* A zero mask means HI/LO registers. */
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if (mask == 0)
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{
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if (core_cop == USER_REG_ARG)
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strcat (string, "ulo,uhi");
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else
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strcat (string, "lo,hi");
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}
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else
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{
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for (i = 0; i < 16; i++)
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{
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if (mask & 0x1)
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{
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switch (core_cop)
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{
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case REG_ARG:
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sprintf (temp_string, "r%d", i);
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break;
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case USER_REG_ARG:
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sprintf (temp_string, "u%d", i);
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break;
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case COP_ARG:
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sprintf (temp_string, "c%d", i);
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break;
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case COPS_ARG:
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sprintf (temp_string, "cs%d", i);
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break;
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default:
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break;
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}
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strcat (string, temp_string);
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if (mask & 0xfffe)
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strcat (string, ",");
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}
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mask >>= 1;
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}
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}
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strcat (string, "}");
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}
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/* START and END are relating 'allWords' struct, which is 48 bits size.
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START|--------|END
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+---------+---------+---------+---------+
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| | V | A | L |
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+---------+---------+---------+---------+
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0 16 32 48
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words [0] [1] [2] */
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static parameter
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makelongparameter (ULONGLONG val, int start, int end)
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{
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parameter p;
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p.val = (dwordU) EXTRACT(val, 48 - end, end - start);
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p.nbits = end - start;
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return p;
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}
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/* Build a mask of the instruction's 'constant' opcode,
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based on the instruction's printing flags. */
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static unsigned long
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build_mask (void)
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{
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unsigned int print_flags;
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unsigned long mask;
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print_flags = instruction->flags & FMT_CRX;
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switch (print_flags)
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{
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case FMT_1:
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mask = 0xF0F00000;
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break;
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case FMT_2:
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mask = 0xFFF0FF00;
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break;
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case FMT_3:
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mask = 0xFFF00F00;
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break;
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case FMT_4:
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mask = 0xFFF0F000;
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break;
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case FMT_5:
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mask = 0xFFF0FFF0;
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break;
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default:
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mask = SBM(instruction->match_bits);
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break;
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}
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return mask;
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}
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/* Search for a matching opcode. Return 1 for success, 0 for failure. */
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static int
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match_opcode (void)
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{
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unsigned long mask;
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/* The instruction 'constant' opcode doewsn't exceed 32 bits. */
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unsigned long doubleWord = words[1] + (words[0] << 16);
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/* Start searching from end of instruction table. */
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instruction = &crx_instruction[NUMOPCODES - 2];
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/* Loop over instruction table until a full match is found. */
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while (instruction >= crx_instruction)
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{
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mask = build_mask ();
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if ((doubleWord & mask) == BIN(instruction->match, instruction->match_bits))
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return 1;
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else
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instruction--;
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}
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return 0;
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}
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/* Set the proper parameter value for different type of arguments. */
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static void
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make_argument (argument * a, int start_bits)
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{
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int inst_bit_size, total_size;
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parameter p;
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if ((instruction->size == 3) && a->size >= 16)
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inst_bit_size = 48;
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else
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inst_bit_size = 32;
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switch (a->type)
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{
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case arg_copr:
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case arg_copsr:
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p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size),
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inst_bit_size - start_bits);
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a->cr = p.val;
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break;
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case arg_r:
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p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size),
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inst_bit_size - start_bits);
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a->r = p.val;
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break;
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case arg_ic:
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p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size),
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inst_bit_size - start_bits);
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if ((p.nbits == 4) && cst4flag)
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{
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if (IS_INSN_TYPE (CMPBR_INS) && (p.val == ESCAPE_16_BIT))
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{
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/* A special case, where the value is actually stored
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in the last 4 bits. */
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p = makelongparameter (allWords, 44, 48);
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/* The size of the instruction should be incremented. */
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size_changed = 1;
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}
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if (p.val == 6)
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p.val = -1;
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else if (p.val == 13)
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p.val = 48;
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else if (p.val == 5)
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p.val = -4;
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else if (p.val == 10)
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p.val = 32;
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else if (p.val == 11)
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p.val = 20;
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else if (p.val == 9)
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p.val = 16;
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}
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a->constant = p.val;
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break;
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case arg_icr:
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a->scale = 0;
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total_size = a->size + 10; /* sizeof(rbase + ridx + scl2) = 10. */
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p = makelongparameter (allWords, inst_bit_size - total_size,
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inst_bit_size - (total_size - 4));
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a->r = p.val;
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p = makelongparameter (allWords, inst_bit_size - (total_size - 4),
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inst_bit_size - (total_size - 8));
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a->i_r = p.val;
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p = makelongparameter (allWords, inst_bit_size - (total_size - 8),
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inst_bit_size - (total_size - 10));
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a->scale = p.val;
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p = makelongparameter (allWords, inst_bit_size - (total_size - 10),
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inst_bit_size);
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a->constant = p.val;
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break;
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case arg_rbase:
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p = makelongparameter (allWords, inst_bit_size - (start_bits + 4),
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inst_bit_size - start_bits);
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a->r = p.val;
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break;
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case arg_cr:
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if (a->size <= 8)
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{
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p = makelongparameter (allWords, inst_bit_size - (start_bits + 4),
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inst_bit_size - start_bits);
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a->r = p.val;
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/* Case for opc4 r dispu rbase. */
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p = makelongparameter (allWords, inst_bit_size - (start_bits + 8),
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inst_bit_size - (start_bits + 4));
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}
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else
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{
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/* The 'rbase' start_bits is always relative to a 32-bit data type. */
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p = makelongparameter (allWords, 32 - (start_bits + 4),
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32 - start_bits);
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a->r = p.val;
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p = makelongparameter (allWords, 32 - start_bits,
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inst_bit_size);
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}
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if ((p.nbits == 4) && cst4flag)
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{
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if (instruction->flags & DISPUW4)
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p.val *= 2;
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else if (instruction->flags & DISPUD4)
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p.val *= 4;
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}
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a->constant = p.val;
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break;
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case arg_c:
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p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size),
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inst_bit_size - start_bits);
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a->constant = p.val;
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break;
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default:
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break;
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}
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}
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/* Print a single argument. */
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static void
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print_arg (argument *a, struct disassemble_info *info)
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{
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LONGLONG longdisp, mask;
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char sign_flag;
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int op_index = 0;
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char string[200];
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PTR stream = info->stream;
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fprintf_ftype func = info->fprintf_func;
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switch (a->type)
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{
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case arg_copr:
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func (stream, "%s", getcopregname (a->cr, CRX_C_REGTYPE));
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break;
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case arg_copsr:
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func (stream, "%s", getcopregname (a->cr, CRX_CS_REGTYPE));
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break;
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case arg_r:
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if (IS_INSN_MNEMONIC ("mtpr") || IS_INSN_MNEMONIC ("mfpr"))
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func (stream, "%s", getprocregname (a->r));
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else
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func (stream, "%s", getregname (a->r));
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break;
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case arg_ic:
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if (IS_INSN_MNEMONIC ("excp"))
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func (stream, "%s", gettrapstring (a->constant));
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else if (IS_INSN_MNEMONIC ("cinv"))
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func (stream, "%s", getcinvstring (a->constant));
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else if (INST_HAS_REG_LIST)
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{
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REG_ARG_TYPE reg_arg_type = IS_INSN_TYPE (COP_REG_INS) ?
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COP_ARG : IS_INSN_TYPE (COPS_REG_INS) ?
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COPS_ARG : (instruction->flags & USER_REG) ?
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USER_REG_ARG : REG_ARG;
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|
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if ((reg_arg_type == COP_ARG) || (reg_arg_type == COPS_ARG))
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{
|
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/* Check for proper argument number. */
|
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if (processing_argument_number == 2)
|
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{
|
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getregliststring (a->constant, string, reg_arg_type);
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func (stream, "%s", string);
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}
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else
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func (stream, "$0x%x", a->constant);
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}
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else
|
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{
|
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getregliststring (a->constant, string, reg_arg_type);
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func (stream, "%s", string);
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}
|
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}
|
|
else
|
|
func (stream, "$0x%x", a->constant);
|
|
break;
|
|
|
|
case arg_icr:
|
|
func (stream, "0x%x(%s,%s,%d)", a->constant, getregname (a->r),
|
|
getregname (a->i_r), powerof2 (a->scale));
|
|
break;
|
|
|
|
case arg_rbase:
|
|
func (stream, "(%s)", getregname (a->r));
|
|
break;
|
|
|
|
case arg_cr:
|
|
func (stream, "0x%x(%s)", a->constant, getregname (a->r));
|
|
|
|
if (IS_INSN_TYPE (LD_STOR_INS_INC))
|
|
func (stream, "+");
|
|
break;
|
|
|
|
case arg_c:
|
|
/* Removed the *2 part as because implicit zeros are no more required.
|
|
Have to fix this as this needs a bit of extension in terms of branchins.
|
|
Have to add support for cmp and branch instructions. */
|
|
if (IS_INSN_TYPE (BRANCH_INS) || IS_INSN_MNEMONIC ("bal")
|
|
|| IS_INSN_TYPE (CMPBR_INS) || IS_INSN_TYPE (DCR_BRANCH_INS)
|
|
|| IS_INSN_TYPE (COP_BRANCH_INS))
|
|
{
|
|
func (stream, "%c", '*');
|
|
longdisp = a->constant;
|
|
longdisp <<= 1;
|
|
sign_flag = '+';
|
|
|
|
switch (a->size)
|
|
{
|
|
case 8:
|
|
case 16:
|
|
case 24:
|
|
case 32:
|
|
mask = ((LONGLONG)1 << a->size) - 1;
|
|
if (longdisp & ((LONGLONG)1 << a->size))
|
|
{
|
|
sign_flag = '-';
|
|
longdisp = ~(longdisp) + 1;
|
|
}
|
|
a->constant = (unsigned long int) (longdisp & mask);
|
|
break;
|
|
default:
|
|
func (stream,
|
|
"Wrong offset used in branch/bal instruction");
|
|
break;
|
|
}
|
|
|
|
func (stream, "%c", sign_flag);
|
|
}
|
|
/* For branch Neq instruction it is 2*offset + 2. */
|
|
if (IS_INSN_TYPE (BRANCH_NEQ_INS))
|
|
a->constant = 2 * a->constant + 2;
|
|
if (IS_INSN_TYPE (LD_STOR_INS_INC)
|
|
|| IS_INSN_TYPE (LD_STOR_INS)
|
|
|| IS_INSN_TYPE (STOR_IMM_INS)
|
|
|| IS_INSN_TYPE (CSTBIT_INS))
|
|
{
|
|
op_index = instruction->flags & REVERSE_MATCH ? 0 : 1;
|
|
if (instruction->operands[op_index].op_type == abs16)
|
|
a->constant |= 0xFFFF0000;
|
|
}
|
|
func (stream, "0x%x", a->constant);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Print all the arguments of CURRINSN instruction. */
|
|
|
|
static void
|
|
print_arguments (ins *currInsn, struct disassemble_info *info)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < currInsn->nargs; i++)
|
|
{
|
|
processing_argument_number = i;
|
|
|
|
print_arg (&currInsn->arg[i], info);
|
|
|
|
if (i != currInsn->nargs - 1)
|
|
info->fprintf_func (info->stream, ", ");
|
|
}
|
|
}
|
|
|
|
/* Build the instruction's arguments. */
|
|
|
|
static void
|
|
make_instruction (void)
|
|
{
|
|
int i;
|
|
unsigned int temp_value, shift;
|
|
argument a;
|
|
|
|
for (i = 0; i < currInsn.nargs; i++)
|
|
{
|
|
a.type = getargtype (instruction->operands[i].op_type);
|
|
if (instruction->operands[i].op_type == cst4
|
|
|| instruction->operands[i].op_type == rbase_cst4)
|
|
cst4flag = 1;
|
|
a.size = getbits (instruction->operands[i].op_type);
|
|
shift = instruction->operands[i].shift;
|
|
|
|
make_argument (&a, shift);
|
|
currInsn.arg[i] = a;
|
|
}
|
|
|
|
/* Calculate instruction size (in bytes). */
|
|
currInsn.size = instruction->size + (size_changed ? 1 : 0);
|
|
currInsn.size *= 2;
|
|
|
|
/* Swapping first and second arguments. */
|
|
if (IS_INSN_TYPE (COP_BRANCH_INS))
|
|
{
|
|
temp_value = currInsn.arg[0].constant;
|
|
currInsn.arg[0].constant = currInsn.arg[1].constant;
|
|
currInsn.arg[1].constant = temp_value;
|
|
}
|
|
}
|
|
|
|
/* Retrieve a single word from a given memory address. */
|
|
|
|
static wordU
|
|
get_word_at_PC (bfd_vma memaddr, struct disassemble_info *info)
|
|
{
|
|
bfd_byte buffer[4];
|
|
int status;
|
|
wordU insn = 0;
|
|
|
|
status = info->read_memory_func (memaddr, buffer, 2, info);
|
|
|
|
if (status == 0)
|
|
insn = (wordU) bfd_getl16 (buffer);
|
|
|
|
return insn;
|
|
}
|
|
|
|
/* Retrieve multiple words (3) from a given memory address. */
|
|
|
|
static void
|
|
get_words_at_PC (bfd_vma memaddr, struct disassemble_info *info)
|
|
{
|
|
int i;
|
|
bfd_vma mem;
|
|
|
|
for (i = 0, mem = memaddr; i < 3; i++, mem += 2)
|
|
words[i] = get_word_at_PC (mem, info);
|
|
|
|
allWords =
|
|
((ULONGLONG) words[0] << 32) + ((unsigned long) words[1] << 16) + words[2];
|
|
}
|
|
|
|
/* Prints the instruction by calling print_arguments after proper matching. */
|
|
|
|
int
|
|
print_insn_crx (memaddr, info)
|
|
bfd_vma memaddr;
|
|
struct disassemble_info *info;
|
|
{
|
|
int is_decoded; /* Nonzero means instruction has a match. */
|
|
|
|
/* Initialize global variables. */
|
|
cst4flag = 0;
|
|
size_changed = 0;
|
|
|
|
/* Retrieve the encoding from current memory location. */
|
|
get_words_at_PC (memaddr, info);
|
|
/* Find a matching opcode in table. */
|
|
is_decoded = match_opcode ();
|
|
/* If found, print the instruction's mnemonic and arguments. */
|
|
if (is_decoded > 0 && (words[0] << 16 || words[1]) != 0)
|
|
{
|
|
info->fprintf_func (info->stream, "%s", instruction->mnemonic);
|
|
if ((currInsn.nargs = get_number_of_operands ()) != 0)
|
|
info->fprintf_func (info->stream, "\t");
|
|
make_instruction ();
|
|
print_arguments (&currInsn, info);
|
|
return currInsn.size;
|
|
}
|
|
|
|
/* No match found. */
|
|
info->fprintf_func (info->stream,"%s ",ILLEGAL);
|
|
return 2;
|
|
}
|