180fd370b1
spot different prompts at run-time, so as to avoid having target
specific versions of gdb. This is a pending TODO.
Fri Sep 1 08:25:50 1995 James G. Smith <jsmith@beauty.cygnus.com>
* configure (mips64*vr4300*-*-elf): Support added.
* remote-mips.c (mips_readchar): Change to allow build-time prompt
string.
* config/mips/tm-mips.h: Added TARGET_MONITOR_PROMPT.
* config/mips/{vr4300.mt, vr4300el.mt, tm-vr4300.h,
tm-vr4300el.h}: Added.
499 lines
18 KiB
C
499 lines
18 KiB
C
/* Definitions to make GDB run on a mips box under 4.3bsd.
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Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995
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Free Software Foundation, Inc.
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Contributed by Per Bothner (bothner@cs.wisc.edu) at U.Wisconsin
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and by Alessandro Forin (af@cs.cmu.edu) at CMU..
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include <bfd.h>
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#include "coff/sym.h" /* Needed for PDR below. */
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#include "coff/symconst.h"
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#if !defined (TARGET_BYTE_ORDER)
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#define TARGET_BYTE_ORDER LITTLE_ENDIAN
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#endif
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#if !defined (GDB_TARGET_IS_MIPS64)
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#define GDB_TARGET_IS_MIPS64 0
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#endif
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/* CYGNUS LOCAL jsmith */
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#if !defined (TARGET_MONITOR_PROMPT)
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#define TARGET_MONITOR_PROMPT { '<', 'I', 'D', 'T', '>' }
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#endif
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/* END CYGNUS LOCAL */
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/* Floating point is IEEE compliant */
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#define IEEE_FLOAT
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/* Some MIPS boards are provided both with and without a floating
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point coprocessor. The MIPS R4650 chip has only single precision
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floating point. We provide a user settable variable to tell gdb
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what type of floating point to use. */
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enum mips_fpu_type
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{
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MIPS_FPU_DOUBLE, /* Full double precision floating point. */
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MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
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MIPS_FPU_NONE /* No floating point. */
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};
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extern enum mips_fpu_type mips_fpu;
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/* The name of the usual type of MIPS processor that is in the target
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system. */
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#define DEFAULT_MIPS_TYPE "generic"
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/* Offset from address of function to start of its code.
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Zero on most machines. */
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#define FUNCTION_START_OFFSET 0
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/* Advance PC across any function entry prologue instructions
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to reach some "real" code. */
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#define SKIP_PROLOGUE(pc) pc = mips_skip_prologue (pc, 0)
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extern CORE_ADDR mips_skip_prologue PARAMS ((CORE_ADDR addr, int lenient));
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/* Return non-zero if PC points to an instruction which will cause a step
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to execute both the instruction at PC and an instruction at PC+4. */
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#define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))
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/* Immediately after a function call, return the saved pc.
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Can't always go through the frames for this because on some machines
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the new frame is not set up until the new function executes
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some instructions. */
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#define SAVED_PC_AFTER_CALL(frame) read_register(RA_REGNUM)
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/* Are we currently handling a signal */
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extern int in_sigtramp PARAMS ((CORE_ADDR, char *));
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#define IN_SIGTRAMP(pc, name) in_sigtramp(pc, name)
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/* Stack grows downward. */
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#define INNER_THAN <
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#define BIG_ENDIAN 4321
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#if TARGET_BYTE_ORDER == BIG_ENDIAN
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#define BREAKPOINT {0, 0x5, 0, 0xd}
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#else
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#define BREAKPOINT {0xd, 0, 0x5, 0}
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#endif
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/* Amount PC must be decremented by after a breakpoint.
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This is often the number of bytes in BREAKPOINT
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but not always. */
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#define DECR_PC_AFTER_BREAK 0
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/* Nonzero if instruction at PC is a return instruction. "j ra" on mips. */
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#define ABOUT_TO_RETURN(pc) (read_memory_integer (pc, 4) == 0x3e00008)
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/* Say how long (ordinary) registers are. This is a piece of bogosity
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used in push_word and a few other places; REGISTER_RAW_SIZE is the
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real way to know how big a register is. */
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#define REGISTER_SIZE 4
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/* The size of a register. This is predefined in tm-mips64.h. We
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can't use REGISTER_SIZE because that is used for various other
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things. */
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#ifndef MIPS_REGSIZE
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#define MIPS_REGSIZE 4
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#endif
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/* Number of machine registers */
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#define NUM_REGS 90
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/* Initializer for an array of names of registers.
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There should be NUM_REGS strings in this initializer. */
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#define REGISTER_NAMES \
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{ "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
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"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
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"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
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"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", \
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"sr", "lo", "hi", "bad", "cause","pc", \
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"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
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"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
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"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",\
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"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",\
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"fsr", "fir", "fp", "", \
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"", "", "", "", "", "", "", "", \
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"", "", "", "", "", "", "", "", \
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}
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/* Register numbers of various important registers.
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Note that some of these values are "real" register numbers,
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and correspond to the general registers of the machine,
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and some are "phony" register numbers which are too large
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to be actual register numbers as far as the user is concerned
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but do serve to get the desired values when passed to read_register. */
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#define ZERO_REGNUM 0 /* read-only register, always 0 */
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#define V0_REGNUM 2 /* Function integer return value */
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#define A0_REGNUM 4 /* Loc of first arg during a subr call */
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#define SP_REGNUM 29 /* Contains address of top of stack */
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#define RA_REGNUM 31 /* Contains return address value */
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#define PS_REGNUM 32 /* Contains processor status */
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#define HI_REGNUM 34 /* Multiple/divide temp */
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#define LO_REGNUM 33 /* ... */
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#define BADVADDR_REGNUM 35 /* bad vaddr for addressing exception */
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#define CAUSE_REGNUM 36 /* describes last exception */
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#define PC_REGNUM 37 /* Contains program counter */
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#define FP0_REGNUM 38 /* Floating point register 0 (single float) */
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#define FCRCS_REGNUM 70 /* FP control/status */
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#define FCRIR_REGNUM 71 /* FP implementation/revision */
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#define FP_REGNUM 72 /* Pseudo register that contains true address of executing stack frame */
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#define FIRST_EMBED_REGNUM 74 /* First CP0 register for embedded use */
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#define PRID_REGNUM 89 /* Processor ID */
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#define LAST_EMBED_REGNUM 89 /* Last one */
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/* Define DO_REGISTERS_INFO() to do machine-specific formatting
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of register dumps. */
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#define DO_REGISTERS_INFO(_regnum, fp) mips_do_registers_info(_regnum, fp)
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/* Total amount of space needed to store our copies of the machine's
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register state, the array `registers'. */
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#define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE)
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/* Index within `registers' of the first byte of the space for
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register N. */
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#define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE)
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/* Number of bytes of storage in the actual machine representation
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for register N. On mips, all regs are the same size. */
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#define REGISTER_RAW_SIZE(N) MIPS_REGSIZE
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/* Number of bytes of storage in the program's representation
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for register N. On mips, all regs are the same size. */
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#define REGISTER_VIRTUAL_SIZE(N) MIPS_REGSIZE
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/* Largest value REGISTER_RAW_SIZE can have. */
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#define MAX_REGISTER_RAW_SIZE 8
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/* Largest value REGISTER_VIRTUAL_SIZE can have. */
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#define MAX_REGISTER_VIRTUAL_SIZE 8
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/* Return the GDB type object for the "standard" data type
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of data in register N. */
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#ifndef REGISTER_VIRTUAL_TYPE
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#define REGISTER_VIRTUAL_TYPE(N) \
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(((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32) \
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? builtin_type_float : builtin_type_int)
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#endif
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#if HOST_BYTE_ORDER == BIG_ENDIAN
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/* All mips targets store doubles in a register pair with the least
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significant register in the lower numbered register.
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If the host is big endian, double register values need conversion between
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memory and register formats. */
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#define REGISTER_CONVERT_TO_TYPE(n, type, buffer) \
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do {if ((n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32 && \
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TYPE_CODE(type) == TYPE_CODE_FLT && TYPE_LENGTH(type) == 8) { \
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char __temp[4]; \
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memcpy (__temp, ((char *)(buffer))+4, 4); \
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memcpy (((char *)(buffer))+4, (buffer), 4); \
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memcpy (((char *)(buffer)), __temp, 4); }} while (0)
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#define REGISTER_CONVERT_FROM_TYPE(n, type, buffer) \
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do {if ((n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32 && \
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TYPE_CODE(type) == TYPE_CODE_FLT && TYPE_LENGTH(type) == 8) { \
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char __temp[4]; \
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memcpy (__temp, ((char *)(buffer))+4, 4); \
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memcpy (((char *)(buffer))+4, (buffer), 4); \
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memcpy (((char *)(buffer)), __temp, 4); }} while (0)
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#endif
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/* Store the address of the place in which to copy the structure the
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subroutine will return. Handled by mips_push_arguments. */
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#define STORE_STRUCT_RETURN(addr, sp) /**/
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/* Extract from an array REGBUF containing the (raw) register state
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a function return value of type TYPE, and copy that, in virtual format,
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into VALBUF. XXX floats */
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#define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
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mips_extract_return_value(TYPE, REGBUF, VALBUF)
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/* Write into appropriate registers a function return value
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of type TYPE, given in virtual format. */
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#define STORE_RETURN_VALUE(TYPE,VALBUF) \
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mips_store_return_value(TYPE, VALBUF)
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/* Extract from an array REGBUF containing the (raw) register state
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the address in which a function should return its structure value,
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as a CORE_ADDR (or an expression that can be used as one). */
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/* The address is passed in a0 upon entry to the function, but when
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the function exits, the compiler has copied the value to v0. This
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convention is specified by the System V ABI, so I think we can rely
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on it. */
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#define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
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(extract_address (REGBUF + REGISTER_BYTE (V0_REGNUM), \
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REGISTER_RAW_SIZE (V0_REGNUM)))
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/* Structures are returned by ref in extra arg0 */
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#define USE_STRUCT_CONVENTION(gcc_p, type) 1
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/* Describe the pointer in each stack frame to the previous stack frame
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(its caller). */
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/* FRAME_CHAIN takes a frame's nominal address
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and produces the frame's chain-pointer. */
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#define FRAME_CHAIN(thisframe) (CORE_ADDR) mips_frame_chain (thisframe)
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/* Define other aspects of the stack frame. */
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/* A macro that tells us whether the function invocation represented
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by FI does not have a frame on the stack associated with it. If it
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does not, FRAMELESS is set to 1, else 0. */
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/* We handle this differently for mips, and maybe we should not */
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#define FRAMELESS_FUNCTION_INVOCATION(FI, FRAMELESS) {(FRAMELESS) = 0;}
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/* Saved Pc. */
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#define FRAME_SAVED_PC(FRAME) (mips_frame_saved_pc(FRAME))
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#define FRAME_ARGS_ADDRESS(fi) (fi)->frame
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#define FRAME_LOCALS_ADDRESS(fi) (fi)->frame
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/* Return number of args passed to a frame.
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Can return -1, meaning no way to tell. */
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#define FRAME_NUM_ARGS(num, fi) (num = mips_frame_num_args(fi))
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/* Return number of bytes at start of arglist that are not really args. */
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#define FRAME_ARGS_SKIP 0
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/* Put here the code to store, into a struct frame_saved_regs,
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the addresses of the saved registers of frame described by FRAME_INFO.
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This includes special registers such as pc and fp saved in special
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ways in the stack frame. sp is even more special:
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the address we return for it IS the sp for the next frame. */
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#define FRAME_FIND_SAVED_REGS(frame_info, frame_saved_regs) \
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do { \
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if ((frame_info)->saved_regs == NULL) \
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mips_find_saved_regs (frame_info); \
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(frame_saved_regs) = *(frame_info)->saved_regs; \
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(frame_saved_regs).regs[SP_REGNUM] = (frame_info)->frame; \
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} while (0)
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/* Things needed for making the inferior call functions. */
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/* Stack has strict alignment. However, use PUSH_ARGUMENTS
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to take care of it. */
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/*#define STACK_ALIGN(addr) (((addr)+3)&~3)*/
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#define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
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sp = mips_push_arguments(nargs, args, sp, struct_return, struct_addr)
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/* Push an empty stack frame, to record the current PC, etc. */
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#define PUSH_DUMMY_FRAME mips_push_dummy_frame()
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/* Discard from the stack the innermost frame, restoring all registers. */
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#define POP_FRAME mips_pop_frame()
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#define MK_OP(op,rs,rt,offset) (((op)<<26)|((rs)<<21)|((rt)<<16)|(offset))
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#ifndef OP_LDFPR
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#define OP_LDFPR 061 /* lwc1 */
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#endif
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#ifndef OP_LDGPR
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#define OP_LDGPR 043 /* lw */
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#endif
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#define CALL_DUMMY_SIZE (16*4)
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#define Dest_Reg 2
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#define CALL_DUMMY {\
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MK_OP(0,RA_REGNUM,0,8), /* jr $ra # Fake ABOUT_TO_RETURN ...*/\
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0, /* nop # ... to stop raw backtrace*/\
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0x27bd0000, /* addu sp,?0 # Pseudo prologue */\
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/* Start here; reload FP regs, then GP regs: */\
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MK_OP(OP_LDFPR,SP_REGNUM,12,0 ), /* l[wd]c1 $f12,0(sp) */\
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MK_OP(OP_LDFPR,SP_REGNUM,13, MIPS_REGSIZE), /* l[wd]c1 $f13,{4,8}(sp) */\
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MK_OP(OP_LDFPR,SP_REGNUM,14,2*MIPS_REGSIZE), /* l[wd]c1 $f14,{8,16}(sp) */\
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MK_OP(OP_LDFPR,SP_REGNUM,15,3*MIPS_REGSIZE), /* l[wd]c1 $f15,{12,24}(sp) */\
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MK_OP(OP_LDGPR,SP_REGNUM, 4,0 ), /* l[wd] $r4,0(sp) */\
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MK_OP(OP_LDGPR,SP_REGNUM, 5, MIPS_REGSIZE), /* l[wd] $r5,{4,8}(sp) */\
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MK_OP(OP_LDGPR,SP_REGNUM, 6,2*MIPS_REGSIZE), /* l[wd] $r6,{8,16}(sp) */\
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MK_OP(OP_LDGPR,SP_REGNUM, 7,3*MIPS_REGSIZE), /* l[wd] $r7,{12,24}(sp) */\
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(017<<26)| (Dest_Reg << 16), /* lui $r31,<target upper 16 bits>*/\
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MK_OP(13,Dest_Reg,Dest_Reg,0), /* ori $r31,$r31,<lower 16 bits>*/ \
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(Dest_Reg<<21) | (31<<11) | 9, /* jalr $r31 */\
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MK_OP(OP_LDGPR,SP_REGNUM, 7,3*MIPS_REGSIZE), /* l[wd] $r7,{12,24}(sp) */\
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0x5000d, /* bpt */\
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}
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#define CALL_DUMMY_START_OFFSET 12
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#define CALL_DUMMY_BREAKPOINT_OFFSET (CALL_DUMMY_START_OFFSET + (12 * 4))
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/* Insert the specified number of args and function address
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into a call sequence of the above form stored at DUMMYNAME. */
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/* For big endian mips machines we need to switch the order of the
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words with a floating-point value (it was already coerced to a double
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by mips_push_arguments). */
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#define FIX_CALL_DUMMY(dummyname, start_sp, fun, nargs, args, rettype, gcc_p) \
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do \
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{ \
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store_unsigned_integer \
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(dummyname + 11 * 4, 4, \
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(extract_unsigned_integer (dummyname + 11 * 4, 4) \
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| (((fun) >> 16) & 0xffff))); \
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store_unsigned_integer \
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(dummyname + 12 * 4, 4, \
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(extract_unsigned_integer (dummyname + 12 * 4, 4) \
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| ((fun) & 0xffff))); \
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if (mips_fpu == MIPS_FPU_NONE) \
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{ \
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store_unsigned_integer (dummyname + 3 * 4, 4, \
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(unsigned LONGEST) 0); \
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store_unsigned_integer (dummyname + 4 * 4, 4, \
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(unsigned LONGEST) 0); \
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store_unsigned_integer (dummyname + 5 * 4, 4, \
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(unsigned LONGEST) 0); \
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store_unsigned_integer (dummyname + 6 * 4, 4, \
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(unsigned LONGEST) 0); \
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} \
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else if (mips_fpu == MIPS_FPU_SINGLE) \
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{ \
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/* This isn't right. mips_push_arguments will call \
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value_arg_coerce, which will convert all float arguments \
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to doubles. If the function prototype is float, though, \
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it will be expecting a float argument in a float \
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register. */ \
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store_unsigned_integer (dummyname + 4 * 4, 4, \
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(unsigned LONGEST) 0); \
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store_unsigned_integer (dummyname + 6 * 4, 4, \
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(unsigned LONGEST) 0); \
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} \
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else if (TARGET_BYTE_ORDER == BIG_ENDIAN \
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&& ! GDB_TARGET_IS_MIPS64) \
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{ \
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if (nargs > 0 \
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&& TYPE_CODE (VALUE_TYPE (args[0])) == TYPE_CODE_FLT) \
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{ \
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if (TYPE_LENGTH (VALUE_TYPE (args[0])) > 8) \
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error ("floating point value too large to pass to function");\
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store_unsigned_integer \
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(dummyname + 3 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 12, 4));\
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store_unsigned_integer \
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(dummyname + 4 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 13, 0));\
|
||
} \
|
||
if (nargs > 1 \
|
||
&& TYPE_CODE (VALUE_TYPE (args[1])) == TYPE_CODE_FLT) \
|
||
{ \
|
||
if (TYPE_LENGTH (VALUE_TYPE (args[1])) > 8) \
|
||
error ("floating point value too large to pass to function");\
|
||
store_unsigned_integer \
|
||
(dummyname + 5 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 14, 12));\
|
||
store_unsigned_integer \
|
||
(dummyname + 6 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 15, 8));\
|
||
} \
|
||
} \
|
||
} \
|
||
while (0)
|
||
|
||
/* There's a mess in stack frame creation. See comments in blockframe.c
|
||
near reference to INIT_FRAME_PC_FIRST. */
|
||
|
||
#define INIT_FRAME_PC(fromleaf, prev) /* nada */
|
||
|
||
#define INIT_FRAME_PC_FIRST(fromleaf, prev) \
|
||
(prev)->pc = ((fromleaf) ? SAVED_PC_AFTER_CALL ((prev)->next) : \
|
||
(prev)->next ? FRAME_SAVED_PC ((prev)->next) : read_pc ());
|
||
|
||
/* Special symbol found in blocks associated with routines. We can hang
|
||
mips_extra_func_info_t's off of this. */
|
||
|
||
#define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__"
|
||
|
||
/* Specific information about a procedure.
|
||
This overlays the MIPS's PDR records,
|
||
mipsread.c (ab)uses this to save memory */
|
||
|
||
typedef struct mips_extra_func_info {
|
||
long numargs; /* number of args to procedure (was iopt) */
|
||
PDR pdr; /* Procedure descriptor record */
|
||
} *mips_extra_func_info_t;
|
||
|
||
#define EXTRA_FRAME_INFO \
|
||
mips_extra_func_info_t proc_desc; \
|
||
int num_args;\
|
||
struct frame_saved_regs *saved_regs;
|
||
|
||
#define INIT_EXTRA_FRAME_INFO(fromleaf, fci) init_extra_frame_info(fci)
|
||
|
||
#define PRINT_EXTRA_FRAME_INFO(fi) \
|
||
{ \
|
||
if (fi && fi->proc_desc && fi->proc_desc->pdr.framereg < NUM_REGS) \
|
||
printf_filtered (" frame pointer is at %s+%d\n", \
|
||
reg_names[fi->proc_desc->pdr.framereg], \
|
||
fi->proc_desc->pdr.frameoffset); \
|
||
}
|
||
|
||
/* It takes two values to specify a frame on the MIPS.
|
||
|
||
In fact, the *PC* is the primary value that sets up a frame. The
|
||
PC is looked up to see what function it's in; symbol information
|
||
from that function tells us which register is the frame pointer
|
||
base, and what offset from there is the "virtual frame pointer".
|
||
(This is usually an offset from SP.) On most non-MIPS machines,
|
||
the primary value is the SP, and the PC, if needed, disambiguates
|
||
multiple functions with the same SP. But on the MIPS we can't do
|
||
that since the PC is not stored in the same part of the frame every
|
||
time. This does not seem to be a very clever way to set up frames,
|
||
but there is nothing we can do about that). */
|
||
|
||
#define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv)
|
||
extern struct frame_info *setup_arbitrary_frame PARAMS ((int, CORE_ADDR *));
|
||
|
||
/* Convert a dbx stab register number (from `r' declaration) to a gdb REGNUM */
|
||
|
||
#define STAB_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-38)
|
||
|
||
/* Convert a ecoff register number to a gdb REGNUM */
|
||
|
||
#define ECOFF_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-32)
|