2b4bc832a7
This port already was storing its cpu state in the sim_cpu structure, so converting it over was pretty easy. It is allocating memory itself still, but we'll fix that up in the future at some point.
787 lines
17 KiB
C
787 lines
17 KiB
C
/* Simulator for Xilinx MicroBlaze processor
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Copyright 2009-2015 Free Software Foundation, Inc.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see <http://www.gnu.org/licenses/>. */
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#include "config.h"
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#include <signal.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#include "bfd.h"
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#include "gdb/callback.h"
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#include "libiberty.h"
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#include "gdb/remote-sim.h"
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#include "sim-main.h"
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#include "sim-options.h"
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#include "microblaze-dis.h"
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#define target_big_endian (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
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static unsigned long
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microblaze_extract_unsigned_integer (unsigned char *addr, int len)
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{
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unsigned long retval;
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unsigned char *p;
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unsigned char *startaddr = (unsigned char *)addr;
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unsigned char *endaddr = startaddr + len;
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if (len > (int) sizeof (unsigned long))
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printf ("That operation is not available on integers of more than "
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"%zu bytes.", sizeof (unsigned long));
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/* Start at the most significant end of the integer, and work towards
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the least significant. */
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retval = 0;
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if (!target_big_endian)
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{
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for (p = endaddr; p > startaddr;)
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retval = (retval << 8) | * -- p;
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}
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else
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{
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for (p = startaddr; p < endaddr;)
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retval = (retval << 8) | * p ++;
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}
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return retval;
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}
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static void
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microblaze_store_unsigned_integer (unsigned char *addr, int len,
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unsigned long val)
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{
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unsigned char *p;
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unsigned char *startaddr = (unsigned char *)addr;
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unsigned char *endaddr = startaddr + len;
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if (!target_big_endian)
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{
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for (p = startaddr; p < endaddr;)
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{
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*p++ = val & 0xff;
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val >>= 8;
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}
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}
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else
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{
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for (p = endaddr; p > startaddr;)
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{
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*--p = val & 0xff;
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val >>= 8;
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}
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}
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}
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/* TODO: Convert to common tracing framework. */
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static int issue_messages = 0;
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static void /* INLINE */
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wbat (SIM_CPU *cpu, word x, word v)
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{
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if (((uword)x) >= CPU.msize)
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{
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if (issue_messages)
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fprintf (stderr, "byte write to 0x%x outside memory range\n", x);
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CPU.exception = SIGSEGV;
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}
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else
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{
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unsigned char *p = CPU.memory + x;
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p[0] = v;
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}
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}
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static void /* INLINE */
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wlat (SIM_CPU *cpu, word x, word v)
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{
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if (((uword)x) >= CPU.msize)
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{
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if (issue_messages)
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fprintf (stderr, "word write to 0x%x outside memory range\n", x);
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CPU.exception = SIGSEGV;
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}
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else
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{
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if ((x & 3) != 0)
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{
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if (issue_messages)
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fprintf (stderr, "word write to unaligned memory address: 0x%x\n", x);
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CPU.exception = SIGBUS;
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}
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else if (!target_big_endian)
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{
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unsigned char *p = CPU.memory + x;
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p[3] = v >> 24;
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p[2] = v >> 16;
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p[1] = v >> 8;
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p[0] = v;
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}
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else
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{
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unsigned char *p = CPU.memory + x;
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p[0] = v >> 24;
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p[1] = v >> 16;
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p[2] = v >> 8;
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p[3] = v;
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}
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}
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}
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static void /* INLINE */
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what (SIM_CPU *cpu, word x, word v)
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{
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if (((uword)x) >= CPU.msize)
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{
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if (issue_messages)
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fprintf (stderr, "short write to 0x%x outside memory range\n", x);
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CPU.exception = SIGSEGV;
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}
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else
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{
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if ((x & 1) != 0)
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{
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if (issue_messages)
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fprintf (stderr, "short write to unaligned memory address: 0x%x\n",
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x);
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CPU.exception = SIGBUS;
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}
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else if (!target_big_endian)
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{
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unsigned char *p = CPU.memory + x;
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p[1] = v >> 8;
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p[0] = v;
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}
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else
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{
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unsigned char *p = CPU.memory + x;
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p[0] = v >> 8;
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p[1] = v;
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}
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}
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}
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/* Read functions. */
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static int /* INLINE */
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rbat (SIM_CPU *cpu, word x)
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{
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if (((uword)x) >= CPU.msize)
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{
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if (issue_messages)
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fprintf (stderr, "byte read from 0x%x outside memory range\n", x);
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CPU.exception = SIGSEGV;
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return 0;
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}
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else
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{
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unsigned char *p = CPU.memory + x;
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return p[0];
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}
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}
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static int /* INLINE */
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rlat (SIM_CPU *cpu, word x)
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{
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if (((uword) x) >= CPU.msize)
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{
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if (issue_messages)
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fprintf (stderr, "word read from 0x%x outside memory range\n", x);
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CPU.exception = SIGSEGV;
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return 0;
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}
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else
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{
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if ((x & 3) != 0)
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{
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if (issue_messages)
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fprintf (stderr, "word read from unaligned address: 0x%x\n", x);
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CPU.exception = SIGBUS;
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return 0;
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}
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else if (! target_big_endian)
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{
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unsigned char *p = CPU.memory + x;
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return (p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0];
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}
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else
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{
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unsigned char *p = CPU.memory + x;
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return (p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3];
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}
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}
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}
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static int /* INLINE */
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rhat (SIM_CPU *cpu, word x)
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{
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if (((uword)x) >= CPU.msize)
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{
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if (issue_messages)
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fprintf (stderr, "short read from 0x%x outside memory range\n", x);
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CPU.exception = SIGSEGV;
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return 0;
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}
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else
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{
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if ((x & 1) != 0)
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{
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if (issue_messages)
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fprintf (stderr, "short read from unaligned address: 0x%x\n", x);
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CPU.exception = SIGBUS;
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return 0;
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}
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else if (!target_big_endian)
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{
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unsigned char *p = CPU.memory + x;
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return (p[1] << 8) | p[0];
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}
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else
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{
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unsigned char *p = CPU.memory + x;
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return (p[0] << 8) | p[1];
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}
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}
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}
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/* TODO: Delete all sim_size and use common memory functions. */
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/* Default to a 8 Mbyte (== 2^23) memory space. */
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static int sim_memory_size = 1 << 23;
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#define MEM_SIZE_FLOOR 64
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static void
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sim_size (SIM_CPU *cpu, int size)
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{
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sim_memory_size = size;
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CPU.msize = sim_memory_size;
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if (CPU.memory)
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free (CPU.memory);
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CPU.memory = (unsigned char *) calloc (1, CPU.msize);
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if (!CPU.memory)
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{
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if (issue_messages)
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fprintf (stderr,
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"Not enough VM for simulation of %ld bytes of RAM\n",
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CPU.msize);
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CPU.msize = 1;
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CPU.memory = (unsigned char *) calloc (1, 1);
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}
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}
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static void
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init_pointers (SIM_CPU *cpu)
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{
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if (CPU.msize != (sim_memory_size))
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sim_size (cpu, sim_memory_size);
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}
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static void
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set_initial_gprs (SIM_CPU *cpu)
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{
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int i;
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long space;
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unsigned long memsize;
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init_pointers (cpu);
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/* Set up machine just out of reset. */
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PC = 0;
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MSR = 0;
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memsize = CPU.msize / (1024 * 1024);
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if (issue_messages > 1)
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fprintf (stderr, "Simulated memory of %ld Mbytes (0x0 .. 0x%08lx)\n",
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memsize, CPU.msize - 1);
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/* Clean out the GPRs */
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for (i = 0; i < 32; i++)
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CPU.regs[i] = 0;
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CPU.insts = 0;
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CPU.cycles = 0;
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CPU.imm_enable = 0;
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}
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static int tracing = 0;
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void
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sim_resume (SIM_DESC sd, int step, int siggnal)
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{
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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int needfetch;
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word inst;
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enum microblaze_instr op;
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int memops;
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int bonus_cycles;
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int insts;
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int w;
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int cycs;
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word WLhash;
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ubyte carry;
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int imm_unsigned;
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short ra, rb, rd;
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long immword;
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uword oldpc, newpc;
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short delay_slot_enable;
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short branch_taken;
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short num_delay_slot; /* UNUSED except as reqd parameter */
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enum microblaze_instr_type insn_type;
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CPU.exception = step ? SIGTRAP : 0;
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memops = 0;
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bonus_cycles = 0;
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insts = 0;
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do
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{
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/* Fetch the initial instructions that we'll decode. */
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inst = rlat (cpu, PC & 0xFFFFFFFC);
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op = get_insn_microblaze (inst, &imm_unsigned, &insn_type,
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&num_delay_slot);
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if (op == invalid_inst)
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fprintf (stderr, "Unknown instruction 0x%04x", inst);
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if (tracing)
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fprintf (stderr, "%.4x: inst = %.4x ", PC, inst);
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rd = GET_RD;
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rb = GET_RB;
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ra = GET_RA;
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/* immword = IMM_W; */
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oldpc = PC;
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delay_slot_enable = 0;
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branch_taken = 0;
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if (op == microblaze_brk)
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CPU.exception = SIGTRAP;
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else if (inst == MICROBLAZE_HALT_INST)
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{
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CPU.exception = SIGQUIT;
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insts += 1;
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bonus_cycles++;
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}
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else
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{
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switch(op)
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{
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#define INSTRUCTION(NAME, OPCODE, TYPE, ACTION) \
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case NAME: \
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ACTION; \
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break;
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#include "microblaze.isa"
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#undef INSTRUCTION
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default:
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CPU.exception = SIGILL;
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fprintf (stderr, "ERROR: Unknown opcode\n");
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}
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/* Make R0 consistent */
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CPU.regs[0] = 0;
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/* Check for imm instr */
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if (op == imm)
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IMM_ENABLE = 1;
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else
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IMM_ENABLE = 0;
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/* Update cycle counts */
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insts ++;
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if (insn_type == memory_store_inst || insn_type == memory_load_inst)
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memops++;
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if (insn_type == mult_inst)
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bonus_cycles++;
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if (insn_type == barrel_shift_inst)
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bonus_cycles++;
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if (insn_type == anyware_inst)
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bonus_cycles++;
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if (insn_type == div_inst)
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bonus_cycles += 33;
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if ((insn_type == branch_inst || insn_type == return_inst)
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&& branch_taken)
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{
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/* Add an extra cycle for taken branches */
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bonus_cycles++;
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/* For branch instructions handle the instruction in the delay slot */
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if (delay_slot_enable)
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{
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newpc = PC;
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PC = oldpc + INST_SIZE;
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inst = rlat (cpu, PC & 0xFFFFFFFC);
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op = get_insn_microblaze (inst, &imm_unsigned, &insn_type,
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&num_delay_slot);
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if (op == invalid_inst)
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fprintf (stderr, "Unknown instruction 0x%04x", inst);
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if (tracing)
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fprintf (stderr, "%.4x: inst = %.4x ", PC, inst);
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rd = GET_RD;
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rb = GET_RB;
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ra = GET_RA;
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/* immword = IMM_W; */
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if (op == microblaze_brk)
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{
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if (issue_messages)
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fprintf (stderr, "Breakpoint set in delay slot "
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"(at address 0x%x) will not be honored\n", PC);
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/* ignore the breakpoint */
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}
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else if (insn_type == branch_inst || insn_type == return_inst)
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{
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if (issue_messages)
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fprintf (stderr, "Cannot have branch or return instructions "
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"in delay slot (at address 0x%x)\n", PC);
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CPU.exception = SIGILL;
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}
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else
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{
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switch(op)
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{
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#define INSTRUCTION(NAME, OPCODE, TYPE, ACTION) \
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case NAME: \
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ACTION; \
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break;
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#include "microblaze.isa"
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#undef INSTRUCTION
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default:
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CPU.exception = SIGILL;
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fprintf (stderr, "ERROR: Unknown opcode at 0x%x\n", PC);
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}
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/* Update cycle counts */
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insts++;
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if (insn_type == memory_store_inst
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|| insn_type == memory_load_inst)
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memops++;
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if (insn_type == mult_inst)
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bonus_cycles++;
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if (insn_type == barrel_shift_inst)
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bonus_cycles++;
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if (insn_type == anyware_inst)
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bonus_cycles++;
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if (insn_type == div_inst)
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bonus_cycles += 33;
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}
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/* Restore the PC */
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PC = newpc;
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/* Make R0 consistent */
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CPU.regs[0] = 0;
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/* Check for imm instr */
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if (op == imm)
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IMM_ENABLE = 1;
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else
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IMM_ENABLE = 0;
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}
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else
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/* no delay slot: increment cycle count */
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bonus_cycles++;
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}
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}
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if (tracing)
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fprintf (stderr, "\n");
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}
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while (!CPU.exception);
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/* Hide away the things we've cached while executing. */
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/* CPU.pc = pc; */
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CPU.insts += insts; /* instructions done ... */
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CPU.cycles += insts; /* and each takes a cycle */
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CPU.cycles += bonus_cycles; /* and extra cycles for branches */
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CPU.cycles += memops; /* and memop cycle delays */
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}
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int
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sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
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{
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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int i;
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init_pointers (cpu);
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memcpy (&CPU.memory[addr], buffer, size);
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return size;
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}
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int
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sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
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{
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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int i;
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init_pointers (cpu);
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memcpy (buffer, &CPU.memory[addr], size);
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return size;
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}
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int
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sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
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{
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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init_pointers (cpu);
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if (rn < NUM_REGS + NUM_SPECIAL && rn >= 0)
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{
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if (length == 4)
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{
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/* misalignment safe */
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long ival = microblaze_extract_unsigned_integer (memory, 4);
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if (rn < NUM_REGS)
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CPU.regs[rn] = ival;
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else
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CPU.spregs[rn-NUM_REGS] = ival;
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return 4;
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}
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else
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return 0;
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}
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else
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return 0;
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}
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|
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int
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sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
|
|
{
|
|
SIM_CPU *cpu = STATE_CPU (sd, 0);
|
|
long ival;
|
|
|
|
init_pointers (cpu);
|
|
|
|
if (rn < NUM_REGS + NUM_SPECIAL && rn >= 0)
|
|
{
|
|
if (length == 4)
|
|
{
|
|
if (rn < NUM_REGS)
|
|
ival = CPU.regs[rn];
|
|
else
|
|
ival = CPU.spregs[rn-NUM_REGS];
|
|
|
|
/* misalignment-safe */
|
|
microblaze_store_unsigned_integer (memory, 4, ival);
|
|
return 4;
|
|
}
|
|
else
|
|
return 0;
|
|
}
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
sim_stop_reason (SIM_DESC sd, enum sim_stop *reason, int *sigrc)
|
|
{
|
|
SIM_CPU *cpu = STATE_CPU (sd, 0);
|
|
|
|
if (CPU.exception == SIGQUIT)
|
|
{
|
|
*reason = sim_exited;
|
|
*sigrc = RETREG;
|
|
}
|
|
else
|
|
{
|
|
*reason = sim_stopped;
|
|
*sigrc = CPU.exception;
|
|
}
|
|
}
|
|
|
|
void
|
|
sim_info (SIM_DESC sd, int verbose)
|
|
{
|
|
SIM_CPU *cpu = STATE_CPU (sd, 0);
|
|
host_callback *callback = STATE_CALLBACK (sd);
|
|
|
|
callback->printf_filtered (callback, "\n\n# instructions executed %10d\n",
|
|
CPU.insts);
|
|
callback->printf_filtered (callback, "# cycles %10d\n",
|
|
(CPU.cycles) ? CPU.cycles+2 : 0);
|
|
}
|
|
|
|
static void
|
|
free_state (SIM_DESC sd)
|
|
{
|
|
if (STATE_MODULES (sd) != NULL)
|
|
sim_module_uninstall (sd);
|
|
sim_cpu_free_all (sd);
|
|
sim_state_free (sd);
|
|
}
|
|
|
|
SIM_DESC
|
|
sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv)
|
|
{
|
|
int i;
|
|
SIM_DESC sd = sim_state_alloc (kind, cb);
|
|
SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
|
|
|
|
/* The cpu data is kept in a separately allocated chunk of memory. */
|
|
if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
|
|
{
|
|
free_state (sd);
|
|
return 0;
|
|
}
|
|
|
|
if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
|
|
{
|
|
free_state (sd);
|
|
return 0;
|
|
}
|
|
|
|
/* getopt will print the error message so we just have to exit if this fails.
|
|
FIXME: Hmmm... in the case of gdb we need getopt to call
|
|
print_filtered. */
|
|
if (sim_parse_args (sd, argv) != SIM_RC_OK)
|
|
{
|
|
free_state (sd);
|
|
return 0;
|
|
}
|
|
|
|
/* Check for/establish the a reference program image. */
|
|
if (sim_analyze_program (sd,
|
|
(STATE_PROG_ARGV (sd) != NULL
|
|
? *STATE_PROG_ARGV (sd)
|
|
: NULL), abfd) != SIM_RC_OK)
|
|
{
|
|
free_state (sd);
|
|
return 0;
|
|
}
|
|
|
|
/* Configure/verify the target byte order and other runtime
|
|
configuration options. */
|
|
if (sim_config (sd) != SIM_RC_OK)
|
|
{
|
|
sim_module_uninstall (sd);
|
|
return 0;
|
|
}
|
|
|
|
if (sim_post_argv_init (sd) != SIM_RC_OK)
|
|
{
|
|
/* Uninstall the modules to avoid memory leaks,
|
|
file descriptor leaks, etc. */
|
|
sim_module_uninstall (sd);
|
|
return 0;
|
|
}
|
|
|
|
if (kind == SIM_OPEN_STANDALONE)
|
|
issue_messages = 1;
|
|
|
|
/* CPU specific initialization. */
|
|
for (i = 0; i < MAX_NR_PROCESSORS; ++i)
|
|
{
|
|
SIM_CPU *cpu = STATE_CPU (sd, i);
|
|
int osize = sim_memory_size;
|
|
|
|
set_initial_gprs (cpu);
|
|
|
|
/* Discard and reacquire memory -- start with a clean slate. */
|
|
sim_size (cpu, 1); /* small */
|
|
sim_size (cpu, osize); /* and back again */
|
|
}
|
|
|
|
return sd;
|
|
}
|
|
|
|
void
|
|
sim_close (SIM_DESC sd, int quitting)
|
|
{
|
|
/* Do nothing. */
|
|
}
|
|
|
|
SIM_RC
|
|
sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd, char **argv, char **env)
|
|
{
|
|
SIM_CPU *cpu = STATE_CPU (sd, 0);
|
|
|
|
PC = bfd_get_start_address (prog_bfd);
|
|
|
|
return SIM_RC_OK;
|
|
}
|
|
|
|
void
|
|
sim_do_command (SIM_DESC sd, const char *cmd)
|
|
{
|
|
SIM_CPU *cpu = STATE_CPU (sd, 0);
|
|
|
|
/* Nothing there yet; it's all an error. */
|
|
|
|
if (cmd != NULL)
|
|
{
|
|
char ** simargv = buildargv (cmd);
|
|
|
|
if (strcmp (simargv[0], "dumpmem") == 0)
|
|
{
|
|
unsigned char * p;
|
|
FILE * dumpfile;
|
|
|
|
if (simargv[1] == NULL)
|
|
fprintf (stderr, "Error: missing argument to dumpmem cmd.\n");
|
|
|
|
fprintf (stderr, "Writing dumpfile %s...",simargv[1]);
|
|
|
|
dumpfile = fopen (simargv[1], "w");
|
|
p = CPU.memory;
|
|
fwrite (p, CPU.msize-1, 1, dumpfile);
|
|
fclose (dumpfile);
|
|
|
|
fprintf (stderr, "done.\n");
|
|
}
|
|
else if (strcmp (simargv[0], "clearstats") == 0)
|
|
{
|
|
CPU.cycles = 0;
|
|
CPU.insts = 0;
|
|
}
|
|
else if (strcmp (simargv[0], "verbose") == 0)
|
|
{
|
|
issue_messages = 2;
|
|
}
|
|
else
|
|
{
|
|
fprintf (stderr,"Error: \"%s\" is not a valid M.CORE simulator command.\n",
|
|
cmd);
|
|
}
|
|
|
|
freeargv (simargv);
|
|
}
|
|
else
|
|
{
|
|
fprintf (stderr, "M.CORE sim commands: \n");
|
|
fprintf (stderr, " dumpmem <filename>\n");
|
|
fprintf (stderr, " clearstats\n");
|
|
fprintf (stderr, " verbose\n");
|
|
}
|
|
}
|