208 lines
5.7 KiB
C
208 lines
5.7 KiB
C
/* d10v.h -- Header file for D10V opcode table
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Copyright (C) 1996-2014 Free Software Foundation, Inc.
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Written by Martin Hunt (hunt@cygnus.com), Cygnus Support
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version 3,
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or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING3. If not, write to the Free
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#ifndef D10V_H
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#define D10V_H
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/* Format Specifier */
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#define FM00 0
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#define FM01 0x40000000
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#define FM10 0x80000000
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#define FM11 0xC0000000
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#define NOP 0x5e00
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#define OPCODE_DIVS 0x14002800
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/* The opcode table is an array of struct d10v_opcode. */
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struct d10v_opcode
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{
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/* The opcode name. */
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const char *name;
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/* the opcode format */
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int format;
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/* These numbers were picked so we can do if( i & SHORT_OPCODE) */
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#define SHORT_OPCODE 1
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#define LONG_OPCODE 8
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#define SHORT_2 1 /* short with 2 operands */
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#define SHORT_B 3 /* short with 8-bit branch */
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#define LONG_B 8 /* long with 16-bit branch */
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#define LONG_L 10 /* long with 3 operands */
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#define LONG_R 12 /* reserved */
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/* just a placeholder for variable-length instructions */
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/* for example, "bra" will be a fake for "bra.s" and bra.l" */
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/* which will immediately follow in the opcode table. */
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#define OPCODE_FAKE 32
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/* the number of cycles */
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int cycles;
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/* the execution unit(s) used */
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int unit;
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#define EITHER 0
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#define IU 1
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#define MU 2
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#define BOTH 3
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/* execution type; parallel or sequential */
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/* this field is used to decide if two instructions */
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/* can be executed in parallel */
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int exec_type;
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#define PARONLY 1 /* parallel only */
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#define SEQ 2 /* must be sequential */
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#define PAR 4 /* may be parallel */
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#define BRANCH_LINK 8 /* subroutine call. must be aligned */
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#define RMEM 16 /* reads memory */
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#define WMEM 32 /* writes memory */
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#define RF0 64 /* reads f0 */
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#define WF0 128 /* modifies f0 */
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#define WCAR 256 /* write Carry */
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#define BRANCH 512 /* branch, no link */
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#define ALONE 1024 /* short but pack with a NOP if on asm line alone */
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/* the opcode */
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long opcode;
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/* mask. if( (i & mask) == opcode ) then match */
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long mask;
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/* An array of operand codes. Each code is an index into the
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operand table. They appear in the order which the operands must
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appear in assembly code, and are terminated by a zero. */
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unsigned char operands[6];
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};
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/* The table itself is sorted by major opcode number, and is otherwise
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in the order in which the disassembler should consider
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instructions. */
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extern const struct d10v_opcode d10v_opcodes[];
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extern const int d10v_num_opcodes;
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/* The operands table is an array of struct d10v_operand. */
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struct d10v_operand
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{
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/* The number of bits in the operand. */
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int bits;
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/* How far the operand is left shifted in the instruction. */
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int shift;
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/* One bit syntax flags. */
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int flags;
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};
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/* Elements in the table are retrieved by indexing with values from
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the operands field of the d10v_opcodes table. */
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extern const struct d10v_operand d10v_operands[];
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/* Values defined for the flags field of a struct d10v_operand. */
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/* the operand must be an even number */
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#define OPERAND_EVEN (1)
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/* the operand must be an odd number */
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#define OPERAND_ODD (2)
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/* this is the destination register; it will be modified */
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/* this is used by the optimizer */
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#define OPERAND_DEST (4)
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/* number or symbol */
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#define OPERAND_NUM (8)
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/* address or label */
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#define OPERAND_ADDR (0x10)
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/* register */
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#define OPERAND_REG (0x20)
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/* postincrement + */
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#define OPERAND_PLUS (0x40)
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/* postdecrement - */
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#define OPERAND_MINUS (0x80)
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/* @ */
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#define OPERAND_ATSIGN (0x100)
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/* @( */
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#define OPERAND_ATPAR (0x200)
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/* accumulator 0 */
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#define OPERAND_ACC0 (0x400)
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/* accumulator 1 */
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#define OPERAND_ACC1 (0x800)
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/* f0 / f1 flag register */
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#define OPERAND_FFLAG (0x1000)
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/* c flag register */
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#define OPERAND_CFLAG (0x2000)
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/* control register */
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#define OPERAND_CONTROL (0x4000)
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/* predecrement mode '@-sp' */
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#define OPERAND_ATMINUS (0x8000)
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/* signed number */
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#define OPERAND_SIGNED (0x10000)
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/* special accumulator shifts need a 4-bit number */
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/* 1 <= x <= 16 */
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#define OPERAND_SHIFT (0x20000)
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/* general purpose register */
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#define OPERAND_GPR (0x40000)
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/* special imm3 values with range restricted to -2 <= imm3 <= 3 */
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/* needed for rac/rachi */
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#define RESTRICTED_NUM3 (0x80000)
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/* Pre-decrement is only supported for SP. */
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#define OPERAND_SP (0x100000)
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/* Post-decrement is not supported for SP. Like OPERAND_EVEN, and
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unlike OPERAND_SP, this flag doesn't prevent the instruction from
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matching, it only fails validation later on. */
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#define OPERAND_NOSP (0x200000)
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/* Structure to hold information about predefined registers. */
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struct pd_reg
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{
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char *name; /* name to recognize */
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char *pname; /* name to print for this register */
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int value;
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};
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extern const struct pd_reg d10v_predefined_registers[];
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int d10v_reg_name_cnt (void);
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/* an expressionS only has one register type, so we fake it */
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/* by setting high bits to indicate type */
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#define REGISTER_MASK 0xFF
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#endif /* D10V_H */
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