126 lines
4.1 KiB
C
126 lines
4.1 KiB
C
/* Target-dependent definitions for AMD64.
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Copyright (C) 2001, 2003, 2004, 2007, 2008, 2009, 2010, 2011
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Free Software Foundation, Inc.
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Contributed by Jiri Smid, SuSE Labs.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef AMD64_TDEP_H
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#define AMD64_TDEP_H
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struct gdbarch;
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struct frame_info;
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struct regcache;
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#include "i386-tdep.h"
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/* Register numbers of various important registers. */
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enum amd64_regnum
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{
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AMD64_RAX_REGNUM, /* %rax */
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AMD64_RBX_REGNUM, /* %rbx */
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AMD64_RCX_REGNUM, /* %rcx */
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AMD64_RDX_REGNUM, /* %rdx */
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AMD64_RSI_REGNUM, /* %rsi */
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AMD64_RDI_REGNUM, /* %rdi */
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AMD64_RBP_REGNUM, /* %rbp */
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AMD64_RSP_REGNUM, /* %rsp */
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AMD64_R8_REGNUM, /* %r8 */
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AMD64_R9_REGNUM, /* %r9 */
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AMD64_R10_REGNUM, /* %r10 */
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AMD64_R11_REGNUM, /* %r11 */
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AMD64_R12_REGNUM, /* %r12 */
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AMD64_R13_REGNUM, /* %r13 */
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AMD64_R14_REGNUM, /* %r14 */
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AMD64_R15_REGNUM, /* %r15 */
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AMD64_RIP_REGNUM, /* %rip */
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AMD64_EFLAGS_REGNUM, /* %eflags */
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AMD64_CS_REGNUM, /* %cs */
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AMD64_SS_REGNUM, /* %ss */
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AMD64_DS_REGNUM, /* %ds */
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AMD64_ES_REGNUM, /* %es */
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AMD64_FS_REGNUM, /* %fs */
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AMD64_GS_REGNUM, /* %gs */
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AMD64_ST0_REGNUM = 24, /* %st0 */
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AMD64_FCTRL_REGNUM = AMD64_ST0_REGNUM + 8,
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AMD64_FSTAT_REGNUM = AMD64_ST0_REGNUM + 9,
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AMD64_XMM0_REGNUM = 40, /* %xmm0 */
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AMD64_XMM1_REGNUM, /* %xmm1 */
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AMD64_MXCSR_REGNUM = AMD64_XMM0_REGNUM + 16,
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AMD64_YMM0H_REGNUM, /* %ymm0h */
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AMD64_YMM15H_REGNUM = AMD64_YMM0H_REGNUM + 15
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};
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/* Number of general purpose registers. */
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#define AMD64_NUM_GREGS 24
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#define AMD64_NUM_REGS (AMD64_YMM15H_REGNUM + 1)
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extern struct displaced_step_closure *amd64_displaced_step_copy_insn
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(struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to,
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struct regcache *regs);
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extern void amd64_displaced_step_fixup (struct gdbarch *gdbarch,
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struct displaced_step_closure *closure,
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CORE_ADDR from, CORE_ADDR to,
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struct regcache *regs);
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extern void amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch);
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/* Fill register REGNUM in REGCACHE with the appropriate
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floating-point or SSE register value from *FXSAVE. If REGNUM is
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-1, do this for all registers. This function masks off any of the
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reserved bits in *FXSAVE. */
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extern void amd64_supply_fxsave (struct regcache *regcache, int regnum,
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const void *fxsave);
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/* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
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extern void amd64_supply_xsave (struct regcache *regcache, int regnum,
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const void *xsave);
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/* Fill register REGNUM (if it is a floating-point or SSE register) in
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*FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
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all registers. This function doesn't touch any of the reserved
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bits in *FXSAVE. */
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extern void amd64_collect_fxsave (const struct regcache *regcache, int regnum,
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void *fxsave);
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/* Similar to amd64_collect_fxsave, but but use XSAVE extended state. */
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extern void amd64_collect_xsave (const struct regcache *regcache,
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int regnum, void *xsave, int gcore);
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void amd64_classify (struct type *type, enum amd64_reg_class class[2]);
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/* Variables exported from amd64-linux-tdep.c. */
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extern int amd64_linux_gregset_reg_offset[];
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/* Variables exported from amd64nbsd-tdep.c. */
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extern int amd64nbsd_r_reg_offset[];
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/* Variables exported from amd64obsd-tdep.c. */
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extern int amd64obsd_r_reg_offset[];
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/* Variables exported from amd64fbsd-tdep.c. */
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extern CORE_ADDR amd64fbsd_sigtramp_start_addr;
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extern CORE_ADDR amd64fbsd_sigtramp_end_addr;
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extern int amd64fbsd_sc_reg_offset[];
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#endif /* amd64-tdep.h */
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