661 lines
17 KiB
C
661 lines
17 KiB
C
/* Print i860 instructions for GDB, the GNU debugger.
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Copyright status of this module is unclear!!!
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Copyright (C) 1992 Free Software Foundation, Inc.
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SVR4 changes Contributed by Peggy Fieland (pfieland@stratus.com)
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GDB is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY. No author or distributor accepts responsibility to anyone
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for the consequences of using it or for whether it serves any
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particular purpose or works at all, unless he says so in writing.
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Refer to the GDB General Public License for full details.
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Everyone is granted permission to copy, modify and redistribute GDB,
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but only under the conditions described in the GDB General Public
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License. A copy of this license is supposed to have been given to you
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along with GDB so you can know your rights and responsibilities. It
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should be in a file named COPYING. Among other things, the copyright
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notice and this notice must be preserved on all copies.
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In other words, go ahead and share GDB, but don't try to stop
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anyone else from sharing it farther. Help stamp out software hoarding!
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*/
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#include <stdio.h>
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#include "defs.h"
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#include "tm-i860.h"
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#include "i860-opcode.h"
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/* i860 instructions are never longer than this many bytes. */
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#define MAXLEN 4
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static int fp_instr();
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static void fld_offset();
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static void gen_rrr();
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static void gen_irr();
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static void ctrl_a();
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/*
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* integer registers names
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*/
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static char *ireg[32] =
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{
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"r0", "r1", "sp", "fp", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
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"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
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};
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/*
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* Control registers of the ld.c and st.c instructions
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*/
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static char *ctlreg[32] =
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{
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"fir", "psr", "dirbase", "db", "fsr", "?", "?", "?",
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"?", "?", "?", "?", "?", "?", "?", "?",
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"?", "?", "?", "?", "?", "?", "?", "?",
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"?", "?", "?", "?", "?", "?", "?", "?"
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};
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/***********************************************************************
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* Print the i860 instruction at address MEMADDR in debugged memory,
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* on STREAM. Returns length of the instruction, in bytes, which
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* is always 4.
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*/
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int
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print_insn (memaddr, stream)
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CORE_ADDR memaddr; /* address of the instruction */
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FILE *stream; /* stream on which to write result */
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{
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union insn_fmt insn; /* the instruction we're decoding */
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long offset; /* the (decoded) offset from the instruction */
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long split_offset; /* the value of a ld/st-style split offset */
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int ai; /* autoincrement flag */
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char suffix; /* length suffix */
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adj_read_memory (memaddr, &insn, MAXLEN);
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/* These offsets used in ld, st, bte, etc. instructions and are formed by
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* combining 2 separate fields within the instruction and sign-extending
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* the result
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*/
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split_offset = (insn.gen.dest << 11) | insn.gen.offset;
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split_offset = SIGN_EXT(16, split_offset);
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switch (insn.gen.op1)
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{
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case 000:
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fprintf (stream, "ld.b %s(%s),%s", ireg[insn.gen.src1],
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ireg[insn.gen.src2], ireg[insn.gen.dest]);
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break;
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case 001:
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offset = SIGN_EXT(16, insn.geni.offset);
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fprintf (stream, "ld.b 0x%x(%s),%s", offset,
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ireg[insn.geni.src2], ireg[insn.geni.dest]);
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break;
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case 002:
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fprintf (stream, "ixfr %s,f%d", ireg[insn.gen.src1], insn.gen.dest);
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break;
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case 003:
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fprintf (stream, "st.b %s,0x%x(%s)", ireg[insn.gen.src1], split_offset,
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ireg[insn.geni.src2]);
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break;
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case 004:
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fprintf (stream, "ld.%c %s(%s),%s", (insn.gen.offset & 1) ? 'l' : 's',
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ireg[insn.gen.src1], ireg[insn.gen.src2], ireg[insn.gen.dest]);
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break;
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case 005:
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offset = SIGN_EXT(16, insn.geni.offset);
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fprintf (stream, "ld.%c 0x%x(%s),%s", (insn.geni.offset & 1) ? 'l' : 's',
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(offset & ~1), ireg[insn.geni.src2], ireg[insn.geni.dest]);
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break;
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case 007:
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fprintf (stream, "st.%c %s,0x%x(%s)", (insn.geni.offset & 1) ? 'l' : 's',
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ireg[insn.gen.src1], (split_offset & ~1), ireg[insn.geni.src2]);
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break;
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case 010:
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offset = insn.gen.offset;
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fld_offset(&offset, &suffix, &ai);
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fprintf (stream, "fld.%c %s(%s)%s,f%d", suffix,
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ireg[insn.gen.src1], ireg[insn.gen.src2], ai ? "++" : "",
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insn.gen.dest);
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break;
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case 011:
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offset = SIGN_EXT(16, insn.geni.offset);
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fld_offset(&offset, &suffix, &ai);
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fprintf (stream, "fld.%c 0x%x(%s)%s,f%d", suffix,
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offset, ireg[insn.gen.src2], ai ? "++" : "", insn.gen.dest);
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break;
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case 012:
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offset = insn.gen.offset;
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fld_offset(&offset, &suffix, &ai);
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fprintf (stream, "fst.%c f%d,%s(%s)%s", suffix,
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insn.gen.dest, ireg[insn.gen.src1], ireg[insn.gen.src2],
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ai ? "++" : "");
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break;
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case 013:
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offset = SIGN_EXT(16, insn.geni.offset);
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fld_offset(&offset, &suffix, &ai);
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fprintf (stream, "fst.%c f%d,0x%x(%s)%s", suffix,
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insn.gen.dest, offset, ireg[insn.gen.src2], ai ? "++" : "");
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break;
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case 014:
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fprintf (stream, "ld.c %s,%s", ctlreg[insn.gen.src2],
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ireg[insn.gen.dest]);
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break;
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case 015:
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offset = SIGN_EXT(16, insn.geni.offset);
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fld_offset(&offset, &suffix, &ai);
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fprintf (stream, "flush 0x%x(%s)%s", offset, ireg[insn.gen.src2],
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ai ? "++" : "");
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break;
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case 016:
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fprintf (stream, "st.c %s,%s", ireg[insn.gen.src1],
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ctlreg[insn.gen.src2]);
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break;
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case 017:
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offset = SIGN_EXT(16, insn.geni.offset);
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fld_offset(&offset, &suffix, &ai);
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fprintf (stream, "pst.d f%d,0x%x(%s)%s", insn.gen.dest,
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offset, ireg[insn.gen.src2], ai ? "++" : "");
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break;
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case 020:
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fprintf (stream, "bri %s", ireg[insn.gen.src1]);
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break;
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case 021:
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gen_rrr("trap", insn, stream);
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break;
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case 022:
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/*
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* Floating-point Opcodes
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*/
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if (!fp_instr(insn.fp, stream))
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fprintf (stream, "0x%08x (invalid instruction)", insn.int_val);
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break;
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case 023:
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/*
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* Core Escape Opcodes
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*/
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switch (insn.esc.op2)
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{
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case 1:
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fprintf (stream, "lock");
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break;
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case 2:
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fprintf (stream, "calli %s", ireg[insn.esc.src1]);
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break;
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case 4:
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fprintf (stream, "intovr");
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break;
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case 7:
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fprintf (stream, "unlock");
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break;
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default:
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fprintf (stream, "0x%08x (invalid instruction)", insn.int_val);
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break;
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}
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break;
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case 024:
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fprintf (stream, "btne %s,%s,", ireg[insn.gen.src1],
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ireg[insn.gen.src2]);
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offset = split_offset << 2;
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print_address ((CORE_ADDR) (memaddr + 4 + offset), stream);
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break;
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case 025:
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fprintf (stream, "btne 0x%x,%s,", insn.gen.src1, ireg[insn.gen.src2]);
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offset = split_offset << 2;
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print_address ((CORE_ADDR) (memaddr + 4 + offset), stream);
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break;
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case 026:
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fprintf (stream, "bte %s,%s,", ireg[insn.gen.src1],
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ireg[insn.gen.src2]);
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offset = split_offset << 2;
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print_address ((CORE_ADDR) (memaddr + 4 + offset), stream);
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break;
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case 027:
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fprintf (stream, "bte 0x%x,%s,", insn.gen.src1, ireg[insn.gen.src2]);
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offset = split_offset << 2;
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print_address ((CORE_ADDR) (memaddr + 4 + offset), stream);
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break;
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case 030:
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offset = insn.gen.offset;
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fld_offset(&offset, &suffix, &ai);
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fprintf (stream, "pfld.%c %s(%s)%s,f%d", suffix,
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ireg[insn.gen.src1], ireg[insn.gen.src2], ai ? "++" : "",
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insn.gen.dest);
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break;
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case 031:
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offset = SIGN_EXT(16, insn.geni.offset);
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fld_offset(&offset, &suffix, &ai);
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fprintf (stream, "pfld.%c 0x%x(%s)%s,f%d", suffix,
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offset, ireg[insn.gen.src2], ai ? "++" : "", insn.gen.dest);
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break;
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case 032:
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ctrl_a("br", insn, memaddr, stream);
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break;
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case 033:
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ctrl_a("call", insn, memaddr, stream);
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break;
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case 034:
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ctrl_a("bc", insn, memaddr, stream);
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break;
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case 035:
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ctrl_a("bc.t", insn, memaddr, stream);
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break;
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case 036:
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ctrl_a("bnc", insn, memaddr, stream);
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break;
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case 037:
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ctrl_a("bnc.t", insn, memaddr, stream);
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break;
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case 040:
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gen_rrr("addu", insn, stream);
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break;
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case 041:
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gen_irr("addu", insn, SIGN_EXT(16, insn.geni.offset), stream);
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break;
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case 042:
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gen_rrr("subu", insn, stream);
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break;
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case 043:
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gen_irr("subu", insn, SIGN_EXT(16, insn.geni.offset), stream);
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break;
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case 044:
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gen_rrr("adds", insn, stream);
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break;
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case 045:
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gen_irr("adds", insn, SIGN_EXT(16, insn.geni.offset), stream);
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break;
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case 046:
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gen_rrr("subs", insn, stream);
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break;
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case 047:
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gen_irr("subs", insn, SIGN_EXT(16, insn.geni.offset), stream);
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break;
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case 050:
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if (insn.gen.src1 == 0)
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{
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if (insn.gen.src2 == 0 && insn.gen.dest == 0)
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fprintf (stream, "nop");
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else
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fprintf (stream, "mov %s,%s", ireg[insn.gen.src2],
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ireg[insn.gen.dest]);
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}
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else
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gen_rrr("shl", insn, stream);
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break;
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case 051:
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gen_irr("shl", insn, insn.geni.offset, stream);
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break;
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case 052:
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gen_rrr("shr", insn, stream);
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break;
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case 053:
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gen_irr("shr", insn, insn.geni.offset, stream);
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break;
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case 054:
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if (insn.gen.src1 == 0 && insn.gen.src2 == 0 && insn.gen.dest == 0)
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{
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if ((insn.int_val & (1 << 9)) != 0)
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fprintf (stream, "d.");
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fprintf (stream, "fnop");
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}
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else
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gen_rrr("shrd", insn, stream);
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break;
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case 055:
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fprintf (stream, "bla %s,%s,", ireg[insn.gen.src1],
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ireg[insn.gen.src2]);
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offset = split_offset << 2;
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print_address ((CORE_ADDR) (memaddr + 4 + offset), stream);
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break;
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case 056:
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gen_rrr("shra", insn, stream);
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break;
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case 057:
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gen_irr("shra", insn, insn.geni.offset, stream);
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break;
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case 060:
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gen_rrr("and", insn, stream);
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break;
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case 061:
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gen_irr("and", insn, insn.geni.offset, stream);
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break;
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case 063:
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gen_irr("andh", insn, insn.geni.offset, stream);
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break;
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case 064:
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gen_rrr("andnot", insn, stream);
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break;
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case 065:
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gen_irr("andnot", insn, insn.geni.offset, stream);
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break;
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case 067:
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gen_irr("andnoth", insn, insn.geni.offset, stream);
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break;
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case 070:
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gen_rrr("or", insn, stream);
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break;
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case 071:
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gen_irr("or", insn, insn.geni.offset, stream);
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break;
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case 073:
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gen_irr("orh", insn, insn.geni.offset, stream);
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break;
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case 074:
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gen_rrr("xor", insn, stream);
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break;
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case 075:
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gen_irr("xor", insn, insn.geni.offset, stream);
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break;
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case 077:
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gen_irr("xorh", insn, insn.geni.offset, stream);
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break;
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default:
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fprintf (stream, "0x%08x (invalid instruction)", insn.int_val);
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break;
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}
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return(4);
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}
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/* A full list of floating point opcodes - if the entry is NULL, there is
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* no corresponding instruction
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*/
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static char *fp_ops[] =
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{
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"r2p1", "r2pt", "r2ap1", "r2apt",
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"i2p1", "i2pt", "i2ap1", "i2apt",
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"rat1p2", "m12apm", "ra1p2", "m12ttpa",
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"iat1p2", "m12tpm", "ia1p2", "m12tpa",
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"r2s1", "r2st", "r2as1", "r2ast",
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"i2s1", "i2st", "i2as1", "i2ast",
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"rat1s2", "m12asm", "ra1s2", "m12ttsa",
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"iat1s2", "m12tsm", "ia1s2", "m12tsa",
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"fmul", "fmlow", "frcp", "frsqr",
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"fmul3", NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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"fadd", "fsub", "fix", "famov",
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"fgt", "feq", NULL, NULL,
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NULL, NULL, "ftrunc", NULL,
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NULL, NULL, NULL, NULL,
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"fxfr", NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, "fiadd", NULL, NULL,
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NULL, "fisub", NULL, NULL,
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"faddp", "faddz", NULL, NULL,
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NULL, NULL, NULL, "fzchkl",
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NULL, NULL, "form", NULL,
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NULL, NULL, NULL, "fzchks",
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};
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/* Alternate list of floating point opcodes for PFMAM/PFMSM instructions
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*/
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static char *alt_fp_ops[] =
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{
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"mr2p1", "mr2pt", "mr2mp1", "mr2mpt",
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"mi2p1", "mi2pt", "mi2mp1", "mi2mpt",
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"mrmt1p2", "mm12mpm", "mrm1p2", "mm12ttpm",
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"mimt1p2", "mm12tpm", "mim1p2", "mm12tpm",
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"mr2s1", "mr2st", "mr2ms1", "mr2mst",
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"mi2s1", "mi2st", "mi2ms1", "mi2mst",
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"mrmt1s2", "mm12msm", "mrm1s2", "mm12ttsm",
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"mimt1s2", "mm12tsm", "mim1s2", "mm12tsm",
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};
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/* Floating point precision suffix values - indexed by s and r bits of
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* instructions.
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*/
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static char precision[2] =
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{
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's', 'd',
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};
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/***********************************************************************
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* Print floating-point instruction 'insn' on the indicated stream
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* Returns 1 if successful, 0 on failure (invalid instruction)
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*/
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static int
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fp_instr(insn, stream)
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struct fp_fmt insn; /* instruction to decode */
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FILE *stream; /* stream to print on */
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{
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char *name; /* the opcode name */
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name = fp_ops[insn.op2];
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if (name && insn.d)
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fprintf(stream, "d.");
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if (insn.op2 < 0x20)
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{
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/*
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* DPC Ops
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*/
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if (insn.p == 0) /* use PFMAM/PFMSM ops if p=0 */
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name = alt_fp_ops[insn.op2];
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fprintf (stream, "%s.%c%c f%d,f%d,f%d", name,
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precision[insn.s], precision[insn.r],
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insn.src1, insn.src2, insn.dest);
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}
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||
else
|
||
{
|
||
switch (insn.op2)
|
||
{
|
||
case 0x21: /* fmlow (no pipeline allowed) */
|
||
fprintf (stream, "%s.%c%c f%d,f%d,f%d", name,
|
||
precision[insn.s], precision[insn.r],
|
||
insn.src1, insn.src2, insn.dest);
|
||
break;
|
||
|
||
case 0x22: /* frcp */
|
||
case 0x23: /* fsqrt */
|
||
fprintf (stream, "%s.%c%c f%d,f%d", name,
|
||
precision[insn.s], precision[insn.r],
|
||
insn.src2, insn.dest);
|
||
break;
|
||
|
||
case 0x24: /* pfmul3 */
|
||
fprintf (stream, "pfmul3.dd f%d,f%d,f%d",
|
||
insn.src1, insn.src2, insn.dest);
|
||
break;
|
||
|
||
case 0x30: /* fadd */
|
||
case 0x49: /* fiadd */
|
||
if (insn.src2 == 0)
|
||
{
|
||
/*
|
||
* Really fmov
|
||
*/
|
||
fprintf (stream, "%sfmov.%c%c f%d,f%d", insn.p ? "p" : "",
|
||
precision[insn.s], precision[insn.r],
|
||
insn.src1, insn.dest);
|
||
}
|
||
else
|
||
{
|
||
fprintf (stream, "%s%s.%c%c f%d,f%d,f%d", insn.p ? "p" : "", name,
|
||
precision[insn.s], precision[insn.r],
|
||
insn.src1, insn.src2, insn.dest);
|
||
}
|
||
break;
|
||
|
||
case 0x32: /* fix */
|
||
case 0x3A: /* ftrunc */
|
||
fprintf (stream, "%s%s.%c%c f%d,f%d", insn.p ? "p" : "", name,
|
||
precision[insn.s], precision[insn.r],
|
||
insn.src1, insn.dest);
|
||
break;
|
||
|
||
case 0x34: /* pfgt/pfle */
|
||
if (insn.r)
|
||
name = "fle";
|
||
fprintf (stream, "p%s.%c%c f%d,f%d,f%d", name,
|
||
precision[insn.s], precision[insn.s],
|
||
insn.src1, insn.src2, insn.dest);
|
||
break;
|
||
|
||
case 0x35: /* pfeq */
|
||
fprintf (stream, "pfeq.%c%c f%d,f%d,f%d",
|
||
precision[insn.s], precision[insn.r],
|
||
insn.src1, insn.src2, insn.dest);
|
||
break;
|
||
|
||
case 0x40: /* fxfr */
|
||
fprintf (stream, "fxfr f%d,%s", insn.src1, ireg[insn.dest]);
|
||
break;
|
||
|
||
case 0x50: /* faddp */
|
||
case 0x51: /* faddz */
|
||
case 0x57: /* fzchkl */
|
||
case 0x5F: /* fzchks */
|
||
/*
|
||
* Graphics ops with no precision
|
||
*/
|
||
fprintf (stream, "%s%s f%d,f%d,f%d", insn.p ? "p" : "", name,
|
||
insn.src1, insn.src2, insn.dest);
|
||
break;
|
||
|
||
case 0x5A: /* form */
|
||
fprintf (stream, "%sform f%d,f%d", insn.p ? "p" : "",
|
||
insn.src1, insn.dest);
|
||
break;
|
||
|
||
default:
|
||
/*
|
||
* All the rest are uniform 3-address, optionally pipelined, etc
|
||
*/
|
||
if (name)
|
||
fprintf (stream, "%s%s.%c%c f%d,f%d,f%d", insn.p ? "p" : "", name,
|
||
precision[insn.s], precision[insn.r],
|
||
insn.src1, insn.src2, insn.dest);
|
||
else
|
||
return (0);
|
||
break;
|
||
}
|
||
}
|
||
return (1);
|
||
}
|
||
|
||
/***********************************************************************
|
||
* Decode fld/fst-style offset encodings into actual offset, precision suffix,
|
||
* and autoincrement flag
|
||
*/
|
||
|
||
static void
|
||
fld_offset(offset, suffix, autoincrement)
|
||
long *offset; /* original and returned offset */
|
||
char *suffix; /* returned suffix character */
|
||
int *autoincrement; /* autoincrement flag (1 if ai) */
|
||
{
|
||
long off = *offset; /* working copy of *offset */
|
||
|
||
*autoincrement = ((off & 1) != 0);
|
||
|
||
if (off & 2)
|
||
{
|
||
*suffix = 'l';
|
||
*offset = (off & ~3);
|
||
}
|
||
else if (off & 4)
|
||
{
|
||
*suffix = 'q';
|
||
*offset = (off & ~7);
|
||
}
|
||
else
|
||
{
|
||
*suffix = 'd';
|
||
*offset = (off & ~7);
|
||
}
|
||
}
|
||
|
||
/***********************************************************************
|
||
* Print a general format instruction of the three register form:
|
||
* op rx,ry,rz
|
||
*/
|
||
|
||
static void
|
||
gen_rrr(name, insn, stream)
|
||
char *name;
|
||
union insn_fmt insn;
|
||
FILE *stream;
|
||
{
|
||
fprintf (stream, "%s %s,%s,%s", name, ireg[insn.gen.src1],
|
||
ireg[insn.gen.src2], ireg[insn.gen.dest]);
|
||
}
|
||
|
||
/***********************************************************************
|
||
* Print a general format instruction of the immed + two register form:
|
||
* op i,ry,rz
|
||
*/
|
||
|
||
static void
|
||
gen_irr(name, insn, immed, stream)
|
||
char *name;
|
||
union insn_fmt insn;
|
||
long immed;
|
||
FILE *stream;
|
||
{
|
||
fprintf (stream, "%s 0x%x,%s,%s", name, immed,
|
||
ireg[insn.gen.src2], ireg[insn.gen.dest]);
|
||
}
|
||
|
||
/***********************************************************************
|
||
* Print a ctrl format instruction with a 26-bit displacement:
|
||
* op addr
|
||
*/
|
||
|
||
static void
|
||
ctrl_a(name, insn, memaddr, stream)
|
||
char *name;
|
||
union insn_fmt insn;
|
||
CORE_ADDR memaddr;
|
||
FILE *stream;
|
||
{
|
||
long offset;
|
||
|
||
fprintf (stream, "%s ", name);
|
||
offset = SIGN_EXT(28, insn.ctrl.offset << 2);
|
||
|
||
print_address ((CORE_ADDR) (memaddr + 4 + offset), stream);
|
||
}
|
||
|
||
|