345d88d96e
Written by matthew green <mrg@redhat.com>, with fixes from Aldy Hernandez <aldyh@redhat.com>, Jim Wilson <wilson@redhat.com>, and Nick Clifton <nickc@redhat.com>. * ppc-instructions: Include altivec.igen and e500.igen. (model_busy, model_data): Add vr_busy and vscr_busy. (model_trace_release): Trace vr_busy and vscr_busy. (model_new_cycle): Update vr_busy and vscr_busy. (model_make_busy): Update vr_busy and vscr_busy. * registers.c (register_description): Add Altivec and e500 registers. * psim.c (psim_read_register, psim_read_register): Handle Altivec and e500 registers. * ppc-spr-table (SPEFSCR): Add VRSAVE and SPEFSCR registers. * configure.in (sim_filter): When *altivec* add "av". When *spe* or *simd* add e500. (sim_float): When *altivec* define WITH_ALTIVEC. When *spe* add WITH_E500. * configure: Re-generate. * e500.igen, altivec.igen: New files. * e500_expression.h, altivec_expression.h: New files. * idecode_expression.h: Update copyright. Include "e500_expression.h" and "altivec_expression.h". * e500_registers.h, altivec_registers.h: New files. * registers.h: Update copyright. Include "e500_registers.h" and "altivec_registers.h". (registers): Add Altivec and e500 specific registers. * Makefile.in (IDECODE_H): Add "idecode_e500.h" and "idecode_altivec.h". (REGISTERS_H): Add "e500_registers.h" and "altivec_registers.h". (tmp-igen): Add dependencies on altivec.igen and e500.igen .
63 lines
2.1 KiB
C
63 lines
2.1 KiB
C
/* Altivec registers, for PSIM, the PowerPC simulator.
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Copyright 2003 Free Software Foundation, Inc.
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Contributed by Red Hat Inc; developed under contract from Motorola.
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Written by matthew green <mrg@redhat.com>.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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/* Manage this as 4 32-bit entities, 8 16-bit entities or 16 8-bit
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entities. */
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typedef union
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{
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unsigned8 b[16];
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unsigned16 h[8];
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unsigned32 w[4];
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} vreg;
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typedef unsigned32 vscreg;
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struct altivec_regs {
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/* AltiVec Registers */
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vreg vr[32];
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vscreg vscr;
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};
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/* AltiVec registers */
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#define VR(N) cpu_registers(processor)->altivec.vr[N]
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/* AltiVec vector status and control register */
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#define VSCR cpu_registers(processor)->altivec.vscr
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/* AltiVec endian helpers, wrong endian hosts vs targets need to be
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sure to get the right bytes/halfs/words when the order matters.
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Note that many AltiVec instructions do not depend on byte order and
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work on N independant bits of data. This is only for the
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instructions that actually move data around. */
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#if (WITH_HOST_BYTE_ORDER == BIG_ENDIAN)
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#define AV_BINDEX(x) ((x) & 15)
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#define AV_HINDEX(x) ((x) & 7)
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#else
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static char endian_b2l_bindex[16] = { 3, 2, 1, 0, 7, 6, 5, 4,
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11, 10, 9, 8, 15, 14, 13, 12 };
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static char endian_b2l_hindex[16] = { 1, 0, 3, 2, 5, 4, 7, 6 };
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#define AV_BINDEX(x) endian_b2l_bindex[(x) & 15]
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#define AV_HINDEX(x) endian_b2l_hindex[(x) & 7]
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#endif
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