517 lines
15 KiB
C
517 lines
15 KiB
C
/* Disassembler interface for targets using CGEN. -*- C -*-
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CGEN: Cpu tools GENerator
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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- the resultant file is machine generated, cgen-dis.in isn't
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Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
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This file is part of the GNU Binutils and GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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/* ??? Eventually more and more of this stuff can go to cpu-independent files.
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Keep that in mind. */
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#include "sysdep.h"
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#include <stdio.h>
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#include "ansidecl.h"
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#include "dis-asm.h"
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#include "bfd.h"
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#include "symcat.h"
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#include "openrisc-desc.h"
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#include "openrisc-opc.h"
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#include "opintl.h"
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/* Default text to print if an instruction isn't recognized. */
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#define UNKNOWN_INSN_MSG _("*unknown*")
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static void print_normal
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PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
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static void print_address
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PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
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static void print_keyword
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PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
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static void print_insn_normal
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PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
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bfd_vma, int));
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static int print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma,
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disassemble_info *, char *, int));
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static int default_print_insn
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PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
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/* -- disassembler routines inserted here */
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/* Main entry point for printing operands.
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XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
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of dis-asm.h on cgen.h.
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This function is basically just a big switch statement. Earlier versions
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used tables to look up the function to use, but
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- if the table contains both assembler and disassembler functions then
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the disassembler contains much of the assembler and vice-versa,
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- there's a lot of inlining possibilities as things grow,
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- using a switch statement avoids the function call overhead.
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This function could be moved into `print_insn_normal', but keeping it
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separate makes clear the interface between `print_insn_normal' and each of
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the handlers.
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*/
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void
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openrisc_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
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CGEN_CPU_DESC cd;
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int opindex;
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PTR xinfo;
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CGEN_FIELDS *fields;
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void const *attrs;
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bfd_vma pc;
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int length;
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{
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disassemble_info *info = (disassemble_info *) xinfo;
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switch (opindex)
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{
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case OPENRISC_OPERAND_ABS_26 :
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print_address (cd, info, fields->f_abs26, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
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break;
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case OPENRISC_OPERAND_DISP_26 :
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print_address (cd, info, fields->f_disp26, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
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break;
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case OPENRISC_OPERAND_HI16 :
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print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
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break;
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case OPENRISC_OPERAND_LO16 :
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print_normal (cd, info, fields->f_lo16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
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break;
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case OPENRISC_OPERAND_OP_F_23 :
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print_normal (cd, info, fields->f_op4, 0, pc, length);
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break;
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case OPENRISC_OPERAND_OP_F_3 :
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print_normal (cd, info, fields->f_op5, 0, pc, length);
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break;
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case OPENRISC_OPERAND_RA :
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print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r2, 0);
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break;
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case OPENRISC_OPERAND_RB :
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print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r3, 0);
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break;
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case OPENRISC_OPERAND_RD :
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print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r1, 0);
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break;
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case OPENRISC_OPERAND_SIMM_16 :
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print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
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break;
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case OPENRISC_OPERAND_UI16NC :
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print_normal (cd, info, fields->f_i16nc, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
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break;
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case OPENRISC_OPERAND_UIMM_16 :
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print_normal (cd, info, fields->f_uimm16, 0, pc, length);
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break;
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case OPENRISC_OPERAND_UIMM_5 :
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print_normal (cd, info, fields->f_uimm5, 0, pc, length);
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break;
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default :
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/* xgettext:c-format */
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fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
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opindex);
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abort ();
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}
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}
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cgen_print_fn * const openrisc_cgen_print_handlers[] =
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{
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print_insn_normal,
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};
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void
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openrisc_cgen_init_dis (cd)
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CGEN_CPU_DESC cd;
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{
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openrisc_cgen_init_opcode_table (cd);
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openrisc_cgen_init_ibld_table (cd);
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cd->print_handlers = & openrisc_cgen_print_handlers[0];
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cd->print_operand = openrisc_cgen_print_operand;
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}
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/* Default print handler. */
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static void
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print_normal (cd, dis_info, value, attrs, pc, length)
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#ifdef CGEN_PRINT_NORMAL
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CGEN_CPU_DESC cd;
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#else
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CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
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#endif
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PTR dis_info;
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long value;
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unsigned int attrs;
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#ifdef CGEN_PRINT_NORMAL
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bfd_vma pc;
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int length;
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#else
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bfd_vma pc ATTRIBUTE_UNUSED;
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int length ATTRIBUTE_UNUSED;
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#endif
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{
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disassemble_info *info = (disassemble_info *) dis_info;
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#ifdef CGEN_PRINT_NORMAL
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CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
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#endif
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/* Print the operand as directed by the attributes. */
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if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
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; /* nothing to do */
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else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
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(*info->fprintf_func) (info->stream, "%ld", value);
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else
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(*info->fprintf_func) (info->stream, "0x%lx", value);
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}
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/* Default address handler. */
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static void
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print_address (cd, dis_info, value, attrs, pc, length)
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#ifdef CGEN_PRINT_NORMAL
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CGEN_CPU_DESC cd;
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#else
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CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
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#endif
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PTR dis_info;
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bfd_vma value;
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unsigned int attrs;
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#ifdef CGEN_PRINT_NORMAL
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bfd_vma pc;
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int length;
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#else
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bfd_vma pc ATTRIBUTE_UNUSED;
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int length ATTRIBUTE_UNUSED;
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#endif
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{
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disassemble_info *info = (disassemble_info *) dis_info;
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#ifdef CGEN_PRINT_ADDRESS
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CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
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#endif
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/* Print the operand as directed by the attributes. */
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if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
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; /* nothing to do */
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else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
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(*info->print_address_func) (value, info);
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else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
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(*info->print_address_func) (value, info);
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else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
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(*info->fprintf_func) (info->stream, "%ld", (long) value);
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else
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(*info->fprintf_func) (info->stream, "0x%lx", (long) value);
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}
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/* Keyword print handler. */
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static void
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print_keyword (cd, dis_info, keyword_table, value, attrs)
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CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
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PTR dis_info;
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CGEN_KEYWORD *keyword_table;
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long value;
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unsigned int attrs ATTRIBUTE_UNUSED;
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{
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disassemble_info *info = (disassemble_info *) dis_info;
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const CGEN_KEYWORD_ENTRY *ke;
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ke = cgen_keyword_lookup_value (keyword_table, value);
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if (ke != NULL)
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(*info->fprintf_func) (info->stream, "%s", ke->name);
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else
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(*info->fprintf_func) (info->stream, "???");
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}
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/* Default insn printer.
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DIS_INFO is defined as `PTR' so the disassembler needn't know anything
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about disassemble_info. */
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static void
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print_insn_normal (cd, dis_info, insn, fields, pc, length)
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CGEN_CPU_DESC cd;
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PTR dis_info;
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const CGEN_INSN *insn;
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CGEN_FIELDS *fields;
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bfd_vma pc;
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int length;
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{
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const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
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disassemble_info *info = (disassemble_info *) dis_info;
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const CGEN_SYNTAX_CHAR_TYPE *syn;
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CGEN_INIT_PRINT (cd);
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for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
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{
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if (CGEN_SYNTAX_MNEMONIC_P (*syn))
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{
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(*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
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continue;
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}
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if (CGEN_SYNTAX_CHAR_P (*syn))
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{
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(*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
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continue;
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}
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/* We have an operand. */
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openrisc_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
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fields, CGEN_INSN_ATTRS (insn), pc, length);
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}
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}
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/* Subroutine of print_insn. Reads an insn into the given buffers and updates
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the extract info.
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Returns 0 if all is well, non-zero otherwise. */
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static int
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read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
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CGEN_CPU_DESC cd;
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bfd_vma pc;
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disassemble_info *info;
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char *buf;
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int buflen;
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CGEN_EXTRACT_INFO *ex_info;
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unsigned long *insn_value;
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{
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int status = (*info->read_memory_func) (pc, buf, buflen, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, pc, info);
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return -1;
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}
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ex_info->dis_info = info;
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ex_info->valid = (1 << buflen) - 1;
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ex_info->insn_bytes = buf;
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*insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
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return 0;
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}
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/* Utility to print an insn.
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BUF is the base part of the insn, target byte order, BUFLEN bytes long.
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The result is the size of the insn in bytes or zero for an unknown insn
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or -1 if an error occurs fetching data (memory_error_func will have
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been called). */
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static int
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print_insn (cd, pc, info, buf, buflen)
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CGEN_CPU_DESC cd;
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bfd_vma pc;
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disassemble_info *info;
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char *buf;
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int buflen;
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{
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unsigned long insn_value;
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const CGEN_INSN_LIST *insn_list;
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CGEN_EXTRACT_INFO ex_info;
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int rc = read_insn (cd, pc, info, buf, buflen, & ex_info, & insn_value);
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if (rc != 0)
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return rc;
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/* The instructions are stored in hash lists.
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Pick the first one and keep trying until we find the right one. */
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insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
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while (insn_list != NULL)
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{
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const CGEN_INSN *insn = insn_list->insn;
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CGEN_FIELDS fields;
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int length;
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#ifdef CGEN_VALIDATE_INSN_SUPPORTED
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/* not needed as insn shouldn't be in hash lists if not supported */
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/* Supported by this cpu? */
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if (! openrisc_cgen_insn_supported (cd, insn))
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{
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insn_list = CGEN_DIS_NEXT_INSN (insn_list);
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continue;
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}
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#endif
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/* Basic bit mask must be correct. */
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/* ??? May wish to allow target to defer this check until the extract
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handler. */
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if ((insn_value & CGEN_INSN_BASE_MASK (insn))
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== CGEN_INSN_BASE_VALUE (insn))
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{
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/* Printing is handled in two passes. The first pass parses the
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machine insn and extracts the fields. The second pass prints
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them. */
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/* Make sure the entire insn is loaded into insn_value, if it
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can fit. */
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if (CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize &&
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(CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
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{
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unsigned long full_insn_value;
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int rc = read_insn (cd, pc, info, buf,
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CGEN_INSN_BITSIZE (insn) / 8,
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& ex_info, & full_insn_value);
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if (rc != 0)
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return rc;
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length = CGEN_EXTRACT_FN (cd, insn)
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(cd, insn, &ex_info, full_insn_value, &fields, pc);
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}
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else
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length = CGEN_EXTRACT_FN (cd, insn)
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(cd, insn, &ex_info, insn_value, &fields, pc);
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/* length < 0 -> error */
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if (length < 0)
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return length;
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if (length > 0)
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{
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CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
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/* length is in bits, result is in bytes */
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return length / 8;
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}
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}
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insn_list = CGEN_DIS_NEXT_INSN (insn_list);
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}
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return 0;
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}
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/* Default value for CGEN_PRINT_INSN.
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The result is the size of the insn in bytes or zero for an unknown insn
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or -1 if an error occured fetching bytes. */
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#ifndef CGEN_PRINT_INSN
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#define CGEN_PRINT_INSN default_print_insn
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#endif
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static int
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default_print_insn (cd, pc, info)
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CGEN_CPU_DESC cd;
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bfd_vma pc;
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disassemble_info *info;
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{
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char buf[CGEN_MAX_INSN_SIZE];
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int status;
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/* Read the base part of the insn. */
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status = (*info->read_memory_func) (pc, buf, cd->base_insn_bitsize / 8, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, pc, info);
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return -1;
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}
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return print_insn (cd, pc, info, buf, cd->base_insn_bitsize / 8);
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}
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/* Main entry point.
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Print one instruction from PC on INFO->STREAM.
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Return the size of the instruction (in bytes). */
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int
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print_insn_openrisc (pc, info)
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bfd_vma pc;
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disassemble_info *info;
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{
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static CGEN_CPU_DESC cd = 0;
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static int prev_isa;
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static int prev_mach;
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static int prev_endian;
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int length;
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int isa,mach;
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int endian = (info->endian == BFD_ENDIAN_BIG
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? CGEN_ENDIAN_BIG
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: CGEN_ENDIAN_LITTLE);
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enum bfd_architecture arch;
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/* ??? gdb will set mach but leave the architecture as "unknown" */
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#ifndef CGEN_BFD_ARCH
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#define CGEN_BFD_ARCH bfd_arch_openrisc
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#endif
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arch = info->arch;
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if (arch == bfd_arch_unknown)
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arch = CGEN_BFD_ARCH;
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/* There's no standard way to compute the machine or isa number
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so we leave it to the target. */
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#ifdef CGEN_COMPUTE_MACH
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mach = CGEN_COMPUTE_MACH (info);
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#else
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mach = info->mach;
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#endif
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#ifdef CGEN_COMPUTE_ISA
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isa = CGEN_COMPUTE_ISA (info);
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#else
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isa = 0;
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#endif
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/* If we've switched cpu's, close the current table and open a new one. */
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if (cd
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&& (isa != prev_isa
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|| mach != prev_mach
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|| endian != prev_endian))
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{
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openrisc_cgen_cpu_close (cd);
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cd = 0;
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}
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/* If we haven't initialized yet, initialize the opcode table. */
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if (! cd)
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{
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const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
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const char *mach_name;
|
||
|
||
if (!arch_type)
|
||
abort ();
|
||
mach_name = arch_type->printable_name;
|
||
|
||
prev_isa = isa;
|
||
prev_mach = mach;
|
||
prev_endian = endian;
|
||
cd = openrisc_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
|
||
CGEN_CPU_OPEN_BFDMACH, mach_name,
|
||
CGEN_CPU_OPEN_ENDIAN, prev_endian,
|
||
CGEN_CPU_OPEN_END);
|
||
if (!cd)
|
||
abort ();
|
||
openrisc_cgen_init_dis (cd);
|
||
}
|
||
|
||
/* We try to have as much common code as possible.
|
||
But at this point some targets need to take over. */
|
||
/* ??? Some targets may need a hook elsewhere. Try to avoid this,
|
||
but if not possible try to move this hook elsewhere rather than
|
||
have two hooks. */
|
||
length = CGEN_PRINT_INSN (cd, pc, info);
|
||
if (length > 0)
|
||
return length;
|
||
if (length < 0)
|
||
return -1;
|
||
|
||
(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
|
||
return cd->default_insn_bitsize / 8;
|
||
}
|