c8a1f2548b
* elf32-ppc.c (ppc_elf_relax_section): Work with a partial link. * bout.c (b_out_bfd_relax_section): Reject relocatable links. * elf32-m10300.c (mn10300_elf_relax_section): Likewise. * elf32-avr.c (elf32_avr_relax_section): Likewise. * elf32-frv.c (elf32_avr_relax_section): Likewise. * elf32-xtensa.c (elf_xtensa_relax_section): Likewise. * elf64-mmix.c (mmix_elf_relax_section): Likewise. * elfxx-ia64.c (elfNN_ia64_relax_section): Likewise. * elfxx-sparc.c (_bfd_sparc_elf_relax_section): Likewise. * reloc.c (bfd_generic_relax_section): Likewise. * reloc16.c (bfd_coff_reloc16_relax_section): Likewise. * vms.c (vms_bfd_relax_section): Likewise. ld/ * ldmain.c (main): Don't reject --relax -r. * ld.texinfo (PowerPC ELF32): Document behaviour of relaxing partial links. ld/testsuite/ * ld-powerpc/vxworks-relax-2.s: New. * ld-powerpc/vxworks-relax-2.rd: New. * ld-powerpc/powerpc.exp: Add it.
11 lines
648 B
R
11 lines
648 B
R
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Relocation section '.rela.text' at offset 0x[0-9a-f]+ contains 8 entries:
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Offset Info Type Sym.Value Sym. Name \+ Addend
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00000016 00000106 R_PPC_ADDR16_HA 00000000 .text \+ 4000034
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0000001a 00000104 R_PPC_ADDR16_LO 00000000 .text \+ 4000034
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00000006 00000106 R_PPC_ADDR16_HA 00000000 .text \+ 4000034
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0000000a 00000104 R_PPC_ADDR16_LO 00000000 .text \+ 4000034
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00000026 00000506 R_PPC_ADDR16_HA 00000000 undefined \+ 0
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0000002a 00000504 R_PPC_ADDR16_LO 00000000 undefined \+ 0
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0400003e 00000606 R_PPC_ADDR16_HA 00000000 _start \+ 0
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04000042 00000604 R_PPC_ADDR16_LO 00000000 _start \+ 0
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