712 lines
26 KiB
C
712 lines
26 KiB
C
/* armsupp.c -- ARMulator support code: ARM6 Instruction Emulator.
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Copyright (C) 1994 Advanced RISC Machines Ltd.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "armdefs.h"
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#include "armemu.h"
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/***************************************************************************\
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* Definitions for the support routines *
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\***************************************************************************/
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ARMword ARMul_GetReg(ARMul_State *state, unsigned mode, unsigned reg) ;
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void ARMul_SetReg(ARMul_State *state, unsigned mode, unsigned reg, ARMword value) ;
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ARMword ARMul_GetPC(ARMul_State *state) ;
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ARMword ARMul_GetNextPC(ARMul_State *state) ;
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void ARMul_SetPC(ARMul_State *state, ARMword value) ;
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ARMword ARMul_GetR15(ARMul_State *state) ;
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void ARMul_SetR15(ARMul_State *state, ARMword value) ;
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ARMword ARMul_GetCPSR(ARMul_State *state) ;
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void ARMul_SetCPSR(ARMul_State *state, ARMword value) ;
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void ARMul_FixCPSR(ARMul_State *state, ARMword instr, ARMword rhs) ;
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ARMword ARMul_GetSPSR(ARMul_State *state, ARMword mode) ;
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void ARMul_SetSPSR(ARMul_State *state, ARMword mode, ARMword value) ;
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void ARMul_FixSPSR(ARMul_State *state, ARMword instr, ARMword rhs) ;
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void ARMul_CPSRAltered(ARMul_State *state) ;
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void ARMul_R15Altered(ARMul_State *state) ;
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ARMword ARMul_SwitchMode(ARMul_State *state,ARMword oldmode, ARMword newmode) ;
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static ARMword ModeToBank(ARMul_State *state,ARMword mode) ;
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unsigned ARMul_NthReg(ARMword instr, unsigned number) ;
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void ARMul_NegZero(ARMul_State *state, ARMword result) ;
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void ARMul_AddCarry(ARMul_State *state, ARMword a, ARMword b, ARMword result) ;
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void ARMul_AddOverflow(ARMul_State *state, ARMword a, ARMword b, ARMword result) ;
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void ARMul_SubCarry(ARMul_State *state, ARMword a, ARMword b, ARMword result) ;
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void ARMul_SubOverflow(ARMul_State *state, ARMword a, ARMword b, ARMword result) ;
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void ARMul_LDC(ARMul_State *state,ARMword instr,ARMword address) ;
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void ARMul_STC(ARMul_State *state,ARMword instr,ARMword address) ;
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void ARMul_MCR(ARMul_State *state,ARMword instr, ARMword source) ;
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ARMword ARMul_MRC(ARMul_State *state,ARMword instr) ;
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void ARMul_CDP(ARMul_State *state,ARMword instr) ;
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void ARMul_UndefInstr(ARMul_State *state,ARMword instr) ;
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unsigned IntPending(ARMul_State *state) ;
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ARMword ARMul_Align(ARMul_State *state, ARMword address, ARMword data) ;
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void ARMul_ScheduleEvent(ARMul_State *state, unsigned long delay,
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unsigned (*what)()) ;
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void ARMul_EnvokeEvent(ARMul_State *state) ;
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unsigned long ARMul_Time(ARMul_State *state) ;
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static void EnvokeList(ARMul_State *state, unsigned long from, unsigned long to) ;
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struct EventNode { /* An event list node */
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unsigned (*func)() ; /* The function to call */
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struct EventNode *next ;
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} ;
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/***************************************************************************\
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* This routine returns the value of a register from a mode. *
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\***************************************************************************/
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ARMword ARMul_GetReg(ARMul_State *state, unsigned mode, unsigned reg)
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{mode &= MODEBITS ;
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if (mode != state->Mode)
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return(state->RegBank[ModeToBank(state,(ARMword)mode)][reg]) ;
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else
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return(state->Reg[reg]) ;
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}
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/***************************************************************************\
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* This routine sets the value of a register for a mode. *
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\***************************************************************************/
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void ARMul_SetReg(ARMul_State *state, unsigned mode, unsigned reg, ARMword value)
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{mode &= MODEBITS ;
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if (mode != state->Mode)
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state->RegBank[ModeToBank(state,(ARMword)mode)][reg] = value ;
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else
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state->Reg[reg] = value ;
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}
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/***************************************************************************\
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* This routine returns the value of the PC, mode independently. *
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\***************************************************************************/
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ARMword ARMul_GetPC(ARMul_State *state)
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{if (state->Mode > SVC26MODE)
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return(state->Reg[15]) ;
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else
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return(R15PC) ;
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}
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/***************************************************************************\
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* This routine returns the value of the PC, mode independently. *
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\***************************************************************************/
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ARMword ARMul_GetNextPC(ARMul_State *state)
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{if (state->Mode > SVC26MODE)
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return(state->Reg[15] + isize) ;
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else
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return((state->Reg[15] + isize) & R15PCBITS) ;
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}
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/***************************************************************************\
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* This routine sets the value of the PC. *
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\***************************************************************************/
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void ARMul_SetPC(ARMul_State *state, ARMword value)
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{if (ARMul_MODE32BIT)
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state->Reg[15] = value & PCBITS ;
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else
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state->Reg[15] = R15CCINTMODE | (value & R15PCBITS) ;
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FLUSHPIPE ;
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}
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/***************************************************************************\
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* This routine returns the value of register 15, mode independently. *
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\***************************************************************************/
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ARMword ARMul_GetR15(ARMul_State *state)
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{if (state->Mode > SVC26MODE)
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return(state->Reg[15]) ;
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else
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return(R15PC | ECC | ER15INT | EMODE) ;
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}
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/***************************************************************************\
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* This routine sets the value of Register 15. *
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\***************************************************************************/
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void ARMul_SetR15(ARMul_State *state, ARMword value)
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{
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if (ARMul_MODE32BIT)
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state->Reg[15] = value & PCBITS ;
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else {
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state->Reg[15] = value ;
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ARMul_R15Altered(state) ;
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}
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FLUSHPIPE ;
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}
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/***************************************************************************\
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* This routine returns the value of the CPSR *
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\***************************************************************************/
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ARMword ARMul_GetCPSR(ARMul_State *state)
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{
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return(CPSR) ;
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}
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/***************************************************************************\
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* This routine sets the value of the CPSR *
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\***************************************************************************/
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void ARMul_SetCPSR(ARMul_State *state, ARMword value)
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{state->Cpsr = CPSR ;
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SETPSR(state->Cpsr,value) ;
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ARMul_CPSRAltered(state) ;
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}
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/***************************************************************************\
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* This routine does all the nasty bits involved in a write to the CPSR, *
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* including updating the register bank, given a MSR instruction. *
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\***************************************************************************/
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void ARMul_FixCPSR(ARMul_State *state, ARMword instr, ARMword rhs)
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{state->Cpsr = CPSR ;
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if (state->Bank==USERBANK) { /* Only write flags in user mode */
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if (BIT(19)) {
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SETCC(state->Cpsr,rhs) ;
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}
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}
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else { /* Not a user mode */
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if (BITS(16,19)==9) SETPSR(state->Cpsr,rhs) ;
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else if (BIT(16)) SETINTMODE(state->Cpsr,rhs) ;
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else if (BIT(19)) SETCC(state->Cpsr,rhs) ;
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}
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ARMul_CPSRAltered(state) ;
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}
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/***************************************************************************\
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* Get an SPSR from the specified mode *
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\***************************************************************************/
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ARMword ARMul_GetSPSR(ARMul_State *state, ARMword mode)
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{ARMword bank = ModeToBank(state,mode & MODEBITS) ;
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if (bank == USERBANK || bank == DUMMYBANK)
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return(CPSR) ;
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else
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return(state->Spsr[bank]) ;
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}
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/***************************************************************************\
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* This routine does a write to an SPSR *
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\***************************************************************************/
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void ARMul_SetSPSR(ARMul_State *state, ARMword mode, ARMword value)
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{ARMword bank = ModeToBank(state,mode & MODEBITS) ;
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if (bank != USERBANK && bank !=DUMMYBANK)
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state->Spsr[bank] = value ;
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}
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/***************************************************************************\
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* This routine does a write to the current SPSR, given an MSR instruction *
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\***************************************************************************/
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void ARMul_FixSPSR(ARMul_State *state, ARMword instr, ARMword rhs)
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{if (state->Bank != USERBANK && state->Bank !=DUMMYBANK) {
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if (BITS(16,19)==9) SETPSR(state->Spsr[state->Bank],rhs) ;
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else if (BIT(16)) SETINTMODE(state->Spsr[state->Bank],rhs) ;
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else if (BIT(19)) SETCC(state->Spsr[state->Bank],rhs) ;
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}
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}
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/***************************************************************************\
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* This routine updates the state of the emulator after the Cpsr has been *
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* changed. Both the processor flags and register bank are updated. *
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\***************************************************************************/
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void ARMul_CPSRAltered(ARMul_State *state)
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{ARMword oldmode ;
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if (state->prog32Sig == LOW)
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state->Cpsr &= (CCBITS | INTBITS | R15MODEBITS) ;
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oldmode = state->Mode ;
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if (state->Mode != (state->Cpsr & MODEBITS)) {
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state->Mode = ARMul_SwitchMode(state,state->Mode,state->Cpsr & MODEBITS) ;
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state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
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}
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ASSIGNINT(state->Cpsr & INTBITS) ;
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ASSIGNN((state->Cpsr & NBIT) != 0) ;
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ASSIGNZ((state->Cpsr & ZBIT) != 0) ;
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ASSIGNC((state->Cpsr & CBIT) != 0) ;
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ASSIGNV((state->Cpsr & VBIT) != 0) ;
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#ifdef MODET
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ASSIGNT((state->Cpsr & TBIT) != 0);
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#endif
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if (oldmode > SVC26MODE) {
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if (state->Mode <= SVC26MODE) {
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state->Emulate = CHANGEMODE ;
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state->Reg[15] = ECC | ER15INT | EMODE | R15PC ;
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}
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}
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else {
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if (state->Mode > SVC26MODE) {
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state->Emulate = CHANGEMODE ;
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state->Reg[15] = R15PC ;
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}
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else
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state->Reg[15] = ECC | ER15INT | EMODE | R15PC ;
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}
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}
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/***************************************************************************\
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* This routine updates the state of the emulator after register 15 has *
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* been changed. Both the processor flags and register bank are updated. *
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* This routine should only be called from a 26 bit mode. *
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\***************************************************************************/
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void ARMul_R15Altered(ARMul_State *state)
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{
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if (state->Mode != R15MODE) {
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state->Mode = ARMul_SwitchMode(state,state->Mode,R15MODE) ;
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state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
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}
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if (state->Mode > SVC26MODE)
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state->Emulate = CHANGEMODE ;
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ASSIGNR15INT(R15INT) ;
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ASSIGNN((state->Reg[15] & NBIT) != 0) ;
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ASSIGNZ((state->Reg[15] & ZBIT) != 0) ;
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ASSIGNC((state->Reg[15] & CBIT) != 0) ;
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ASSIGNV((state->Reg[15] & VBIT) != 0) ;
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}
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/***************************************************************************\
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* This routine controls the saving and restoring of registers across mode *
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* changes. The regbank matrix is largely unused, only rows 13 and 14 are *
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* used across all modes, 8 to 14 are used for FIQ, all others use the USER *
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* column. It's easier this way. old and new parameter are modes numbers. *
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* Notice the side effect of changing the Bank variable. *
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\***************************************************************************/
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ARMword ARMul_SwitchMode(ARMul_State *state,ARMword oldmode, ARMword newmode)
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{unsigned i ;
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oldmode = ModeToBank(state,oldmode) ;
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state->Bank = ModeToBank(state,newmode) ;
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if (oldmode != state->Bank) { /* really need to do it */
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switch (oldmode) { /* save away the old registers */
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case USERBANK :
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case IRQBANK :
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case SVCBANK :
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case ABORTBANK :
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case UNDEFBANK : if (state->Bank == FIQBANK)
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for (i = 8 ; i < 13 ; i++)
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state->RegBank[USERBANK][i] = state->Reg[i] ;
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state->RegBank[oldmode][13] = state->Reg[13] ;
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state->RegBank[oldmode][14] = state->Reg[14] ;
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break ;
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case FIQBANK : for (i = 8 ; i < 15 ; i++)
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state->RegBank[FIQBANK][i] = state->Reg[i] ;
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break ;
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case DUMMYBANK : for (i = 8 ; i < 15 ; i++)
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state->RegBank[DUMMYBANK][i] = 0 ;
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break ;
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}
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switch (state->Bank) { /* restore the new registers */
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case USERBANK :
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case IRQBANK :
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case SVCBANK :
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case ABORTBANK :
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case UNDEFBANK : if (oldmode == FIQBANK)
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for (i = 8 ; i < 13 ; i++)
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state->Reg[i] = state->RegBank[USERBANK][i] ;
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state->Reg[13] = state->RegBank[state->Bank][13] ;
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state->Reg[14] = state->RegBank[state->Bank][14] ;
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break ;
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case FIQBANK : for (i = 8 ; i < 15 ; i++)
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state->Reg[i] = state->RegBank[FIQBANK][i] ;
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break ;
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case DUMMYBANK : for (i = 8 ; i < 15 ; i++)
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state->Reg[i] = 0 ;
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break ;
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} /* switch */
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} /* if */
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return(newmode) ;
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}
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/***************************************************************************\
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* Given a processor mode, this routine returns the register bank that *
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* will be accessed in that mode. *
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\***************************************************************************/
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static ARMword ModeToBank(ARMul_State *state, ARMword mode)
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{static ARMword bankofmode[] = {USERBANK, FIQBANK, IRQBANK, SVCBANK,
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DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
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DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
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DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
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USERBANK, FIQBANK, IRQBANK, SVCBANK,
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DUMMYBANK, DUMMYBANK, DUMMYBANK, ABORTBANK,
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DUMMYBANK, DUMMYBANK, DUMMYBANK, UNDEFBANK
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} ;
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if (mode > UNDEF32MODE)
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return(DUMMYBANK) ;
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else
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return(bankofmode[mode]) ;
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}
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/***************************************************************************\
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* Returns the register number of the nth register in a reg list. *
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\***************************************************************************/
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unsigned ARMul_NthReg(ARMword instr, unsigned number)
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{unsigned bit, upto ;
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for (bit = 0, upto = 0 ; upto <= number ; bit++)
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if (BIT(bit)) upto++ ;
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return(bit - 1) ;
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}
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/***************************************************************************\
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* Assigns the N and Z flags depending on the value of result *
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\***************************************************************************/
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void ARMul_NegZero(ARMul_State *state, ARMword result)
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{
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if (NEG(result)) { SETN ; CLEARZ ; }
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else if (result == 0) { CLEARN ; SETZ ; }
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else { CLEARN ; CLEARZ ; } ;
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}
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/***************************************************************************\
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* Assigns the C flag after an addition of a and b to give result *
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\***************************************************************************/
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void ARMul_AddCarry(ARMul_State *state, ARMword a,ARMword b,ARMword result)
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{
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ASSIGNC( (NEG(a) && NEG(b)) ||
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(NEG(a) && POS(result)) ||
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(NEG(b) && POS(result)) ) ;
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}
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/***************************************************************************\
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* Assigns the V flag after an addition of a and b to give result *
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\***************************************************************************/
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void ARMul_AddOverflow(ARMul_State *state, ARMword a,ARMword b,ARMword result)
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{
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ASSIGNV( (NEG(a) && NEG(b) && POS(result)) ||
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(POS(a) && POS(b) && NEG(result)) ) ;
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}
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/***************************************************************************\
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* Assigns the C flag after an subtraction of a and b to give result *
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\***************************************************************************/
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void ARMul_SubCarry(ARMul_State *state, ARMword a,ARMword b,ARMword result)
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{
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ASSIGNC( (NEG(a) && POS(b)) ||
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(NEG(a) && POS(result)) ||
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(POS(b) && POS(result)) ) ;
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}
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/***************************************************************************\
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* Assigns the V flag after an subtraction of a and b to give result *
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\***************************************************************************/
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void ARMul_SubOverflow(ARMul_State *state,ARMword a,ARMword b,ARMword result)
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{
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ASSIGNV( (NEG(a) && POS(b) && POS(result)) ||
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(POS(a) && NEG(b) && NEG(result)) ) ;
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}
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/***************************************************************************\
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* This function does the work of generating the addresses used in an *
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* LDC instruction. The code here is always post-indexed, it's up to the *
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* caller to get the input address correct and to handle base register *
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* modification. It also handles the Busy-Waiting. *
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\***************************************************************************/
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void ARMul_LDC(ARMul_State *state,ARMword instr,ARMword address)
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{unsigned cpab ;
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ARMword data ;
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UNDEF_LSCPCBaseWb ;
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if (ADDREXCEPT(address)) {
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INTERNALABORT(address) ;
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}
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cpab = (state->LDC[CPNum])(state,ARMul_FIRST,instr,0) ;
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while (cpab == ARMul_BUSY) {
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ARMul_Icycles(state,1,0) ;
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if (IntPending(state)) {
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cpab = (state->LDC[CPNum])(state,ARMul_INTERRUPT,instr,0) ;
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return ;
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}
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else
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cpab = (state->LDC[CPNum])(state,ARMul_BUSY,instr,0) ;
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}
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if (cpab == ARMul_CANT) {
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CPTAKEABORT ;
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return ;
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}
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cpab = (state->LDC[CPNum])(state,ARMul_TRANSFER,instr,0) ;
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data = ARMul_LoadWordN(state,address) ;
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BUSUSEDINCPCN ;
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if (BIT(21))
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LSBase = state->Base ;
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cpab = (state->LDC[CPNum])(state,ARMul_DATA,instr,data) ;
|
|
while (cpab == ARMul_INC) {
|
|
address += 4 ;
|
|
data = ARMul_LoadWordN(state,address) ;
|
|
cpab = (state->LDC[CPNum])(state,ARMul_DATA,instr,data) ;
|
|
}
|
|
if (state->abortSig || state->Aborted) {
|
|
TAKEABORT ;
|
|
}
|
|
}
|
|
|
|
/***************************************************************************\
|
|
* This function does the work of generating the addresses used in an *
|
|
* STC instruction. The code here is always post-indexed, it's up to the *
|
|
* caller to get the input address correct and to handle base register *
|
|
* modification. It also handles the Busy-Waiting. *
|
|
\***************************************************************************/
|
|
|
|
void ARMul_STC(ARMul_State *state,ARMword instr,ARMword address)
|
|
{unsigned cpab ;
|
|
ARMword data ;
|
|
|
|
UNDEF_LSCPCBaseWb ;
|
|
if (ADDREXCEPT(address) || VECTORACCESS(address)) {
|
|
INTERNALABORT(address) ;
|
|
}
|
|
cpab = (state->STC[CPNum])(state,ARMul_FIRST,instr,&data) ;
|
|
while (cpab == ARMul_BUSY) {
|
|
ARMul_Icycles(state,1,0) ;
|
|
if (IntPending(state)) {
|
|
cpab = (state->STC[CPNum])(state,ARMul_INTERRUPT,instr,0) ;
|
|
return ;
|
|
}
|
|
else
|
|
cpab = (state->STC[CPNum])(state,ARMul_BUSY,instr,&data) ;
|
|
}
|
|
if (cpab == ARMul_CANT) {
|
|
CPTAKEABORT ;
|
|
return ;
|
|
}
|
|
#ifndef MODE32
|
|
if (ADDREXCEPT(address) || VECTORACCESS(address)) {
|
|
INTERNALABORT(address) ;
|
|
}
|
|
#endif
|
|
BUSUSEDINCPCN ;
|
|
if (BIT(21))
|
|
LSBase = state->Base ;
|
|
cpab = (state->STC[CPNum])(state,ARMul_DATA,instr,&data) ;
|
|
ARMul_StoreWordN(state,address,data) ;
|
|
while (cpab == ARMul_INC) {
|
|
address += 4 ;
|
|
cpab = (state->STC[CPNum])(state,ARMul_DATA,instr,&data) ;
|
|
ARMul_StoreWordN(state,address,data) ;
|
|
}
|
|
if (state->abortSig || state->Aborted) {
|
|
TAKEABORT ;
|
|
}
|
|
}
|
|
|
|
/***************************************************************************\
|
|
* This function does the Busy-Waiting for an MCR instruction. *
|
|
\***************************************************************************/
|
|
|
|
void ARMul_MCR(ARMul_State *state,ARMword instr, ARMword source)
|
|
{unsigned cpab ;
|
|
|
|
cpab = (state->MCR[CPNum])(state,ARMul_FIRST,instr,source) ;
|
|
while (cpab == ARMul_BUSY) {
|
|
ARMul_Icycles(state,1,0) ;
|
|
if (IntPending(state)) {
|
|
cpab = (state->MCR[CPNum])(state,ARMul_INTERRUPT,instr,0) ;
|
|
return ;
|
|
}
|
|
else
|
|
cpab = (state->MCR[CPNum])(state,ARMul_BUSY,instr,source) ;
|
|
}
|
|
if (cpab == ARMul_CANT)
|
|
ARMul_Abort(state,ARMul_UndefinedInstrV) ;
|
|
else {
|
|
BUSUSEDINCPCN ;
|
|
ARMul_Ccycles(state,1,0) ;
|
|
}
|
|
}
|
|
|
|
/***************************************************************************\
|
|
* This function does the Busy-Waiting for an MRC instruction. *
|
|
\***************************************************************************/
|
|
|
|
ARMword ARMul_MRC(ARMul_State *state,ARMword instr)
|
|
{unsigned cpab ;
|
|
ARMword result = 0 ;
|
|
|
|
cpab = (state->MRC[CPNum])(state,ARMul_FIRST,instr,&result) ;
|
|
while (cpab == ARMul_BUSY) {
|
|
ARMul_Icycles(state,1,0) ;
|
|
if (IntPending(state)) {
|
|
cpab = (state->MRC[CPNum])(state,ARMul_INTERRUPT,instr,0) ;
|
|
return(0) ;
|
|
}
|
|
else
|
|
cpab = (state->MRC[CPNum])(state,ARMul_BUSY,instr,&result) ;
|
|
}
|
|
if (cpab == ARMul_CANT) {
|
|
ARMul_Abort(state,ARMul_UndefinedInstrV) ;
|
|
result = ECC ; /* Parent will destroy the flags otherwise */
|
|
}
|
|
else {
|
|
BUSUSEDINCPCN ;
|
|
ARMul_Ccycles(state,1,0) ;
|
|
ARMul_Icycles(state,1,0) ;
|
|
}
|
|
return(result) ;
|
|
}
|
|
|
|
/***************************************************************************\
|
|
* This function does the Busy-Waiting for an CDP instruction. *
|
|
\***************************************************************************/
|
|
|
|
void ARMul_CDP(ARMul_State *state,ARMword instr)
|
|
{unsigned cpab ;
|
|
|
|
cpab = (state->CDP[CPNum])(state,ARMul_FIRST,instr) ;
|
|
while (cpab == ARMul_BUSY) {
|
|
ARMul_Icycles(state,1,0) ;
|
|
if (IntPending(state)) {
|
|
cpab = (state->CDP[CPNum])(state,ARMul_INTERRUPT,instr) ;
|
|
return ;
|
|
}
|
|
else
|
|
cpab = (state->CDP[CPNum])(state,ARMul_BUSY,instr) ;
|
|
}
|
|
if (cpab == ARMul_CANT)
|
|
ARMul_Abort(state,ARMul_UndefinedInstrV) ;
|
|
else
|
|
BUSUSEDN ;
|
|
}
|
|
|
|
/***************************************************************************\
|
|
* This function handles Undefined instructions, as CP isntruction *
|
|
\***************************************************************************/
|
|
|
|
void ARMul_UndefInstr(ARMul_State *state,ARMword instr)
|
|
{
|
|
ARMul_Abort(state,ARMul_UndefinedInstrV) ;
|
|
}
|
|
|
|
/***************************************************************************\
|
|
* Return TRUE if an interrupt is pending, FALSE otherwise. *
|
|
\***************************************************************************/
|
|
|
|
unsigned IntPending(ARMul_State *state)
|
|
{
|
|
if (state->Exception) { /* Any exceptions */
|
|
if (state->NresetSig == LOW) {
|
|
ARMul_Abort(state,ARMul_ResetV) ;
|
|
return(TRUE) ;
|
|
}
|
|
else if (!state->NfiqSig && !FFLAG) {
|
|
ARMul_Abort(state,ARMul_FIQV) ;
|
|
return(TRUE) ;
|
|
}
|
|
else if (!state->NirqSig && !IFLAG) {
|
|
ARMul_Abort(state,ARMul_IRQV) ;
|
|
return(TRUE) ;
|
|
}
|
|
}
|
|
return(FALSE) ;
|
|
}
|
|
|
|
/***************************************************************************\
|
|
* Align a word access to a non word boundary *
|
|
\***************************************************************************/
|
|
|
|
ARMword ARMul_Align(ARMul_State *state, ARMword address, ARMword data)
|
|
{/* this code assumes the address is really unaligned,
|
|
as a shift by 32 is undefined in C */
|
|
|
|
address = (address & 3) << 3 ; /* get the word address */
|
|
return( ( data >> address) | (data << (32 - address)) ) ; /* rot right */
|
|
}
|
|
|
|
/***************************************************************************\
|
|
* This routine is used to call another routine after a certain number of *
|
|
* cycles have been executed. The first parameter is the number of cycles *
|
|
* delay before the function is called, the second argument is a pointer *
|
|
* to the function. A delay of zero doesn't work, just call the function. *
|
|
\***************************************************************************/
|
|
|
|
void ARMul_ScheduleEvent(ARMul_State *state, unsigned long delay, unsigned (*what)())
|
|
{unsigned long when ;
|
|
struct EventNode *event ;
|
|
|
|
if (state->EventSet++ == 0)
|
|
state->Now = ARMul_Time(state) ;
|
|
when = (state->Now + delay) % EVENTLISTSIZE ;
|
|
event = (struct EventNode *)malloc(sizeof(struct EventNode)) ;
|
|
event->func = what ;
|
|
event->next = *(state->EventPtr + when) ;
|
|
*(state->EventPtr + when) = event ;
|
|
}
|
|
|
|
/***************************************************************************\
|
|
* This routine is called at the beginning of every cycle, to envoke *
|
|
* scheduled events. *
|
|
\***************************************************************************/
|
|
|
|
void ARMul_EnvokeEvent(ARMul_State *state)
|
|
{static unsigned long then ;
|
|
|
|
then = state->Now ;
|
|
state->Now = ARMul_Time(state) % EVENTLISTSIZE ;
|
|
if (then < state->Now) /* schedule events */
|
|
EnvokeList(state,then,state->Now) ;
|
|
else if (then > state->Now) { /* need to wrap around the list */
|
|
EnvokeList(state,then,EVENTLISTSIZE-1L) ;
|
|
EnvokeList(state,0L,state->Now) ;
|
|
}
|
|
}
|
|
|
|
static void EnvokeList(ARMul_State *state, unsigned long from, unsigned long to)
|
|
/* envokes all the entries in a range */
|
|
{struct EventNode *anevent ;
|
|
|
|
for (; from <= to ; from++) {
|
|
anevent = *(state->EventPtr + from) ;
|
|
while (anevent) {
|
|
(anevent->func)(state) ;
|
|
state->EventSet-- ;
|
|
anevent = anevent->next ;
|
|
}
|
|
*(state->EventPtr + from) = NULL ;
|
|
}
|
|
}
|
|
|
|
/***************************************************************************\
|
|
* This routine is returns the number of clock ticks since the last reset. *
|
|
\***************************************************************************/
|
|
|
|
unsigned long ARMul_Time(ARMul_State *state)
|
|
{return(state->NumScycles + state->NumNcycles +
|
|
state->NumIcycles + state->NumCcycles + state->NumFcycles) ;
|
|
}
|