e1d6e81ff4
compiles without warnings. 2000-09-06 Scott Bambrough <scottb@netwinder.org> * arm-linux-tdep.c (arm_linux_skip_solib_resolver): Removed debug print statement. Removed arm_pc_is_thumb prototype. * config/arm/tm-arm.h (arm_pc_is_thumb, arm_pc_is_thumb_dummy): Move prototypes here from tm-embed.h. * config/arm/tm-embed.h (arm_pc_is_thumb, arm_pc_is_thumb_dummy): Remove prototypes. Moved to tm-arm.h.
523 lines
19 KiB
C
523 lines
19 KiB
C
/* Definitions to target GDB to ARM targets.
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Copyright 1986, 1987, 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#ifndef TM_ARM_H
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#define TM_ARM_H
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/* Forward declarations for prototypes. */
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struct type;
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struct value;
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/* Target byte order on ARM defaults to selectable, and defaults to
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little endian. */
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#define TARGET_BYTE_ORDER_SELECTABLE_P 1
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#define TARGET_BYTE_ORDER_DEFAULT LITTLE_ENDIAN
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/* IEEE format floating point. */
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#define IEEE_FLOAT (1)
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#define TARGET_DOUBLE_FORMAT (target_byte_order == BIG_ENDIAN \
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? &floatformat_ieee_double_big \
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: &floatformat_ieee_double_littlebyte_bigword)
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/* When reading symbols, we need to zap the low bit of the address,
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which may be set to 1 for Thumb functions. */
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#define SMASH_TEXT_ADDRESS(addr) ((addr) &= ~0x1)
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/* Remove useless bits from addresses in a running program. */
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CORE_ADDR arm_addr_bits_remove (CORE_ADDR);
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#define ADDR_BITS_REMOVE(val) (arm_addr_bits_remove (val))
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/* Offset from address of function to start of its code. Zero on most
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machines. */
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#define FUNCTION_START_OFFSET 0
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/* Advance PC across any function entry prologue instructions to reach
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some "real" code. */
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extern CORE_ADDR arm_skip_prologue (CORE_ADDR pc);
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#define SKIP_PROLOGUE(pc) (arm_skip_prologue (pc))
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/* Immediately after a function call, return the saved pc. Can't
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always go through the frames for this because on some machines the
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new frame is not set up until the new function executes some
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instructions. */
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#define SAVED_PC_AFTER_CALL(frame) arm_saved_pc_after_call (frame)
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struct frame_info;
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extern CORE_ADDR arm_saved_pc_after_call (struct frame_info *);
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/* The following define instruction sequences that will cause ARM
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cpu's to take an undefined instruction trap. These are used to
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signal a breakpoint to GDB.
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The newer ARMv4T cpu's are capable of operating in ARM or Thumb
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modes. A different instruction is required for each mode. The ARM
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cpu's can also be big or little endian. Thus four different
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instructions are needed to support all cases.
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Note: ARMv4 defines several new instructions that will take the
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undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
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not in fact add the new instructions. The new undefined
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instructions in ARMv4 are all instructions that had no defined
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behaviour in earlier chips. There is no guarantee that they will
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raise an exception, but may be treated as NOP's. In practice, it
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may only safe to rely on instructions matching:
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3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
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1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
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Even this may only true if the condition predicate is true. The
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following use a condition predicate of ALWAYS so it is always TRUE.
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There are other ways of forcing a breakpoint. ARM Linux, RisciX,
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and I suspect NetBSD will all use a software interrupt rather than
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an undefined instruction to force a trap. This can be handled by
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redefining some or all of the following in a target dependent
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fashion. */
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#define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
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#define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
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#define THUMB_LE_BREAKPOINT {0xfe,0xdf}
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#define THUMB_BE_BREAKPOINT {0xdf,0xfe}
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/* Stack grows downward. */
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#define INNER_THAN(lhs,rhs) ((lhs) < (rhs))
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/* !!!! if we're using RDP, then we're inserting breakpoints and
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storing their handles instread of what was in memory. It is nice
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that this is the same size as a handle - otherwise remote-rdp will
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have to change. */
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/* BREAKPOINT_FROM_PC uses the program counter value to determine
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whether a 16- or 32-bit breakpoint should be used. It returns a
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pointer to a string of bytes that encode a breakpoint instruction,
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stores the length of the string to *lenptr, and adjusts the pc (if
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necessary) to point to the actual memory location where the
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breakpoint should be inserted. */
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extern breakpoint_from_pc_fn arm_breakpoint_from_pc;
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#define BREAKPOINT_FROM_PC(pcptr, lenptr) arm_breakpoint_from_pc (pcptr, lenptr)
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/* Amount PC must be decremented by after a breakpoint. This is often
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the number of bytes in BREAKPOINT but not always. */
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#define DECR_PC_AFTER_BREAK 0
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/* Code to execute to print interesting information about the floating
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point processor (if any) or emulator. No need to define if there
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is nothing to do. */
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extern void arm_float_info (void);
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#define FLOAT_INFO { arm_float_info (); }
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/* Say how long (ordinary) registers are. This is a piece of bogosity
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used in push_word and a few other places; REGISTER_RAW_SIZE is the
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real way to know how big a register is. */
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#define REGISTER_SIZE 4
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/* Say how long FP registers are. Used for documentation purposes and
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code readability in this header. IEEE extended doubles are 80
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bits. DWORD aligned they use 96 bits. */
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#define FP_REGISTER_RAW_SIZE 12
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/* GCC doesn't support long doubles (extended IEEE values). The FP
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register virtual size is therefore 64 bits. Used for documentation
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purposes and code readability in this header. */
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#define FP_REGISTER_VIRTUAL_SIZE 8
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/* Status registers are the same size as general purpose registers.
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Used for documentation purposes and code readability in this
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header. */
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#define STATUS_REGISTER_SIZE REGISTER_SIZE
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/* Number of machine registers. The only define actually required
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is NUM_REGS. The other definitions are used for documentation
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purposes and code readability. */
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/* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
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(and called PS for processor status) so the status bits can be cleared
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from the PC (register 15). For 32 bit ARM code, a copy of CPSR is placed
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in PS. */
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#define NUM_FREGS 8 /* Number of floating point registers. */
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#define NUM_SREGS 2 /* Number of status registers. */
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#define NUM_GREGS 16 /* Number of general purpose registers. */
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#define NUM_REGS (NUM_GREGS + NUM_FREGS + NUM_SREGS)
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/* An array of names of registers. */
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extern char **arm_register_names;
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#define REGISTER_NAME(i) arm_register_names[i]
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/* Register numbers of various important registers. Note that some of
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these values are "real" register numbers, and correspond to the
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general registers of the machine, and some are "phony" register
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numbers which are too large to be actual register numbers as far as
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the user is concerned but do serve to get the desired values when
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passed to read_register. */
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#define A1_REGNUM 0 /* first integer-like argument */
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#define A4_REGNUM 3 /* last integer-like argument */
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#define AP_REGNUM 11
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#define FP_REGNUM 11 /* Contains address of executing stack frame */
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#define SP_REGNUM 13 /* Contains address of top of stack */
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#define LR_REGNUM 14 /* address to return to from a function call */
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#define PC_REGNUM 15 /* Contains program counter */
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#define F0_REGNUM 16 /* first floating point register */
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#define F3_REGNUM 19 /* last floating point argument register */
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#define F7_REGNUM 23 /* last floating point register */
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#define FPS_REGNUM 24 /* floating point status register */
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#define PS_REGNUM 25 /* Contains processor status */
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#define THUMB_FP_REGNUM 7 /* R7 is frame register on Thumb */
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#define ARM_NUM_ARG_REGS 4
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#define ARM_LAST_ARG_REGNUM A4_REGNUM
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#define ARM_NUM_FP_ARG_REGS 4
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#define ARM_LAST_FP_ARG_REGNUM F3_REGNUM
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/* Instruction condition field values. */
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#define INST_EQ 0x0
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#define INST_NE 0x1
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#define INST_CS 0x2
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#define INST_CC 0x3
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#define INST_MI 0x4
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#define INST_PL 0x5
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#define INST_VS 0x6
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#define INST_VC 0x7
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#define INST_HI 0x8
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#define INST_LS 0x9
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#define INST_GE 0xa
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#define INST_LT 0xb
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#define INST_GT 0xc
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#define INST_LE 0xd
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#define INST_AL 0xe
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#define INST_NV 0xf
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#define FLAG_N 0x80000000
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#define FLAG_Z 0x40000000
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#define FLAG_C 0x20000000
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#define FLAG_V 0x10000000
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/* Total amount of space needed to store our copies of the machine's
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register state, the array `registers'. */
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#define REGISTER_BYTES ((NUM_GREGS * REGISTER_SIZE) + \
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(NUM_FREGS * FP_REGISTER_RAW_SIZE) + \
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(NUM_SREGS * STATUS_REGISTER_SIZE))
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/* Index within `registers' of the first byte of the space for
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register N. */
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#define REGISTER_BYTE(N) \
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((N) < F0_REGNUM \
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? (N) * REGISTER_SIZE \
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: ((N) < PS_REGNUM \
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? (NUM_GREGS * REGISTER_SIZE + \
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((N) - F0_REGNUM) * FP_REGISTER_RAW_SIZE) \
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: (NUM_GREGS * REGISTER_SIZE + \
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NUM_FREGS * FP_REGISTER_RAW_SIZE + \
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((N) - FPS_REGNUM) * STATUS_REGISTER_SIZE)))
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/* Number of bytes of storage in the actual machine representation for
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register N. All registers are 4 bytes, except fp0 - fp7, which are
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12 bytes in length. */
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#define REGISTER_RAW_SIZE(N) \
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((N) < F0_REGNUM ? REGISTER_SIZE : \
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(N) < FPS_REGNUM ? FP_REGISTER_RAW_SIZE : STATUS_REGISTER_SIZE)
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/* Number of bytes of storage in a program's representation
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for register N. */
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#define REGISTER_VIRTUAL_SIZE(N) \
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((N) < F0_REGNUM ? REGISTER_SIZE : \
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(N) < FPS_REGNUM ? FP_REGISTER_VIRTUAL_SIZE : STATUS_REGISTER_SIZE)
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/* Largest value REGISTER_RAW_SIZE can have. */
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#define MAX_REGISTER_RAW_SIZE FP_REGISTER_RAW_SIZE
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/* Largest value REGISTER_VIRTUAL_SIZE can have. */
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#define MAX_REGISTER_VIRTUAL_SIZE FP_REGISTER_VIRTUAL_SIZE
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/* Nonzero if register N requires conversion from raw format to
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virtual format. */
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extern int arm_register_convertible (unsigned int);
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#define REGISTER_CONVERTIBLE(REGNUM) (arm_register_convertible (REGNUM))
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/* Convert data from raw format for register REGNUM in buffer FROM to
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virtual format with type TYPE in buffer TO. */
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extern void arm_register_convert_to_virtual (unsigned int regnum,
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struct type *type,
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void *from, void *to);
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#define REGISTER_CONVERT_TO_VIRTUAL(REGNUM,TYPE,FROM,TO) \
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arm_register_convert_to_virtual (REGNUM, TYPE, FROM, TO)
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/* Convert data from virtual format with type TYPE in buffer FROM to
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raw format for register REGNUM in buffer TO. */
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extern void arm_register_convert_to_raw (unsigned int regnum,
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struct type *type,
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void *from, void *to);
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#define REGISTER_CONVERT_TO_RAW(TYPE,REGNUM,FROM,TO) \
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arm_register_convert_to_raw (REGNUM, TYPE, FROM, TO)
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/* Return the GDB type object for the "standard" data type of data in
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register N. */
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#define REGISTER_VIRTUAL_TYPE(N) \
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(((unsigned)(N) - F0_REGNUM) < NUM_FREGS \
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? builtin_type_double : builtin_type_int)
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/* The system C compiler uses a similar structure return convention to gcc */
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extern use_struct_convention_fn arm_use_struct_convention;
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#define USE_STRUCT_CONVENTION(gcc_p, type) \
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arm_use_struct_convention (gcc_p, type)
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/* Store the address of the place in which to copy the structure the
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subroutine will return. This is called from call_function. */
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#define STORE_STRUCT_RETURN(ADDR, SP) \
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write_register (A1_REGNUM, (ADDR))
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/* Extract from an array REGBUF containing the (raw) register state a
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function return value of type TYPE, and copy that, in virtual
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format, into VALBUF. */
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extern void arm_extract_return_value (struct type *, char[], char *);
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#define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
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arm_extract_return_value ((TYPE), (REGBUF), (VALBUF))
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/* Write into appropriate registers a function return value of type
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TYPE, given in virtual format. */
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extern void convert_to_extended (void *dbl, void *ptr);
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#define STORE_RETURN_VALUE(TYPE,VALBUF) \
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if (TYPE_CODE (TYPE) == TYPE_CODE_FLT) { \
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char _buf[MAX_REGISTER_RAW_SIZE]; \
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convert_to_extended (VALBUF, _buf); \
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write_register_bytes (REGISTER_BYTE (F0_REGNUM), _buf, MAX_REGISTER_RAW_SIZE); \
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} else \
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write_register_bytes (0, VALBUF, TYPE_LENGTH (TYPE))
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/* Extract from an array REGBUF containing the (raw) register state
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the address in which a function should return its structure value,
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as a CORE_ADDR (or an expression that can be used as one). */
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#define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
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(extract_address ((PTR)(REGBUF), REGISTER_RAW_SIZE(0)))
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/* Specify that for the native compiler variables for a particular
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lexical context are listed after the beginning LBRAC instead of
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before in the executables list of symbols. */
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#define VARIABLES_INSIDE_BLOCK(desc, gcc_p) (!(gcc_p))
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/* Define other aspects of the stack frame. We keep the offsets of
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all saved registers, 'cause we need 'em a lot! We also keep the
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current size of the stack frame, and the offset of the frame
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pointer from the stack pointer (for frameless functions, and when
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we're still in the prologue of a function with a frame) */
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#define EXTRA_FRAME_INFO \
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struct frame_saved_regs fsr; \
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int framesize; \
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int frameoffset; \
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int framereg;
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extern void arm_init_extra_frame_info (int fromleaf, struct frame_info * fi);
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#define INIT_EXTRA_FRAME_INFO(fromleaf, fi) \
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arm_init_extra_frame_info ((fromleaf), (fi))
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/* Return the frame address. On ARM, it is R11; on Thumb it is R7. */
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CORE_ADDR arm_target_read_fp (void);
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#define TARGET_READ_FP() arm_target_read_fp ()
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/* Describe the pointer in each stack frame to the previous stack
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frame (its caller). */
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/* FRAME_CHAIN takes a frame's nominal address and produces the
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frame's chain-pointer.
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However, if FRAME_CHAIN_VALID returns zero,
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it means the given frame is the outermost one and has no caller. */
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#define FRAME_CHAIN(thisframe) arm_frame_chain (thisframe)
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extern CORE_ADDR arm_frame_chain (struct frame_info *);
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extern int arm_frame_chain_valid (CORE_ADDR, struct frame_info *);
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#define FRAME_CHAIN_VALID(chain, thisframe) \
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arm_frame_chain_valid (chain, thisframe)
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/* Define other aspects of the stack frame. */
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/* A macro that tells us whether the function invocation represented
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by FI does not have a frame on the stack associated with it. If it
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does not, FRAMELESS is set to 1, else 0.
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Sometimes we have functions that do a little setup (like saving the
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vN registers with the stmdb instruction, but DO NOT set up a frame.
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The symbol table will report this as a prologue. However, it is
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important not to try to parse these partial frames as frames, or we
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will get really confused.
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So I will demand 3 instructions between the start & end of the
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prologue before I call it a real prologue, i.e. at least
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mov ip, sp,
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stmdb sp!, {}
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sub sp, ip, #4. */
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extern int arm_frameless_function_invocation (struct frame_info *fi);
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#define FRAMELESS_FUNCTION_INVOCATION(FI) \
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(arm_frameless_function_invocation (FI))
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/* Saved Pc. */
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#define FRAME_SAVED_PC(FRAME) arm_frame_saved_pc (FRAME)
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extern CORE_ADDR arm_frame_saved_pc (struct frame_info *);
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#define FRAME_ARGS_ADDRESS(fi) (fi->frame)
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#define FRAME_LOCALS_ADDRESS(fi) ((fi)->frame)
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/* Return number of args passed to a frame.
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Can return -1, meaning no way to tell. */
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#define FRAME_NUM_ARGS(fi) (-1)
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/* Return number of bytes at start of arglist that are not really args. */
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#define FRAME_ARGS_SKIP 0
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/* Put here the code to store, into a struct frame_saved_regs, the
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addresses of the saved registers of frame described by FRAME_INFO.
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This includes special registers such as pc and fp saved in special
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ways in the stack frame. sp is even more special: the address we
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return for it IS the sp for the next frame. */
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struct frame_saved_regs;
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struct frame_info;
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void arm_frame_find_saved_regs (struct frame_info * fi,
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struct frame_saved_regs * fsr);
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#define FRAME_FIND_SAVED_REGS(frame_info, frame_saved_regs) \
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arm_frame_find_saved_regs (frame_info, &(frame_saved_regs));
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/* Things needed for making the inferior call functions. */
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#define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
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sp = arm_push_arguments ((nargs), (args), (sp), (struct_return), (struct_addr))
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extern CORE_ADDR arm_push_arguments (int, struct value **, CORE_ADDR, int,
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CORE_ADDR);
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/* Push an empty stack frame, to record the current PC, etc. */
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void arm_push_dummy_frame (void);
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#define PUSH_DUMMY_FRAME arm_push_dummy_frame ()
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/* Discard from the stack the innermost frame, restoring all registers. */
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void arm_pop_frame (void);
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#define POP_FRAME arm_pop_frame ()
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/* This sequence of words is the instructions
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mov lr,pc
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mov pc,r4
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||
illegal
|
||
|
||
Note this is 12 bytes. */
|
||
|
||
#define CALL_DUMMY {0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe}
|
||
#define CALL_DUMMY_START_OFFSET 0 /* Start execution at beginning of dummy */
|
||
|
||
#define CALL_DUMMY_BREAKPOINT_OFFSET arm_call_dummy_breakpoint_offset()
|
||
extern int arm_call_dummy_breakpoint_offset (void);
|
||
|
||
/* Insert the specified number of args and function address into a
|
||
call sequence of the above form stored at DUMMYNAME. */
|
||
|
||
#define FIX_CALL_DUMMY(dummyname, pc, fun, nargs, args, type, gcc_p) \
|
||
arm_fix_call_dummy ((dummyname), (pc), (fun), (nargs), (args), (type), (gcc_p))
|
||
|
||
void arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun,
|
||
int nargs, struct value ** args,
|
||
struct type * type, int gcc_p);
|
||
|
||
CORE_ADDR arm_get_next_pc (CORE_ADDR pc);
|
||
|
||
/* Macros for setting and testing a bit in a minimal symbol that marks
|
||
it as Thumb function. The MSB of the minimal symbol's "info" field
|
||
is used for this purpose. This field is already being used to store
|
||
the symbol size, so the assumption is that the symbol size cannot
|
||
exceed 2^31.
|
||
|
||
COFF_MAKE_MSYMBOL_SPECIAL
|
||
ELF_MAKE_MSYMBOL_SPECIAL
|
||
|
||
These macros test whether the COFF or ELF symbol corresponds to a
|
||
thumb function, and set a "special" bit in a minimal symbol to
|
||
indicate that it does.
|
||
|
||
MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
|
||
MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol.
|
||
MSYMBOL_SIZE Returns the size of the minimal symbol,
|
||
i.e. the "info" field with the "special" bit
|
||
masked out
|
||
*/
|
||
|
||
extern int coff_sym_is_thumb (int val);
|
||
|
||
#define MSYMBOL_SET_SPECIAL(msym) \
|
||
MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000)
|
||
#define MSYMBOL_IS_SPECIAL(msym) \
|
||
(((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
|
||
#define MSYMBOL_SIZE(msym) \
|
||
((long) MSYMBOL_INFO (msym) & 0x7fffffff)
|
||
|
||
/* Thumb symbols are of type STT_LOPROC, (synonymous with STT_ARM_TFUNC) */
|
||
#define ELF_MAKE_MSYMBOL_SPECIAL(sym,msym) \
|
||
{ if(ELF_ST_TYPE(((elf_symbol_type *)(sym))->internal_elf_sym.st_info) == STT_LOPROC) \
|
||
MSYMBOL_SET_SPECIAL(msym); }
|
||
|
||
#define COFF_MAKE_MSYMBOL_SPECIAL(val,msym) \
|
||
{ if(coff_sym_is_thumb(val)) MSYMBOL_SET_SPECIAL(msym); }
|
||
|
||
/* The first 0x20 bytes are the trap vectors. */
|
||
#define LOWEST_PC 0x20
|
||
|
||
/* Function to determine whether MEMADDR is in a Thumb function. */
|
||
extern int arm_pc_is_thumb (bfd_vma memaddr);
|
||
|
||
/* Function to determine whether MEMADDR is in a call dummy called from
|
||
a Thumb function. */
|
||
extern int arm_pc_is_thumb_dummy (bfd_vma memaddr);
|
||
|
||
#endif /* TM_ARM_H */
|