1a1077dec5
systems with a separate instruction and data cache, such as the 29040, these instructions take an optional argument.
285 lines
9.9 KiB
C
285 lines
9.9 KiB
C
/* Table of opcodes for the AMD 29000 family.
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Copyright 1990, 1991, 1992, 1993 Free Software Foundation, Inc.
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This file is part of GDB and GAS.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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struct a29k_opcode {
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/* Name of the instruction. */
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char *name;
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/* Opcode word */
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unsigned long opcode;
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/* A string of characters which describe the operands.
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Valid characters are:
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, Itself. The character appears in the assembly code.
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a RA. The register number is in bits 8-15 of the instruction.
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b RB. The register number is in bits 0-7 of the instruction.
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c RC. The register number is in bits 16-23 of the instruction.
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i An immediate operand is in bits 0-7 of the instruction.
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x Bits 0-7 and 16-23 of the instruction are bits 0-7 and 8-15
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(respectively) of the immediate operand.
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h Same as x but the instruction contains bits 16-31 of the
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immediate operand.
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X Same as x but bits 16-31 of the signed immediate operand
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are set to 1 (thus the operand is always negative).
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P,A Bits 0-7 and 16-23 of the instruction are bits 2-9 and 10-17
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(respectively) of the immediate operand.
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P=PC-relative, sign-extended to 32 bits.
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A=Absolute, zero-extended to 32 bits.
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e CE bit (bit 23) for a load/store instruction.
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n Control field (bits 16-22) for a load/store instruction.
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v Immediate operand in bits 16-23 of the instruction.
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(used for trap numbers).
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s SA. Special-purpose register number in bits 8-15
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of the instruction.
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u UI--bit 7 of the instruction.
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r RND--bits 4-6 of the instruction.
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d FD--bits 2-3 of the instruction.
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f FS--bits 0-1 of the instruction.
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I ID--bits 16-17 of the instruction.
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Extensions for 29050:
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d FMT--bits 2-3 of the instruction (not really new).
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f ACN--bits 0-1 of the instruction (not really new).
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F FUNC--Special function in bits 18-21 of the instruction.
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C ACN--bits 16-17 specifying the accumlator register. */
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char *args;
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};
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#ifndef CONST
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#define CONST
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#endif /* CONST */
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static CONST struct a29k_opcode a29k_opcodes[] =
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{
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{ "add", 0x14000000, "c,a,b" },
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{ "add", 0x15000000, "c,a,i" },
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{ "addc", 0x1c000000, "c,a,b" },
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{ "addc", 0x1d000000, "c,a,i" },
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{ "addcs", 0x18000000, "c,a,b" },
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{ "addcs", 0x19000000, "c,a,i" },
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{ "addcu", 0x1a000000, "c,a,b" },
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{ "addcu", 0x1b000000, "c,a,i" },
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{ "adds", 0x10000000, "c,a,b" },
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{ "adds", 0x11000000, "c,a,i" },
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{ "addu", 0x12000000, "c,a,b" },
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{ "addu", 0x13000000, "c,a,i" },
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{ "and", 0x90000000, "c,a,b" },
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{ "and", 0x91000000, "c,a,i" },
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{ "andn", 0x9c000000, "c,a,b" },
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{ "andn", 0x9d000000, "c,a,i" },
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{ "aseq", 0x70000000, "v,a,b" },
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{ "aseq", 0x71000000, "v,a,i" },
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{ "asge", 0x5c000000, "v,a,b" },
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{ "asge", 0x5d000000, "v,a,i" },
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{ "asgeu", 0x5e000000, "v,a,b" },
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{ "asgeu", 0x5f000000, "v,a,i" },
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{ "asgt", 0x58000000, "v,a,b" },
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{ "asgt", 0x59000000, "v,a,i" },
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{ "asgtu", 0x5a000000, "v,a,b" },
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{ "asgtu", 0x5b000000, "v,a,i" },
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{ "asle", 0x54000000, "v,a,b" },
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{ "asle", 0x55000000, "v,a,i" },
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{ "asleu", 0x56000000, "v,a,b" },
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{ "asleu", 0x57000000, "v,a,i" },
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{ "aslt", 0x50000000, "v,a,b" },
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{ "aslt", 0x51000000, "v,a,i" },
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{ "asltu", 0x52000000, "v,a,b" },
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{ "asltu", 0x53000000, "v,a,i" },
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{ "asneq", 0x72000000, "v,a,b" },
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{ "asneq", 0x73000000, "v,a,i" },
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{ "call", 0xa8000000, "a,P" },
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{ "call", 0xa9000000, "a,A" },
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{ "calli", 0xc8000000, "a,b" },
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{ "class", 0xe6000000, "c,a,f" },
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{ "clz", 0x08000000, "c,b" },
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{ "clz", 0x09000000, "c,i" },
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{ "const", 0x03000000, "a,x" },
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{ "consth", 0x02000000, "a,h" },
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{ "consthz", 0x05000000, "a,h" },
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{ "constn", 0x01000000, "a,X" },
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{ "convert", 0xe4000000, "c,a,u,r,d,f" },
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{ "cpbyte", 0x2e000000, "c,a,b" },
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{ "cpbyte", 0x2f000000, "c,a,i" },
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{ "cpeq", 0x60000000, "c,a,b" },
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{ "cpeq", 0x61000000, "c,a,i" },
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{ "cpge", 0x4c000000, "c,a,b" },
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{ "cpge", 0x4d000000, "c,a,i" },
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{ "cpgeu", 0x4e000000, "c,a,b" },
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{ "cpgeu", 0x4f000000, "c,a,i" },
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{ "cpgt", 0x48000000, "c,a,b" },
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{ "cpgt", 0x49000000, "c,a,i" },
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{ "cpgtu", 0x4a000000, "c,a,b" },
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{ "cpgtu", 0x4b000000, "c,a,i" },
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{ "cple", 0x44000000, "c,a,b" },
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{ "cple", 0x45000000, "c,a,i" },
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{ "cpleu", 0x46000000, "c,a,b" },
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{ "cpleu", 0x47000000, "c,a,i" },
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{ "cplt", 0x40000000, "c,a,b" },
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{ "cplt", 0x41000000, "c,a,i" },
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{ "cpltu", 0x42000000, "c,a,b" },
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{ "cpltu", 0x43000000, "c,a,i" },
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{ "cpneq", 0x62000000, "c,a,b" },
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{ "cpneq", 0x63000000, "c,a,i" },
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{ "dadd", 0xf1000000, "c,a,b" },
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{ "ddiv", 0xf7000000, "c,a,b" },
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{ "deq", 0xeb000000, "c,a,b" },
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{ "dge", 0xef000000, "c,a,b" },
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{ "dgt", 0xed000000, "c,a,b" },
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{ "div", 0x6a000000, "c,a,b" },
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{ "div", 0x6b000000, "c,a,i" },
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{ "div0", 0x68000000, "c,b" },
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{ "div0", 0x69000000, "c,i" },
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{ "divide", 0xe1000000, "c,a,b" },
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{ "dividu", 0xe3000000, "c,a,b" },
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{ "divl", 0x6c000000, "c,a,b" },
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{ "divl", 0x6d000000, "c,a,i" },
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{ "divrem", 0x6e000000, "c,a,b" },
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{ "divrem", 0x6f000000, "c,a,i" },
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{ "dmac", 0xd9000000, "F,C,a,b" },
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{ "dmsm", 0xdb000000, "c,a,b" },
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{ "dmul", 0xf5000000, "c,a,b" },
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{ "dsub", 0xf3000000, "c,a,b" },
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{ "emulate", 0xd7000000, "v,a,b" },
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{ "exbyte", 0x0a000000, "c,a,b" },
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{ "exbyte", 0x0b000000, "c,a,i" },
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{ "exhw", 0x7c000000, "c,a,b" },
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{ "exhw", 0x7d000000, "c,a,i" },
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{ "exhws", 0x7e000000, "c,a" },
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{ "extract", 0x7a000000, "c,a,b" },
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{ "extract", 0x7b000000, "c,a,i" },
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{ "fadd", 0xf0000000, "c,a,b" },
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{ "fdiv", 0xf6000000, "c,a,b" },
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{ "fdmul", 0xf9000000, "c,a,b" },
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{ "feq", 0xea000000, "c,a,b" },
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{ "fge", 0xee000000, "c,a,b" },
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{ "fgt", 0xec000000, "c,a,b" },
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{ "fmac", 0xd8000000, "F,C,a,b" },
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{ "fmsm", 0xda000000, "c,a,b" },
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{ "fmul", 0xf4000000, "c,a,b" },
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{ "fsub", 0xf2000000, "c,a,b" },
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{ "halt", 0x89000000, "" },
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{ "inbyte", 0x0c000000, "c,a,b" },
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{ "inbyte", 0x0d000000, "c,a,i" },
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{ "inhw", 0x78000000, "c,a,b" },
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{ "inhw", 0x79000000, "c,a,i" },
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{ "inv", 0x9f000000, "I" },
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{ "iret", 0x88000000, "" },
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{ "iretinv", 0x8c000000, "I" },
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{ "jmp", 0xa0000000, "P" },
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{ "jmp", 0xa1000000, "A" },
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{ "jmpf", 0xa4000000, "a,P" },
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{ "jmpf", 0xa5000000, "a,A" },
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{ "jmpfdec", 0xb4000000, "a,P" },
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{ "jmpfdec", 0xb5000000, "a,A" },
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{ "jmpfi", 0xc4000000, "a,b" },
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{ "jmpi", 0xc0000000, "b" },
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{ "jmpt", 0xac000000, "a,P" },
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{ "jmpt", 0xad000000, "a,A" },
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{ "jmpti", 0xcc000000, "a,b" },
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{ "load", 0x16000000, "e,n,a,b" },
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{ "load", 0x17000000, "e,n,a,i" },
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{ "loadl", 0x06000000, "e,n,a,b" },
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{ "loadl", 0x07000000, "e,n,a,i" },
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{ "loadm", 0x36000000, "e,n,a,b" },
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{ "loadm", 0x37000000, "e,n,a,i" },
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{ "loadset", 0x26000000, "e,n,a,b" },
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{ "loadset", 0x27000000, "e,n,a,i" },
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{ "mfacc", 0xe9000100, "c,d,f" },
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{ "mfsr", 0xc6000000, "c,s" },
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{ "mftlb", 0xb6000000, "c,a" },
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{ "mtacc", 0xe8010000, "a,d,f" },
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{ "mtsr", 0xce000000, "s,b" },
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{ "mtsrim", 0x04000000, "s,x" },
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{ "mttlb", 0xbe000000, "a,b" },
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{ "mul", 0x64000000, "c,a,b" },
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{ "mul", 0x65000000, "c,a,i" },
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{ "mull", 0x66000000, "c,a,b" },
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{ "mull", 0x67000000, "c,a,i" },
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{ "multiplu", 0xe2000000, "c,a,b" },
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{ "multiply", 0xe0000000, "c,a,b" },
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{ "multm", 0xde000000, "c,a,b" },
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{ "multmu", 0xdf000000, "c,a,b" },
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{ "mulu", 0x74000000, "c,a,b" },
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{ "mulu", 0x75000000, "c,a,i" },
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{ "nand", 0x9a000000, "c,a,b" },
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{ "nand", 0x9b000000, "c,a,i" },
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{ "nop", 0x70400101, "" },
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{ "nor", 0x98000000, "c,a,b" },
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{ "nor", 0x99000000, "c,a,i" },
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{ "or", 0x92000000, "c,a,b" },
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{ "or", 0x93000000, "c,a,i" },
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{ "orn", 0xaa000000, "c,a,b" },
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{ "orn", 0xab000000, "c,a,i" },
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/* The description of "setip" in Chapter 8 ("instruction set") of the user's
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manual claims that these are absolute register numbers. But section
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7.2.1 explains that they are not. The latter is correct, so print
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these normally ("lr0", "lr5", etc.). */
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{ "setip", 0x9e000000, "c,a,b" },
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{ "sll", 0x80000000, "c,a,b" },
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{ "sll", 0x81000000, "c,a,i" },
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{ "sqrt", 0xe5000000, "c,a,f" },
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{ "sra", 0x86000000, "c,a,b" },
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{ "sra", 0x87000000, "c,a,i" },
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{ "srl", 0x82000000, "c,a,b" },
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{ "srl", 0x83000000, "c,a,i" },
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{ "store", 0x1e000000, "e,n,a,b" },
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{ "store", 0x1f000000, "e,n,a,i" },
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{ "storel", 0x0e000000, "e,n,a,b" },
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{ "storel", 0x0f000000, "e,n,a,i" },
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{ "storem", 0x3e000000, "e,n,a,b" },
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{ "storem", 0x3f000000, "e,n,a,i" },
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{ "sub", 0x24000000, "c,a,b" },
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{ "sub", 0x25000000, "c,a,i" },
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{ "subc", 0x2c000000, "c,a,b" },
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{ "subc", 0x2d000000, "c,a,i" },
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{ "subcs", 0x28000000, "c,a,b" },
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{ "subcs", 0x29000000, "c,a,i" },
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{ "subcu", 0x2a000000, "c,a,b" },
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{ "subcu", 0x2b000000, "c,a,i" },
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{ "subr", 0x34000000, "c,a,b" },
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{ "subr", 0x35000000, "c,a,i" },
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{ "subrc", 0x3c000000, "c,a,b" },
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{ "subrc", 0x3d000000, "c,a,i" },
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{ "subrcs", 0x38000000, "c,a,b" },
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{ "subrcs", 0x39000000, "c,a,i" },
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{ "subrcu", 0x3a000000, "c,a,b" },
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{ "subrcu", 0x3b000000, "c,a,i" },
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{ "subrs", 0x30000000, "c,a,b" },
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{ "subrs", 0x31000000, "c,a,i" },
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{ "subru", 0x32000000, "c,a,b" },
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{ "subru", 0x33000000, "c,a,i" },
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{ "subs", 0x20000000, "c,a,b" },
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{ "subs", 0x21000000, "c,a,i" },
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{ "subu", 0x22000000, "c,a,b" },
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{ "subu", 0x23000000, "c,a,i" },
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{ "xnor", 0x96000000, "c,a,b" },
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{ "xnor", 0x97000000, "c,a,i" },
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{ "xor", 0x94000000, "c,a,b" },
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{ "xor", 0x95000000, "c,a,i" },
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{ "", 0x0, "" } /* Dummy entry, not included in NUM_OPCODES. This
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lets code examine entry i+1 without checking
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if we've run off the end of the table. */
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};
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CONST unsigned int num_opcodes = (((sizeof a29k_opcodes) / (sizeof a29k_opcodes[0])) - 1);
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