1ee7d2b1c8
[ChangeLog.sky] 1998-12-08 Frank Ch. Eigler <fche@cygnus.com> * sim-main.h (sim_state): Add multi-phase load tracking fields. * sky-gdb.c (sky_option_handler): Add --load-next option handling. * mips.igen (BREAK): Add multi-phase load and printf code handling.
1183 lines
42 KiB
C
1183 lines
42 KiB
C
/* MIPS Simulator definition.
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Copyright (C) 1997, 1998 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#ifndef SIM_MAIN_H
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#define SIM_MAIN_H
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/* This simulator doesn't cache the Current Instruction Address */
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/* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
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/* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
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#define SIM_HAVE_BIENDIAN
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/* hobble some common features for moment */
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#define WITH_WATCHPOINTS 1
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#define WITH_MODULO_MEMORY 1
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#include "sim-basics.h"
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typedef address_word sim_cia;
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#include "sim-base.h"
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/* Depreciated macros and types for manipulating 64bit values. Use
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../common/sim-bits.h and ../common/sim-endian.h macros instead. */
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typedef signed64 word64;
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typedef unsigned64 uword64;
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#define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF)
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#define WORD64HI(t) (unsigned int)(((uword64)(t))>>32)
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#define SET64LO(t) (((uword64)(t))&0xFFFFFFFF)
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#define SET64HI(t) (((uword64)(t))<<32)
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#define WORD64(h,l) ((word64)((SET64HI(h)|SET64LO(l))))
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#define UWORD64(h,l) (SET64HI(h)|SET64LO(l))
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/* Sign-extend the given value (e) as a value (b) bits long. We cannot
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assume the HI32bits of the operand are zero, so we must perform a
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mask to ensure we can use the simple subtraction to sign-extend. */
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#define SIGNEXTEND(e,b) \
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((unsigned_word) \
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(((e) & ((uword64) 1 << ((b) - 1))) \
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? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \
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: ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1))))
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/* Check if a value will fit within a halfword: */
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#define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
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/* Floating-point operations: */
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#include "sim-fpu.h"
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/* FPU registers must be one of the following types. All other values
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are reserved (and undefined). */
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typedef enum {
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fmt_single = 0,
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fmt_double = 1,
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fmt_word = 4,
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fmt_long = 5,
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/* The following are well outside the normal acceptable format
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range, and are used in the register status vector. */
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fmt_unknown = 0x10000000,
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fmt_uninterpreted = 0x20000000,
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fmt_uninterpreted_32 = 0x40000000,
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fmt_uninterpreted_64 = 0x80000000U,
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} FP_formats;
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unsigned64 value_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats));
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#define ValueFPR(FPR,FMT) value_fpr (SD, CPU, cia, (FPR), (FMT))
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void store_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats fmt, unsigned64 value));
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#define StoreFPR(FPR,FMT,VALUE) store_fpr (SD, CPU, cia, (FPR), (FMT), (VALUE))
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int NaN PARAMS ((unsigned64 op, FP_formats fmt));
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int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
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int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
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unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
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unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
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unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
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unsigned64 Max PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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unsigned64 Min PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
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unsigned64 convert PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
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#define Convert(rm,op,from,to) \
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convert (SD, CPU, cia, rm, op, from, to)
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/* Macro to update FPSR condition-code field. This is complicated by
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the fact that there is a hole in the index range of the bits within
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the FCSR register. Also, the number of bits visible depends on the
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MIPS ISA version being supported. */
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#define SETFCC(cc,v) {\
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int bit = ((cc == 0) ? 23 : (24 + (cc)));\
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FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
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}
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#define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1U : 0)
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/* This should be the COC1 value at the start of the preceding
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instruction: */
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#define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
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#if 1
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#define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
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#else
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/* They depend on the CPU being simulated */
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#define SizeFGR() ((WITH_TARGET_WORD_BITSIZE == 64 && ((SR & status_FR) == 1)) ? 64 : 32)
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#endif
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/* Standard FCRS bits: */
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#define IR (0) /* Inexact Result */
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#define UF (1) /* UnderFlow */
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#define OF (2) /* OverFlow */
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#define DZ (3) /* Division by Zero */
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#define IO (4) /* Invalid Operation */
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#define UO (5) /* Unimplemented Operation */
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/* Get masks for individual flags: */
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#if 1 /* SAFE version */
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#define FP_FLAGS(b) (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
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#define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
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#define FP_CAUSE(b) (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
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#else
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#define FP_FLAGS(b) (1 << ((b) + 2))
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#define FP_ENABLE(b) (1 << ((b) + 7))
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#define FP_CAUSE(b) (1 << ((b) + 12))
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#endif
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#define FP_FS (1 << 24) /* MIPS III onwards : Flush to Zero */
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#define FP_MASK_RM (0x3)
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#define FP_SH_RM (0)
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#define FP_RM_NEAREST (0) /* Round to nearest (Round) */
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#define FP_RM_TOZERO (1) /* Round to zero (Trunc) */
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#define FP_RM_TOPINF (2) /* Round to Plus infinity (Ceil) */
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#define FP_RM_TOMINF (3) /* Round to Minus infinity (Floor) */
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#define GETRM() (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
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/* start-sanitize-sky */
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#ifdef TARGET_SKY
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#ifdef SKY_FUNIT
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#include <assert.h>
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#include "wf.h"
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#endif
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#endif
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/* end-sanitize-sky */
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/* HI/LO register accesses */
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/* For some MIPS targets, the HI/LO registers have certain timing
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restrictions in that, for instance, a read of a HI register must be
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separated by at least three instructions from a preceeding read.
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The struct below is used to record the last access by each of A MT,
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MF or other OP instruction to a HI/LO register. See mips.igen for
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more details. */
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typedef struct _hilo_access {
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signed64 timestamp;
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address_word cia;
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} hilo_access;
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typedef struct _hilo_history {
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hilo_access mt;
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hilo_access mf;
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hilo_access op;
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} hilo_history;
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/* Integer ALU operations: */
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#include "sim-alu.h"
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#define ALU32_END(ANS) \
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if (ALU32_HAD_OVERFLOW) \
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SignalExceptionIntegerOverflow (); \
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(ANS) = (signed32) ALU32_OVERFLOW_RESULT
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#define ALU64_END(ANS) \
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if (ALU64_HAD_OVERFLOW) \
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SignalExceptionIntegerOverflow (); \
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(ANS) = ALU64_OVERFLOW_RESULT;
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/* start-sanitize-r5900 */
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/* Figure 10-5 FPU Control/Status Register.
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Note: some of these bits are different to what is found in a
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standard MIPS manual. */
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enum {
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R5900_FCSR_C = BIT (23), /* OK */
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R5900_FCSR_I = BIT (17),
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R5900_FCSR_D = BIT (16),
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R5900_FCSR_O = BIT (15),
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R5900_FCSR_U = BIT (14),
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R5900_FCSR_CAUSE = MASK (16,14),
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R5900_FCSR_SI = BIT (6),
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R5900_FCSR_SD = BIT (5),
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R5900_FCSR_SO = BIT (4),
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R5900_FCSR_SU = BIT (3),
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};
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/* Table 10-1 FP format values.
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Note: some of these bits are different to what is found in a
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standard MIPS manual. */
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enum {
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R5900_EXPMAX = 128,
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R5900_EXPMIN = -127,
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R5900_EXPBIAS = 127,
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};
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/* MAX and MIN FP values */
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enum {
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R5900_FPMAX = LSMASK32 (30, 0),
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R5900_FPMIN = LSMASK32 (31, 0),
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};
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typedef struct _r4000_tlb_entry {
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unsigned32 mask;
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unsigned32 hi;
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unsigned32 lo0;
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unsigned32 lo1;
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} r4000_tlb_entry_t;
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#define TLB_MASK_MASK_MASK 0x01ffe000
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#define TLB_HI_VPN2_MASK 0xffffe000
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#define TLB_HI_G_MASK 0x00001000
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#define TLB_HI_ASID_MASK 0x000000ff
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#define TLB_LO_S_MASK 0x80000000
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#define TLB_LO_PFN_MASK 0x03ffffc0
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#define TLB_LO_C_MASK 0x00000038
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#define TLB_LO_D_MASK 0x00000004
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#define TLB_LO_V_MASK 0x00000002
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#define TLB_SIZE 48
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typedef struct _sim_r5900_cpu {
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/* The R5900 has 32 x 128bit general purpose registers.
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Fortunatly, the high 64 bits are only touched by multimedia (MMI)
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instructions. The normal mips instructions just use the lower 64
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bits. To avoid changing the older parts of the simulator to
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handle this weirdness, the high 64 bits of each register are kept
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in a separate array (registers1). The high 64 bits of any
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register are by convention refered by adding a '1' to the end of
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the normal register's name. So LO still refers to the low 64
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bits of the LO register, LO1 refers to the high 64 bits of that
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same register. */
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signed_word gpr1[32];
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#define GPR1 ((CPU)->r5900.gpr1)
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#define GPR1_SET(N,VAL) (GPR1[(N]) = (VAL))
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signed_word lo1;
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signed_word hi1;
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#define LO1 ((CPU)->r5900.lo1)
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#define HI1 ((CPU)->r5900.hi1)
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/* The R5900 defines a shift amount register, that controls the
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amount of certain shift instructions */
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unsigned_word sa; /* the shift amount register */
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#define REGISTER_SA (124) /* GET RID IF THIS! */
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#define SA ((CPU)->r5900.sa)
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/* The R5900, in addition to the (almost) standard floating point
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registers, defines a 32 bit accumulator. This is used in
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multiply/accumulate style instructions */
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fp_word acc; /* floating-point accumulator */
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#define ACC ((CPU)->r5900.acc)
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/* See comments below about needing to count cycles between updating
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and setting HI/LO registers */
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hilo_history hi1_history;
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#define HI1HISTORY (&(CPU)->r5900.hi1_history)
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hilo_history lo1_history;
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#define LO1HISTORY (&(CPU)->r5900.lo1_history)
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r4000_tlb_entry_t tlb[TLB_SIZE];
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#define TLB ((CPU)->r5900.tlb)
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} sim_r5900_cpu;
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#define BYTES_IN_MMI_REGS (sizeof(signed_word) + sizeof(signed_word))
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#define HALFWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/2)
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#define WORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/4)
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#define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
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#define BYTES_IN_MIPS_REGS (sizeof(signed_word))
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#define HALFWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/2)
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#define WORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/4)
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#define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
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/* SUB_REG_FETCH - return as lvalue some sub-part of a "register"
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T - type of the sub part
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TC - # of T's in the mips part of the "register"
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I - index (from 0) of desired sub part
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A - low part of "register"
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A1 - high part of register
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*/
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#define SUB_REG_FETCH(T,TC,A,A1,I) \
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(*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
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+ (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
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? ((TC) - 1 - (I) % (TC)) \
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: ((I) % (TC)) \
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) \
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) \
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)
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/*
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GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
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where <type> has two letters:
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1 is S=signed or U=unsigned
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2 is B=byte H=halfword W=word D=doubleword
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*/
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#define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8, BYTES_IN_MIPS_REGS, A, A1, I)
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#define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS, A, A1, I)
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#define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS, A, A1, I)
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#define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
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#define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8, BYTES_IN_MIPS_REGS, A, A1, I)
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#define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS, A, A1, I)
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#define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS, A, A1, I)
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#define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
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#define GPR_SB(R,I) SUB_REG_SB(&GPR[R], &GPR1[R], I)
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#define GPR_SH(R,I) SUB_REG_SH(&GPR[R], &GPR1[R], I)
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#define GPR_SW(R,I) SUB_REG_SW(&GPR[R], &GPR1[R], I)
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#define GPR_SD(R,I) SUB_REG_SD(&GPR[R], &GPR1[R], I)
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#define GPR_UB(R,I) SUB_REG_UB(&GPR[R], &GPR1[R], I)
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#define GPR_UH(R,I) SUB_REG_UH(&GPR[R], &GPR1[R], I)
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#define GPR_UW(R,I) SUB_REG_UW(&GPR[R], &GPR1[R], I)
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#define GPR_UD(R,I) SUB_REG_UD(&GPR[R], &GPR1[R], I)
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#define TMP_DCL unsigned64 tmp_reg, tmp_reg1
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#define TMP_SB(I) SUB_REG_SB(&tmp_reg, &tmp_reg1, I)
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#define TMP_SH(I) SUB_REG_SH(&tmp_reg, &tmp_reg1, I)
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#define TMP_SW(I) SUB_REG_SW(&tmp_reg, &tmp_reg1, I)
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#define TMP_SD(I) SUB_REG_SD(&tmp_reg, &tmp_reg1, I)
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#define TMP_UB(I) SUB_REG_UB(&tmp_reg, &tmp_reg1, I)
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#define TMP_UH(I) SUB_REG_UH(&tmp_reg, &tmp_reg1, I)
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#define TMP_UW(I) SUB_REG_UW(&tmp_reg, &tmp_reg1, I)
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#define TMP_UD(I) SUB_REG_UD(&tmp_reg, &tmp_reg1, I)
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#define TMP_WRT(R) do { GPR[R] = tmp_reg; GPR1[R] = tmp_reg1; } while(0)
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#define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
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#define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
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#define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
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#define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
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#define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
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#define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
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#define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
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#define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
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#define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
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#define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
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#define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
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#define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
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#define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
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#define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
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#define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
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#define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
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#define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
|
|
#define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
|
|
#define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
|
|
#define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
|
|
|
|
#define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
|
|
#define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
|
|
#define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
|
|
#define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
|
|
|
|
#define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
|
|
#define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
|
|
#define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
|
|
#define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
|
|
|
|
#define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
|
|
#define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
|
|
#define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
|
|
#define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
|
|
|
|
/* end-sanitize-r5900 */
|
|
|
|
|
|
|
|
/* The following is probably not used for MIPS IV onwards: */
|
|
/* Slots for delayed register updates. For the moment we just have a
|
|
fixed number of slots (rather than a more generic, dynamic
|
|
system). This keeps the simulator fast. However, we only allow
|
|
for the register update to be delayed for a single instruction
|
|
cycle. */
|
|
#define PSLOTS (8) /* Maximum number of instruction cycles */
|
|
|
|
typedef struct _pending_write_queue {
|
|
int in;
|
|
int out;
|
|
int total;
|
|
int slot_delay[PSLOTS];
|
|
int slot_size[PSLOTS];
|
|
int slot_bit[PSLOTS];
|
|
void *slot_dest[PSLOTS];
|
|
unsigned64 slot_value[PSLOTS];
|
|
} pending_write_queue;
|
|
|
|
#ifndef PENDING_TRACE
|
|
#define PENDING_TRACE 0
|
|
#endif
|
|
#define PENDING_IN ((CPU)->pending.in)
|
|
#define PENDING_OUT ((CPU)->pending.out)
|
|
#define PENDING_TOTAL ((CPU)->pending.total)
|
|
#define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
|
|
#define PENDING_SLOT_BIT ((CPU)->pending.slot_bit)
|
|
#define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
|
|
#define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
|
|
#define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
|
|
|
|
/* Invalidate the pending write queue, all pending writes are
|
|
discarded. */
|
|
|
|
#define PENDING_INVALIDATE() \
|
|
memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
|
|
|
|
/* Schedule a write to DEST for N cycles time. For 64 bit
|
|
destinations, schedule two writes. For floating point registers,
|
|
the caller should schedule a write to both the dest register and
|
|
the FPR_STATE register. When BIT is non-negative, only BIT of DEST
|
|
is updated. */
|
|
|
|
#define PENDING_SCHED(DEST,VAL,DELAY,BIT) \
|
|
do { \
|
|
if (PENDING_SLOT_DEST[PENDING_IN] != NULL) \
|
|
sim_engine_abort (SD, CPU, cia, \
|
|
"PENDING_SCHED - buffer overflow\n"); \
|
|
if (PENDING_TRACE) \
|
|
sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n", \
|
|
(unsigned long) cia, (unsigned long) &(DEST), \
|
|
(unsigned long) (VAL), (BIT), (int) sizeof (DEST),\
|
|
PENDING_IN, PENDING_OUT, PENDING_TOTAL); \
|
|
PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1; \
|
|
PENDING_SLOT_DEST[PENDING_IN] = &(DEST); \
|
|
PENDING_SLOT_VALUE[PENDING_IN] = (VAL); \
|
|
PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST); \
|
|
PENDING_SLOT_BIT[PENDING_IN] = (BIT); \
|
|
PENDING_IN = (PENDING_IN + 1) % PSLOTS; \
|
|
PENDING_TOTAL += 1; \
|
|
} while (0)
|
|
|
|
#define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
|
|
#define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
|
|
|
|
#define PENDING_TICK() pending_tick (SD, CPU, cia)
|
|
|
|
#define PENDING_FLUSH() abort () /* think about this one */
|
|
#define PENDING_FP() abort () /* think about this one */
|
|
|
|
/* For backward compatibility */
|
|
#define PENDING_FILL(R,VAL) \
|
|
do { \
|
|
if ((R) >= FGRIDX && (R) < FGRIDX + NR_FGR) \
|
|
{ \
|
|
PENDING_SCHED(FGR[(R) - FGRIDX], VAL, 1, -1); \
|
|
PENDING_SCHED(FPR_STATE[(R) - FGRIDX], fmt_uninterpreted, 1, -1); \
|
|
} \
|
|
else \
|
|
PENDING_SCHED(GPR[(R)], VAL, 1, -1); \
|
|
} while (0)
|
|
|
|
|
|
|
|
struct _sim_cpu {
|
|
|
|
|
|
/* The following are internal simulator state variables: */
|
|
#define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
|
|
#define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
|
|
address_word dspc; /* delay-slot PC */
|
|
#define DSPC ((CPU)->dspc)
|
|
|
|
#define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
|
|
#define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
|
|
|
|
|
|
/* State of the simulator */
|
|
unsigned int state;
|
|
unsigned int dsstate;
|
|
#define STATE ((CPU)->state)
|
|
#define DSSTATE ((CPU)->dsstate)
|
|
|
|
/* Flags in the "state" variable: */
|
|
#define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
|
|
#define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
|
|
#define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */
|
|
#define simPCOC0 (1 << 17) /* COC[1] from current */
|
|
#define simPCOC1 (1 << 18) /* COC[1] from previous */
|
|
#define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
|
|
#define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
|
|
#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
|
|
#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
|
|
|
|
#define ENGINE_ISSUE_PREFIX_HOOK() \
|
|
{ \
|
|
/* Perform any pending writes */ \
|
|
PENDING_TICK(); \
|
|
/* Set previous flag, depending on current: */ \
|
|
if (STATE & simPCOC0) \
|
|
STATE |= simPCOC1; \
|
|
else \
|
|
STATE &= ~simPCOC1; \
|
|
/* and update the current value: */ \
|
|
if (GETFCC(0)) \
|
|
STATE |= simPCOC0; \
|
|
else \
|
|
STATE &= ~simPCOC0; \
|
|
}
|
|
|
|
|
|
/* This is nasty, since we have to rely on matching the register
|
|
numbers used by GDB. Unfortunately, depending on the MIPS target
|
|
GDB uses different register numbers. We cannot just include the
|
|
relevant "gdb/tm.h" link, since GDB may not be configured before
|
|
the sim world, and also the GDB header file requires too much other
|
|
state. */
|
|
|
|
#ifndef TM_MIPS_H
|
|
#define LAST_EMBED_REGNUM (89)
|
|
#define NUM_REGS (LAST_EMBED_REGNUM + 1)
|
|
|
|
/* start-sanitize-r5900 */
|
|
#define FIRST_COP0_REG 128
|
|
#define NUM_COP0_REGS 22
|
|
#undef NUM_REGS
|
|
#define NUM_REGS (150)
|
|
/* end-sanitize-r5900 */
|
|
|
|
#endif
|
|
|
|
/* start-sanitize-sky */
|
|
#ifdef TARGET_SKY
|
|
#ifndef TM_TXVU_H
|
|
/* Number of machine registers */
|
|
#define NUM_VU_REGS 160
|
|
|
|
#define NUM_VU_INTEGER_REGS 16
|
|
#define FIRST_VEC_REG 32
|
|
|
|
#define NUM_VIF_REGS 26
|
|
|
|
#define NUM_CORE_REGS 150
|
|
|
|
#undef NUM_REGS
|
|
#define NUM_REGS (NUM_CORE_REGS + 2*(NUM_VU_REGS) + 2*(NUM_VIF_REGS))
|
|
#endif /* no tm-txvu.h */
|
|
#endif /* TARGET_SKY */
|
|
/* end-sanitize-sky */
|
|
|
|
enum float_operation
|
|
/* start-sanitize-sky */
|
|
/* NOTE: THE VALUES of THESE CONSTANTS MUST BE IN SYNC WITH THOSE IN WF.H */
|
|
/* end-sanitize-sky */
|
|
{
|
|
FLOP_ADD, FLOP_SUB, FLOP_MUL, FLOP_MADD,
|
|
FLOP_MSUB, FLOP_MAX=10, FLOP_MIN, FLOP_ABS,
|
|
FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
|
|
};
|
|
|
|
/* To keep this default simulator simple, and fast, we use a direct
|
|
vector of registers. The internal simulator engine then uses
|
|
manifests to access the correct slot. */
|
|
|
|
unsigned_word registers[LAST_EMBED_REGNUM + 1];
|
|
int register_widths[NUM_REGS];
|
|
#define REGISTERS ((CPU)->registers)
|
|
|
|
#define GPR (®ISTERS[0])
|
|
#define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
|
|
|
|
/* While space is allocated for the floating point registers in the
|
|
main registers array, they are stored separatly. This is because
|
|
their size may not necessarily match the size of either the
|
|
general-purpose or system specific registers */
|
|
#define NR_FGR (32)
|
|
#define FGRIDX (38)
|
|
fp_word fgr[NR_FGR];
|
|
#define FGR ((CPU)->fgr)
|
|
|
|
#define LO (REGISTERS[33])
|
|
#define HI (REGISTERS[34])
|
|
#define PCIDX 37
|
|
#define PC (REGISTERS[PCIDX])
|
|
#define CAUSE (REGISTERS[36])
|
|
#define SRIDX (32)
|
|
#define SR (REGISTERS[SRIDX]) /* CPU status register */
|
|
#define FCR0IDX (71)
|
|
#define FCR0 (REGISTERS[FCR0IDX]) /* really a 32bit register */
|
|
#define FCR31IDX (70)
|
|
#define FCR31 (REGISTERS[FCR31IDX]) /* really a 32bit register */
|
|
#define FCSR (FCR31)
|
|
#define Debug (REGISTERS[86])
|
|
#define DEPC (REGISTERS[87])
|
|
#define EPC (REGISTERS[88])
|
|
#define COCIDX (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
|
|
|
|
unsigned_word c0_config_reg;
|
|
#define C0_CONFIG ((CPU)->c0_config_reg)
|
|
|
|
/* The following are pseudonyms for standard registers */
|
|
#define ZERO (REGISTERS[0])
|
|
#define V0 (REGISTERS[2])
|
|
#define A0 (REGISTERS[4])
|
|
#define A1 (REGISTERS[5])
|
|
#define A2 (REGISTERS[6])
|
|
#define A3 (REGISTERS[7])
|
|
#define T8IDX 24
|
|
#define T8 (REGISTERS[T8IDX])
|
|
#define SPIDX 29
|
|
#define SP (REGISTERS[SPIDX])
|
|
#define RAIDX 31
|
|
#define RA (REGISTERS[RAIDX])
|
|
|
|
/* While space is allocated in the main registers arrray for some of
|
|
the COP0 registers, that space isn't sufficient. Unknown COP0
|
|
registers overflow into the array below */
|
|
|
|
#define NR_COP0_GPR 32
|
|
unsigned_word cop0_gpr[NR_COP0_GPR];
|
|
#define COP0_GPR ((CPU)->cop0_gpr)
|
|
/* start-sanitize-r5900 */
|
|
#define NR_COP0_BP 8
|
|
unsigned_word cop0_bp[NR_COP0_BP];
|
|
#define COP0_BP ((CPU)->cop0_bp)
|
|
#define NR_COP0_P 64
|
|
unsigned_word cop0_p[NR_COP0_P];
|
|
|
|
#define COP0_P ((CPU)->cop0_p)
|
|
#define COP0_INDEX ((unsigned32)(COP0_GPR[0]))
|
|
#define COP0_RANDOM ((unsigned32)(COP0_GPR[1]))
|
|
#define COP0_ENTRYLO0 ((unsigned32)(COP0_GPR[2]))
|
|
#define COP0_ENTRYLO1 ((unsigned32)(COP0_GPR[3]))
|
|
#define COP0_CONTEXT ((unsigned32)(COP0_GPR[4]))
|
|
#define COP0_PAGEMASK ((unsigned32)(COP0_GPR[5]))
|
|
#define COP0_WIRED ((unsigned32)(COP0_GPR[6]))
|
|
#define COP0_BADVADDR ((unsigned32)(COP0_GPR[8]))
|
|
#define COP0_COUNT ((unsigned32)(COP0_GPR[9]))
|
|
#define COP0_ENTRYHI ((unsigned32)(COP0_GPR[10]))
|
|
#define COP0_COMPARE ((unsigned32)(COP0_GPR[11]))
|
|
#define COP0_EPC ((unsigned32)(EPC)) /* 14 */
|
|
#define COP0_PRID ((unsigned32)(COP0_GPR[15]))
|
|
#define COP0_CONFIG ((unsigned32)(C0_CONFIG)) /* 16 */
|
|
#define COP0_TAGLO ((unsigned32)(COP0_GPR[28]))
|
|
#define COP0_TAGHI ((unsigned32)(COP0_GPR[29]))
|
|
#define COP0_ERROREPC ((unsigned32)(COP0_GPR[30]))
|
|
|
|
#define COP0_CONTEXT_BADVPN2_MASK 0x007ffff0
|
|
|
|
#define COP0_CONTEXT_set_BADVPN2(x) \
|
|
(COP0_CONTEXT = ((COP0_CONTEXT & 0xff100000) | ((x << 4) & 0x007ffff0)))
|
|
/* end-sanitize-r5900 */
|
|
|
|
/* Keep the current format state for each register: */
|
|
FP_formats fpr_state[32];
|
|
#define FPR_STATE ((CPU)->fpr_state)
|
|
|
|
pending_write_queue pending;
|
|
|
|
/* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
|
|
read-write instructions. It is set when a linked load occurs. It
|
|
is tested and cleared by the conditional store. It is cleared
|
|
(during other CPU operations) when a store to the location would
|
|
no longer be atomic. In particular, it is cleared by exception
|
|
return instructions. */
|
|
int llbit;
|
|
#define LLBIT ((CPU)->llbit)
|
|
|
|
|
|
/* The HIHISTORY and LOHISTORY timestamps are used to ensure that
|
|
corruptions caused by using the HI or LO register too close to a
|
|
following operation is spotted. See mips.igen for more details. */
|
|
|
|
hilo_history hi_history;
|
|
#define HIHISTORY (&(CPU)->hi_history)
|
|
hilo_history lo_history;
|
|
#define LOHISTORY (&(CPU)->lo_history)
|
|
|
|
/* start-sanitize-branchbug4011 */
|
|
#if 1
|
|
int branchbug4011_option;
|
|
#define BRANCHBUG4011_OPTION ((CPU)->branchbug4011_option)
|
|
address_word branchbug4011_last_target;
|
|
#define BRANCHBUG4011_LAST_TARGET ((CPU)->branchbug4011_last_target)
|
|
address_word branchbug4011_last_cia;
|
|
#define BRANCHBUG4011_LAST_CIA ((CPU)->branchbug4011_last_cia)
|
|
|
|
#define check_branch_bug() (check_4011_branch_bug (_SD))
|
|
#define mark_branch_bug(TARGET) (mark_4011_branch_bug (_SD,TARGET))
|
|
#else
|
|
/* end-sanitize-branchbug4011 */
|
|
#define check_branch_bug()
|
|
#define mark_branch_bug(TARGET)
|
|
/* start-sanitize-branchbug4011 */
|
|
#endif
|
|
/* end-sanitize-branchbug4011 */
|
|
/* start-sanitize-r5900 */
|
|
sim_r5900_cpu r5900;
|
|
/* end-sanitize-r5900 */
|
|
|
|
/* start-sanitize-cygnus */
|
|
/* The MDMX ISA has a very very large accumulator */
|
|
unsigned8 acc[3 * 8];
|
|
/* end-sanitize-cygnus */
|
|
|
|
/* start-sanitize-sky */
|
|
#ifdef TARGET_SKY
|
|
/* Device on which instruction issue last occured. */
|
|
char cur_device;
|
|
#endif
|
|
/* end-sanitize-sky */
|
|
|
|
sim_cpu_base base;
|
|
};
|
|
|
|
|
|
/* MIPS specific simulator watch config */
|
|
|
|
void watch_options_install PARAMS ((SIM_DESC sd));
|
|
|
|
struct swatch {
|
|
sim_event *pc;
|
|
sim_event *clock;
|
|
sim_event *cycles;
|
|
};
|
|
|
|
|
|
/* FIXME: At present much of the simulator is still static */
|
|
struct sim_state {
|
|
|
|
struct swatch watch;
|
|
|
|
sim_cpu cpu[MAX_NR_PROCESSORS];
|
|
#if (WITH_SMP)
|
|
#define STATE_CPU(sd,n) (&(sd)->cpu[n])
|
|
#else
|
|
#define STATE_CPU(sd,n) (&(sd)->cpu[0])
|
|
#endif
|
|
|
|
/* start-sanitize-sky */
|
|
#ifdef TARGET_SKY
|
|
|
|
#ifdef SKY_FUNIT
|
|
/* Record of option for floating point implementation type. */
|
|
int fp_type_opt;
|
|
#define STATE_FP_TYPE_OPT(sd) ((sd)->fp_type_opt)
|
|
#define STATE_FP_TYPE_OPT_ACCURATE 0x80000000
|
|
#endif
|
|
|
|
/* Index of next unused name slot for multi-phase load list. */
|
|
int next_mload_count;
|
|
#define STATE_MLOAD_COUNT(sd) ((sd)->next_mload_count)
|
|
|
|
#define MAX_MLOAD_COUNT 2 /* limit for next_load_count and load_index */
|
|
|
|
/* Program names for multi-phase load. */
|
|
char *next_mload_name[MAX_MLOAD_COUNT];
|
|
#define STATE_MLOAD_NAME(sd) ((sd)->next_mload_name)
|
|
|
|
/* Index of next program for multi-phase load. */
|
|
int mload_index;
|
|
#define STATE_MLOAD_INDEX(sd) ((sd)->mload_index)
|
|
|
|
#endif
|
|
/* end-sanitize-sky */
|
|
|
|
sim_state_base base;
|
|
};
|
|
|
|
|
|
|
|
/* Status information: */
|
|
|
|
/* TODO : these should be the bitmasks for these bits within the
|
|
status register. At the moment the following are VR4300
|
|
bit-positions: */
|
|
#define status_KSU_mask (0x18) /* mask for KSU bits */
|
|
#define status_KSU_shift (3) /* shift for field */
|
|
#define ksu_kernel (0x0)
|
|
#define ksu_supervisor (0x1)
|
|
#define ksu_user (0x2)
|
|
#define ksu_unknown (0x3)
|
|
|
|
#define SR_KSU ((SR & status_KSU_mask) >> status_KSU_shift)
|
|
|
|
#define status_IE (1 << 0) /* Interrupt enable */
|
|
#define status_EIE (1 << 16) /* Enable Interrupt Enable */
|
|
#define status_EXL (1 << 1) /* Exception level */
|
|
#define status_RE (1 << 25) /* Reverse Endian in user mode */
|
|
#define status_FR (1 << 26) /* enables MIPS III additional FP registers */
|
|
#define status_SR (1 << 20) /* soft reset or NMI */
|
|
#define status_BEV (1 << 22) /* Location of general exception vectors */
|
|
#define status_TS (1 << 21) /* TLB shutdown has occurred */
|
|
#define status_ERL (1 << 2) /* Error level */
|
|
#define status_IM7 (1 << 15) /* Timer Interrupt Mask */
|
|
#define status_RP (1 << 27) /* Reduced Power mode */
|
|
/* start-sanitize-r5900 */
|
|
#define status_CU0 (1 << 28) /* COP0 usable */
|
|
#define status_CU1 (1 << 29) /* COP1 usable */
|
|
#define status_CU2 (1 << 30) /* COP2 usable */
|
|
/* end-sanitize-r5900 */
|
|
|
|
/* Specializations for TX39 family */
|
|
#define status_IEc (1 << 0) /* Interrupt enable (current) */
|
|
#define status_KUc (1 << 1) /* Kernel/User mode */
|
|
#define status_IEp (1 << 2) /* Interrupt enable (previous) */
|
|
#define status_KUp (1 << 3) /* Kernel/User mode */
|
|
#define status_IEo (1 << 4) /* Interrupt enable (old) */
|
|
#define status_KUo (1 << 5) /* Kernel/User mode */
|
|
#define status_IM_mask (0xff) /* Interrupt mask */
|
|
#define status_IM_shift (8)
|
|
#define status_NMI (1 << 20) /* NMI */
|
|
#define status_NMI (1 << 20) /* NMI */
|
|
|
|
#define cause_BD ((unsigned)1 << 31) /* L1 Exception in branch delay slot */
|
|
#define cause_BD2 (1 << 30) /* L2 Exception in branch delay slot */
|
|
#define cause_CE_mask 0x30000000 /* Coprocessor exception */
|
|
#define cause_CE_shift 28
|
|
#define cause_EXC2_mask 0x00070000
|
|
#define cause_EXC2_shift 16
|
|
#define cause_IP7 (1 << 15) /* Interrupt pending */
|
|
#define cause_SIOP (1 << 12) /* SIO pending */
|
|
#define cause_IP3 (1 << 11) /* Int 0 pending */
|
|
#define cause_IP2 (1 << 10) /* Int 1 pending */
|
|
|
|
/* start-sanitize-sky */
|
|
#ifdef TARGET_SKY
|
|
#define cause_EXC_mask (0x7c) /* Exception code */
|
|
#else
|
|
/* end-sanitize-sky */
|
|
#define cause_EXC_mask (0x1c) /* Exception code */
|
|
/* start-sanitize-sky */
|
|
#endif
|
|
/* end-sanitize-sky */
|
|
#define cause_EXC_shift (2)
|
|
|
|
#define cause_SW0 (1 << 8) /* Software interrupt 0 */
|
|
#define cause_SW1 (1 << 9) /* Software interrupt 1 */
|
|
#define cause_IP_mask (0x3f) /* Interrupt pending field */
|
|
#define cause_IP_shift (10)
|
|
|
|
#define cause_set_EXC(x) CAUSE = (CAUSE & ~cause_EXC_mask) | ((x << cause_EXC_shift) & cause_EXC_mask)
|
|
#define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask)
|
|
|
|
|
|
/* NOTE: We keep the following status flags as bit values (1 for true,
|
|
0 for false). This allows them to be used in binary boolean
|
|
operations without worrying about what exactly the non-zero true
|
|
value is. */
|
|
|
|
/* UserMode */
|
|
#ifdef SUBTARGET_R3900
|
|
#define UserMode ((SR & status_KUc) ? 1 : 0)
|
|
#else
|
|
#define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
|
|
#endif /* SUBTARGET_R3900 */
|
|
|
|
/* BigEndianMem */
|
|
/* Hardware configuration. Affects endianness of LoadMemory and
|
|
StoreMemory and the endianness of Kernel and Supervisor mode
|
|
execution. The value is 0 for little-endian; 1 for big-endian. */
|
|
#define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
|
|
/*(state & simBE) ? 1 : 0)*/
|
|
|
|
/* ReverseEndian */
|
|
/* This mode is selected if in User mode with the RE bit being set in
|
|
SR (Status Register). It reverses the endianness of load and store
|
|
instructions. */
|
|
#define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0)
|
|
|
|
/* BigEndianCPU */
|
|
/* The endianness for load and store instructions (0=little;1=big). In
|
|
User mode this endianness may be switched by setting the state_RE
|
|
bit in the SR register. Thus, BigEndianCPU may be computed as
|
|
(BigEndianMem EOR ReverseEndian). */
|
|
#define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */
|
|
|
|
|
|
|
|
/* Exceptions: */
|
|
|
|
/* NOTE: These numbers depend on the processor architecture being
|
|
simulated: */
|
|
enum ExceptionCause {
|
|
Interrupt = 0,
|
|
TLBModification = 1,
|
|
TLBLoad = 2,
|
|
TLBStore = 3,
|
|
AddressLoad = 4,
|
|
AddressStore = 5,
|
|
InstructionFetch = 6,
|
|
DataReference = 7,
|
|
SystemCall = 8,
|
|
BreakPoint = 9,
|
|
ReservedInstruction = 10,
|
|
CoProcessorUnusable = 11,
|
|
IntegerOverflow = 12, /* Arithmetic overflow (IDT monitor raises SIGFPE) */
|
|
Trap = 13,
|
|
FPE = 15,
|
|
DebugBreakPoint = 16,
|
|
Watch = 23,
|
|
NMIReset = 31,
|
|
|
|
|
|
/* The following exception code is actually private to the simulator
|
|
world. It is *NOT* a processor feature, and is used to signal
|
|
run-time errors in the simulator. */
|
|
SimulatorFault = 0xFFFFFFFF
|
|
};
|
|
|
|
#define TLB_REFILL (0)
|
|
#define TLB_INVALID (1)
|
|
|
|
/* start-sanitize-r5900 */
|
|
/* For the 5900, we have level 1 and level 2 exceptions. The level 2 exceptions
|
|
are ColdReset, NMI, Counter, and Debug/SIO. Of these, we support only
|
|
the NMIReset exception. */
|
|
|
|
#define is5900Level2Exception(x) (x == NMIReset)
|
|
/* end-sanitize-r5900 */
|
|
|
|
/* The following break instructions are reserved for use by the
|
|
simulator. The first is used to halt the simulation. The second
|
|
is used by gdb for break-points. NOTE: Care must be taken, since
|
|
this value may be used in later revisions of the MIPS ISA. */
|
|
#define HALT_INSTRUCTION_MASK (0x03FFFFC0)
|
|
|
|
#define HALT_INSTRUCTION (0x03ff000d)
|
|
#define HALT_INSTRUCTION2 (0x0000ffcd)
|
|
|
|
/* start-sanitize-sky */
|
|
#define HALT_INSTRUCTION_PASS (0x03fffc0d) /* break 0xffff0 */
|
|
#define HALT_INSTRUCTION_FAIL (0x03ffffcd) /* break 0xfffff */
|
|
/* end-sanitize-sky */
|
|
|
|
#define BREAKPOINT_INSTRUCTION (0x0005000d)
|
|
#define BREAKPOINT_INSTRUCTION2 (0x0000014d)
|
|
|
|
/* start-sanitize-sky */
|
|
#define LOAD_INSTRUCTION (0x03fffc4d) /* break 0xffff1 */
|
|
#define PRINTF_INSTRUCTION (0x03fffc8d) /* break 0xffff2 */
|
|
/* end-sanitize-sky */
|
|
|
|
|
|
void interrupt_event (SIM_DESC sd, void *data);
|
|
|
|
void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
|
|
#define SignalException(exc,instruction) signal_exception (SD, CPU, cia, (exc), (instruction))
|
|
#define SignalExceptionInterrupt(level) signal_exception (SD, CPU, cia, Interrupt, level)
|
|
#define SignalExceptionInstructionFetch() signal_exception (SD, CPU, cia, InstructionFetch)
|
|
#define SignalExceptionAddressStore() signal_exception (SD, CPU, cia, AddressStore)
|
|
#define SignalExceptionAddressLoad() signal_exception (SD, CPU, cia, AddressLoad)
|
|
#define SignalExceptionSimulatorFault(buf) signal_exception (SD, CPU, cia, SimulatorFault, buf)
|
|
#define SignalExceptionFPE() signal_exception (SD, CPU, cia, FPE)
|
|
#define SignalExceptionIntegerOverflow() signal_exception (SD, CPU, cia, IntegerOverflow)
|
|
#define SignalExceptionCoProcessorUnusable() signal_exception (SD, CPU, cia, CoProcessorUnusable)
|
|
#define SignalExceptionNMIReset() signal_exception (SD, CPU, cia, NMIReset)
|
|
#define SignalExceptionTLBRefillStore() signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL)
|
|
#define SignalExceptionTLBRefillLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL)
|
|
#define SignalExceptionTLBInvalidStore() signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID)
|
|
#define SignalExceptionTLBInvalidLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID)
|
|
#define SignalExceptionTLBModification() signal_exception (SD, CPU, cia, TLBModification)
|
|
|
|
/* Co-processor accesses */
|
|
|
|
void cop_lw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
|
|
void cop_ld PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
|
|
unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
|
|
uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
|
|
|
|
#define COP_LW(coproc_num,coproc_reg,memword) \
|
|
cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
|
|
#define COP_LD(coproc_num,coproc_reg,memword) \
|
|
cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
|
|
#define COP_SW(coproc_num,coproc_reg) \
|
|
cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
|
|
#define COP_SD(coproc_num,coproc_reg) \
|
|
cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
|
|
|
|
/* start-sanitize-sky */
|
|
#ifdef TARGET_SKY
|
|
void cop_lq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia,
|
|
int coproc_num, int coproc_reg, unsigned128 memword));
|
|
unsigned128 cop_sq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia,
|
|
int coproc_num, int coproc_reg));
|
|
#define COP_LQ(coproc_num,coproc_reg,memword) \
|
|
cop_lq (SD, CPU, cia, coproc_num, coproc_reg, memword)
|
|
#define COP_SQ(coproc_num,coproc_reg) \
|
|
cop_sq (SD, CPU, cia, coproc_num, coproc_reg)
|
|
#endif /* TARGET_SKY */
|
|
/* end-sanitize-sky */
|
|
|
|
void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction));
|
|
#define DecodeCoproc(instruction) \
|
|
decode_coproc (SD, CPU, cia, (instruction))
|
|
|
|
void sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
|
|
|
|
|
|
|
|
/* Memory accesses */
|
|
|
|
/* The following are generic to all versions of the MIPS architecture
|
|
to date: */
|
|
|
|
/* Memory Access Types (for CCA): */
|
|
#define Uncached (0)
|
|
#define CachedNoncoherent (1)
|
|
#define CachedCoherent (2)
|
|
#define Cached (3)
|
|
|
|
#define isINSTRUCTION (1 == 0) /* FALSE */
|
|
#define isDATA (1 == 1) /* TRUE */
|
|
#define isLOAD (1 == 0) /* FALSE */
|
|
#define isSTORE (1 == 1) /* TRUE */
|
|
#define isREAL (1 == 0) /* FALSE */
|
|
#define isRAW (1 == 1) /* TRUE */
|
|
/* The parameter HOST (isTARGET / isHOST) is ignored */
|
|
#define isTARGET (1 == 0) /* FALSE */
|
|
/* #define isHOST (1 == 1) TRUE */
|
|
|
|
/* The "AccessLength" specifications for Loads and Stores. NOTE: This
|
|
is the number of bytes minus 1. */
|
|
#define AccessLength_BYTE (0)
|
|
#define AccessLength_HALFWORD (1)
|
|
#define AccessLength_TRIPLEBYTE (2)
|
|
#define AccessLength_WORD (3)
|
|
#define AccessLength_QUINTIBYTE (4)
|
|
#define AccessLength_SEXTIBYTE (5)
|
|
#define AccessLength_SEPTIBYTE (6)
|
|
#define AccessLength_DOUBLEWORD (7)
|
|
#define AccessLength_QUADWORD (15)
|
|
|
|
#define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
|
|
? AccessLength_DOUBLEWORD /*7*/ \
|
|
: AccessLength_WORD /*3*/)
|
|
#define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
|
|
|
|
|
|
INLINE_SIM_MAIN (int) address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
|
|
#define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
|
|
address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
|
|
|
|
INLINE_SIM_MAIN (void) load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD));
|
|
#define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
|
|
load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
|
|
|
|
INLINE_SIM_MAIN (void) store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
|
|
#define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
|
|
store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
|
|
|
|
INLINE_SIM_MAIN (void) cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
|
|
#define CacheOp(op,pAddr,vAddr,instruction) \
|
|
cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
|
|
|
|
INLINE_SIM_MAIN (void) sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype));
|
|
#define SyncOperation(stype) \
|
|
sync_operation (SD, CPU, cia, (stype))
|
|
|
|
INLINE_SIM_MAIN (void) prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
|
|
#define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
|
|
prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
|
|
|
|
INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
|
|
#define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
|
|
INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
|
|
#define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
|
|
#define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
|
|
|
|
void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
|
|
extern FILE *tracefh;
|
|
|
|
INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
|
|
|
|
char* pr_addr PARAMS ((SIM_ADDR addr));
|
|
char* pr_uword64 PARAMS ((uword64 addr));
|
|
|
|
/* start-sanitize-sky */
|
|
#ifdef TARGET_SKY
|
|
|
|
#ifdef SIM_ENGINE_HALT_HOOK
|
|
#undef SIM_ENGINE_HALT_HOOK
|
|
#endif
|
|
|
|
void sky_sim_engine_halt PARAMS ((SIM_DESC sd, sim_cpu *last, sim_cia cia));
|
|
#define SIM_ENGINE_HALT_HOOK(sd, last, cia) sky_sim_engine_halt(sd, last, cia)
|
|
|
|
#ifdef SIM_ENGINE_RESTART_HOOK
|
|
#undef SIM_ENGINE_RESTART_HOOK
|
|
#endif
|
|
|
|
void sky_sim_engine_restart PARAMS ((SIM_DESC sd, sim_cpu *last, sim_cia cia));
|
|
#define SIM_ENGINE_RESTART_HOOK(sd, L, pc) sky_sim_engine_restart(sd, L, pc)
|
|
|
|
/* for resume/suspend modules */
|
|
SIM_RC sky_sim_module_install PARAMS ((SIM_DESC sd));
|
|
|
|
#define MODULE_LIST sky_sim_module_install,
|
|
|
|
#ifndef TM_TXVU_H /* In case GDB hasn't been configured yet */
|
|
enum txvu_cpu_context
|
|
{
|
|
TXVU_CPU_AUTO = -1, /* context-sensitive context */
|
|
TXVU_CPU_MASTER = 0, /* R5900 core */
|
|
TXVU_CPU_VU0 = 1, /* Vector units */
|
|
TXVU_CPU_VU1 = 2,
|
|
TXVU_CPU_VIF0 = 3, /* Vector interface units */
|
|
TXVU_CPU_VIF1 = 4,
|
|
TXVU_CPU_LAST /* Count of context types */
|
|
};
|
|
|
|
/* memory segment for communication with GDB */
|
|
#define VIO_BASE 0xa0000000
|
|
#define GDB_COMM_AREA 0x19810000 /* Random choice */
|
|
#define GDB_COMM_SIZE 0x4000
|
|
|
|
/* Memory address containing last device to execute */
|
|
#define LAST_DEVICE GDB_COMM_AREA
|
|
|
|
/* The FIFO breakpoint count and table */
|
|
#define FIFO_BPT_CNT (GDB_COMM_AREA + 4)
|
|
#define FIFO_BPT_TBL (GDB_COMM_AREA + 8)
|
|
|
|
/* Each element of the breakpoint table is three four-byte integers. */
|
|
#define BPT_ELEM_SZ 4*3
|
|
|
|
#define TXVU_VU_BRK_MASK 0x02 /* Breakpoint bit is #57 for VU insns */
|
|
#define TXVU_VIF_BRK_MASK 0x80 /* Use interrupt bit for VIF insns */
|
|
|
|
#endif /* !TM_TXVU_H */
|
|
#endif /* TARGET_SKY */
|
|
/* end-sanitize-sky */
|
|
|
|
#if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
|
|
#include "sim-main.c"
|
|
#endif
|
|
|
|
#endif
|