7bb99c5383
2014-02-19 Tom Tromey <tromey@redhat.com> * target.h (struct target_ops) <to_insert_watchpoint>: Add argument. (target_insert_watchpoint): Add argument. * target.c (debug_to_insert_watchpoint): Add argument. (update_current_target): Update. * s390-linux-nat.c (s390_insert_watchpoint): Add 'self' argument. * remote.c (remote_insert_watchpoint): Add 'self' argument. * remote-mips.c (mips_insert_watchpoint): Add 'self' argument. * remote-m32r-sdi.c (m32r_insert_watchpoint): Add 'self' argument. * procfs.c (procfs_insert_watchpoint): Add 'self' argument. * ppc-linux-nat.c (ppc_linux_insert_watchpoint): Add 'self' argument. * nto-procfs.c (procfs_insert_hw_watchpoint): Add 'self' argument. (procfs_insert_hw_watchpoint): Add 'self' argument. * mips-linux-nat.c (mips_linux_insert_watchpoint): Add 'self' argument. * inf-ttrace.c (inf_ttrace_insert_watchpoint): Add 'self' argument. * ia64-linux-nat.c (ia64_linux_insert_watchpoint): Add 'self' argument. * i386-nat.c (i386_insert_watchpoint): Add 'self' argument. * arm-linux-nat.c (arm_linux_insert_watchpoint): Add 'self' argument. * aarch64-linux-nat.c (aarch64_linux_insert_watchpoint): Add 'self' argument.
907 lines
23 KiB
C
907 lines
23 KiB
C
/* Functions specific to running gdb native on IA-64 running
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GNU/Linux.
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Copyright (C) 1999-2014 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "defs.h"
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#include <string.h>
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#include "inferior.h"
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#include "target.h"
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#include "gdbcore.h"
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#include "regcache.h"
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#include "ia64-tdep.h"
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#include "linux-nat.h"
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#include <signal.h>
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#include <sys/ptrace.h>
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#include "gdb_wait.h"
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#ifdef HAVE_SYS_REG_H
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#include <sys/reg.h>
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#endif
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#include <sys/syscall.h>
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#include <sys/user.h>
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#include <asm/ptrace_offsets.h>
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#include <sys/procfs.h>
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/* Prototypes for supply_gregset etc. */
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#include "gregset.h"
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/* These must match the order of the register names.
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Some sort of lookup table is needed because the offsets associated
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with the registers are all over the board. */
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static int u_offsets[] =
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{
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/* general registers */
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-1, /* gr0 not available; i.e, it's always zero. */
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PT_R1,
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PT_R2,
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PT_R3,
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PT_R4,
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PT_R5,
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PT_R6,
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PT_R7,
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PT_R8,
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PT_R9,
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PT_R10,
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PT_R11,
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PT_R12,
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PT_R13,
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PT_R14,
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PT_R15,
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PT_R16,
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PT_R17,
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PT_R18,
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PT_R19,
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PT_R20,
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PT_R21,
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PT_R22,
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PT_R23,
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PT_R24,
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PT_R25,
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PT_R26,
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PT_R27,
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PT_R28,
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PT_R29,
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PT_R30,
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PT_R31,
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/* gr32 through gr127 not directly available via the ptrace interface. */
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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/* Floating point registers */
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-1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0). */
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PT_F2,
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PT_F3,
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PT_F4,
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PT_F5,
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PT_F6,
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PT_F7,
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PT_F8,
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PT_F9,
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PT_F10,
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PT_F11,
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PT_F12,
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PT_F13,
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PT_F14,
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PT_F15,
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PT_F16,
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PT_F17,
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PT_F18,
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PT_F19,
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PT_F20,
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PT_F21,
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PT_F22,
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PT_F23,
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PT_F24,
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PT_F25,
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PT_F26,
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PT_F27,
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PT_F28,
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PT_F29,
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PT_F30,
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PT_F31,
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PT_F32,
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PT_F33,
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PT_F34,
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PT_F35,
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PT_F36,
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PT_F37,
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PT_F38,
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PT_F39,
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PT_F40,
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PT_F41,
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PT_F42,
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PT_F43,
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PT_F44,
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PT_F45,
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PT_F46,
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PT_F47,
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PT_F48,
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PT_F49,
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PT_F50,
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PT_F51,
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PT_F52,
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PT_F53,
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PT_F54,
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PT_F55,
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PT_F56,
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PT_F57,
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PT_F58,
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PT_F59,
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PT_F60,
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PT_F61,
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PT_F62,
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PT_F63,
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PT_F64,
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PT_F65,
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PT_F66,
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PT_F67,
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PT_F68,
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PT_F69,
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PT_F70,
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PT_F71,
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PT_F72,
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PT_F73,
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PT_F74,
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PT_F75,
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PT_F76,
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PT_F77,
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PT_F78,
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PT_F79,
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PT_F80,
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PT_F81,
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PT_F82,
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PT_F83,
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PT_F84,
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PT_F85,
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PT_F86,
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PT_F87,
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PT_F88,
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PT_F89,
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PT_F90,
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PT_F91,
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PT_F92,
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PT_F93,
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PT_F94,
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PT_F95,
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PT_F96,
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PT_F97,
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PT_F98,
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PT_F99,
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PT_F100,
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PT_F101,
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PT_F102,
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PT_F103,
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PT_F104,
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PT_F105,
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PT_F106,
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PT_F107,
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PT_F108,
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PT_F109,
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PT_F110,
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PT_F111,
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PT_F112,
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PT_F113,
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PT_F114,
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PT_F115,
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PT_F116,
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PT_F117,
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PT_F118,
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PT_F119,
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PT_F120,
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PT_F121,
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PT_F122,
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PT_F123,
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PT_F124,
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PT_F125,
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PT_F126,
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PT_F127,
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/* Predicate registers - we don't fetch these individually. */
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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/* branch registers */
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PT_B0,
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PT_B1,
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PT_B2,
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PT_B3,
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PT_B4,
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PT_B5,
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PT_B6,
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PT_B7,
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/* Virtual frame pointer and virtual return address pointer. */
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-1, -1,
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/* other registers */
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PT_PR,
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PT_CR_IIP, /* ip */
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PT_CR_IPSR, /* psr */
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PT_CFM, /* cfm */
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/* kernel registers not visible via ptrace interface (?) */
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-1, -1, -1, -1, -1, -1, -1, -1,
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/* hole */
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-1, -1, -1, -1, -1, -1, -1, -1,
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PT_AR_RSC,
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PT_AR_BSP,
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PT_AR_BSPSTORE,
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PT_AR_RNAT,
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-1,
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-1, /* Not available: FCR, IA32 floating control register. */
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-1, -1,
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-1, /* Not available: EFLAG */
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-1, /* Not available: CSD */
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-1, /* Not available: SSD */
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-1, /* Not available: CFLG */
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-1, /* Not available: FSR */
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-1, /* Not available: FIR */
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-1, /* Not available: FDR */
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-1,
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PT_AR_CCV,
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-1, -1, -1,
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PT_AR_UNAT,
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-1, -1, -1,
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PT_AR_FPSR,
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-1, -1, -1,
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-1, /* Not available: ITC */
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1,
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PT_AR_PFS,
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PT_AR_LC,
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PT_AR_EC,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1,
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/* nat bits - not fetched directly; instead we obtain these bits from
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either rnat or unat or from memory. */
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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};
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static CORE_ADDR
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ia64_register_addr (struct gdbarch *gdbarch, int regno)
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{
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CORE_ADDR addr;
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if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
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error (_("Invalid register number %d."), regno);
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if (u_offsets[regno] == -1)
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addr = 0;
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else
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addr = (CORE_ADDR) u_offsets[regno];
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return addr;
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}
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static int
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ia64_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
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{
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return regno < 0
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|| regno >= gdbarch_num_regs (gdbarch)
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|| u_offsets[regno] == -1;
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}
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static int
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ia64_cannot_store_register (struct gdbarch *gdbarch, int regno)
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{
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/* Rationale behind not permitting stores to bspstore...
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The IA-64 architecture provides bspstore and bsp which refer
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memory locations in the RSE's backing store. bspstore is the
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next location which will be written when the RSE needs to write
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to memory. bsp is the address at which r32 in the current frame
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would be found if it were written to the backing store.
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The IA-64 architecture provides read-only access to bsp and
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read/write access to bspstore (but only when the RSE is in
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the enforced lazy mode). It should be noted that stores
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to bspstore also affect the value of bsp. Changing bspstore
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does not affect the number of dirty entries between bspstore
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and bsp, so changing bspstore by N words will also cause bsp
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to be changed by (roughly) N as well. (It could be N-1 or N+1
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depending upon where the NaT collection bits fall.)
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OTOH, the Linux kernel provides read/write access to bsp (and
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currently read/write access to bspstore as well). But it
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is definitely the case that if you change one, the other
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will change at the same time. It is more useful to gdb to
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be able to change bsp. So in order to prevent strange and
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undesirable things from happening when a dummy stack frame
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is popped (after calling an inferior function), we allow
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bspstore to be read, but not written. (Note that popping
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a (generic) dummy stack frame causes all registers that
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were previously read from the inferior process to be written
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back.) */
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return regno < 0
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|| regno >= gdbarch_num_regs (gdbarch)
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|| u_offsets[regno] == -1
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|| regno == IA64_BSPSTORE_REGNUM;
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}
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void
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supply_gregset (struct regcache *regcache, const gregset_t *gregsetp)
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{
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int regi;
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const greg_t *regp = (const greg_t *) gregsetp;
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for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
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{
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regcache_raw_supply (regcache, regi, regp + (regi - IA64_GR0_REGNUM));
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}
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/* FIXME: NAT collection bits are at index 32; gotta deal with these
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somehow... */
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regcache_raw_supply (regcache, IA64_PR_REGNUM, regp + 33);
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for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
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{
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regcache_raw_supply (regcache, regi,
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regp + 34 + (regi - IA64_BR0_REGNUM));
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}
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regcache_raw_supply (regcache, IA64_IP_REGNUM, regp + 42);
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regcache_raw_supply (regcache, IA64_CFM_REGNUM, regp + 43);
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regcache_raw_supply (regcache, IA64_PSR_REGNUM, regp + 44);
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regcache_raw_supply (regcache, IA64_RSC_REGNUM, regp + 45);
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regcache_raw_supply (regcache, IA64_BSP_REGNUM, regp + 46);
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regcache_raw_supply (regcache, IA64_BSPSTORE_REGNUM, regp + 47);
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regcache_raw_supply (regcache, IA64_RNAT_REGNUM, regp + 48);
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regcache_raw_supply (regcache, IA64_CCV_REGNUM, regp + 49);
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regcache_raw_supply (regcache, IA64_UNAT_REGNUM, regp + 50);
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regcache_raw_supply (regcache, IA64_FPSR_REGNUM, regp + 51);
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regcache_raw_supply (regcache, IA64_PFS_REGNUM, regp + 52);
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regcache_raw_supply (regcache, IA64_LC_REGNUM, regp + 53);
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regcache_raw_supply (regcache, IA64_EC_REGNUM, regp + 54);
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}
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void
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fill_gregset (const struct regcache *regcache, gregset_t *gregsetp, int regno)
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{
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int regi;
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greg_t *regp = (greg_t *) gregsetp;
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#define COPY_REG(_idx_,_regi_) \
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if ((regno == -1) || regno == _regi_) \
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regcache_raw_collect (regcache, _regi_, regp + _idx_)
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for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
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{
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COPY_REG (regi - IA64_GR0_REGNUM, regi);
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}
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/* FIXME: NAT collection bits at index 32? */
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COPY_REG (33, IA64_PR_REGNUM);
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for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
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{
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COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi);
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}
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COPY_REG (42, IA64_IP_REGNUM);
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COPY_REG (43, IA64_CFM_REGNUM);
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COPY_REG (44, IA64_PSR_REGNUM);
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COPY_REG (45, IA64_RSC_REGNUM);
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COPY_REG (46, IA64_BSP_REGNUM);
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COPY_REG (47, IA64_BSPSTORE_REGNUM);
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COPY_REG (48, IA64_RNAT_REGNUM);
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COPY_REG (49, IA64_CCV_REGNUM);
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COPY_REG (50, IA64_UNAT_REGNUM);
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COPY_REG (51, IA64_FPSR_REGNUM);
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COPY_REG (52, IA64_PFS_REGNUM);
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COPY_REG (53, IA64_LC_REGNUM);
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COPY_REG (54, IA64_EC_REGNUM);
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}
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|
|
/* Given a pointer to a floating point register set in /proc format
|
|
(fpregset_t *), unpack the register contents and supply them as gdb's
|
|
idea of the current floating point register values. */
|
|
|
|
void
|
|
supply_fpregset (struct regcache *regcache, const fpregset_t *fpregsetp)
|
|
{
|
|
int regi;
|
|
const char *from;
|
|
const gdb_byte f_zero[16] = { 0 };
|
|
const gdb_byte f_one[16] =
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 };
|
|
|
|
/* Kernel generated cores have fr1==0 instead of 1.0. Older GDBs
|
|
did the same. So ignore whatever might be recorded in fpregset_t
|
|
for fr0/fr1 and always supply their expected values. */
|
|
|
|
/* fr0 is always read as zero. */
|
|
regcache_raw_supply (regcache, IA64_FR0_REGNUM, f_zero);
|
|
/* fr1 is always read as one (1.0). */
|
|
regcache_raw_supply (regcache, IA64_FR1_REGNUM, f_one);
|
|
|
|
for (regi = IA64_FR2_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
|
|
{
|
|
from = (const char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
|
|
regcache_raw_supply (regcache, regi, from);
|
|
}
|
|
}
|
|
|
|
/* Given a pointer to a floating point register set in /proc format
|
|
(fpregset_t *), update the register specified by REGNO from gdb's idea
|
|
of the current floating point register set. If REGNO is -1, update
|
|
them all. */
|
|
|
|
void
|
|
fill_fpregset (const struct regcache *regcache,
|
|
fpregset_t *fpregsetp, int regno)
|
|
{
|
|
int regi;
|
|
|
|
for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
|
|
{
|
|
if ((regno == -1) || (regno == regi))
|
|
regcache_raw_collect (regcache, regi,
|
|
&((*fpregsetp)[regi - IA64_FR0_REGNUM]));
|
|
}
|
|
}
|
|
|
|
#define IA64_PSR_DB (1UL << 24)
|
|
#define IA64_PSR_DD (1UL << 39)
|
|
|
|
static void
|
|
enable_watchpoints_in_psr (ptid_t ptid)
|
|
{
|
|
struct regcache *regcache = get_thread_regcache (ptid);
|
|
ULONGEST psr;
|
|
|
|
regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
|
|
if (!(psr & IA64_PSR_DB))
|
|
{
|
|
psr |= IA64_PSR_DB; /* Set the db bit - this enables hardware
|
|
watchpoints and breakpoints. */
|
|
regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
|
|
}
|
|
}
|
|
|
|
static long debug_registers[8];
|
|
|
|
static void
|
|
store_debug_register (ptid_t ptid, int idx, long val)
|
|
{
|
|
int tid;
|
|
|
|
tid = ptid_get_lwp (ptid);
|
|
if (tid == 0)
|
|
tid = ptid_get_pid (ptid);
|
|
|
|
(void) ptrace (PT_WRITE_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), val);
|
|
}
|
|
|
|
static void
|
|
store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr,
|
|
long *dbr_mask)
|
|
{
|
|
if (dbr_addr)
|
|
store_debug_register (ptid, 2 * idx, *dbr_addr);
|
|
if (dbr_mask)
|
|
store_debug_register (ptid, 2 * idx + 1, *dbr_mask);
|
|
}
|
|
|
|
static int
|
|
is_power_of_2 (int val)
|
|
{
|
|
int i, onecount;
|
|
|
|
onecount = 0;
|
|
for (i = 0; i < 8 * sizeof (val); i++)
|
|
if (val & (1 << i))
|
|
onecount++;
|
|
|
|
return onecount <= 1;
|
|
}
|
|
|
|
static int
|
|
ia64_linux_insert_watchpoint (struct target_ops *self,
|
|
CORE_ADDR addr, int len, int rw,
|
|
struct expression *cond)
|
|
{
|
|
struct lwp_info *lp;
|
|
int idx;
|
|
long dbr_addr, dbr_mask;
|
|
int max_watchpoints = 4;
|
|
|
|
if (len <= 0 || !is_power_of_2 (len))
|
|
return -1;
|
|
|
|
for (idx = 0; idx < max_watchpoints; idx++)
|
|
{
|
|
dbr_mask = debug_registers[idx * 2 + 1];
|
|
if ((dbr_mask & (0x3UL << 62)) == 0)
|
|
{
|
|
/* Exit loop if both r and w bits clear. */
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (idx == max_watchpoints)
|
|
return -1;
|
|
|
|
dbr_addr = (long) addr;
|
|
dbr_mask = (~(len - 1) & 0x00ffffffffffffffL); /* construct mask to match */
|
|
dbr_mask |= 0x0800000000000000L; /* Only match privilege level 3 */
|
|
switch (rw)
|
|
{
|
|
case hw_write:
|
|
dbr_mask |= (1L << 62); /* Set w bit */
|
|
break;
|
|
case hw_read:
|
|
dbr_mask |= (1L << 63); /* Set r bit */
|
|
break;
|
|
case hw_access:
|
|
dbr_mask |= (3L << 62); /* Set both r and w bits */
|
|
break;
|
|
default:
|
|
return -1;
|
|
}
|
|
|
|
debug_registers[2 * idx] = dbr_addr;
|
|
debug_registers[2 * idx + 1] = dbr_mask;
|
|
ALL_LWPS (lp)
|
|
{
|
|
store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask);
|
|
enable_watchpoints_in_psr (lp->ptid);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
ia64_linux_remove_watchpoint (struct target_ops *self,
|
|
CORE_ADDR addr, int len, int type,
|
|
struct expression *cond)
|
|
{
|
|
int idx;
|
|
long dbr_addr, dbr_mask;
|
|
int max_watchpoints = 4;
|
|
|
|
if (len <= 0 || !is_power_of_2 (len))
|
|
return -1;
|
|
|
|
for (idx = 0; idx < max_watchpoints; idx++)
|
|
{
|
|
dbr_addr = debug_registers[2 * idx];
|
|
dbr_mask = debug_registers[2 * idx + 1];
|
|
if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)
|
|
{
|
|
struct lwp_info *lp;
|
|
|
|
debug_registers[2 * idx] = 0;
|
|
debug_registers[2 * idx + 1] = 0;
|
|
dbr_addr = 0;
|
|
dbr_mask = 0;
|
|
|
|
ALL_LWPS (lp)
|
|
store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask);
|
|
|
|
return 0;
|
|
}
|
|
}
|
|
return -1;
|
|
}
|
|
|
|
static void
|
|
ia64_linux_new_thread (struct lwp_info *lp)
|
|
{
|
|
int i, any;
|
|
|
|
any = 0;
|
|
for (i = 0; i < 8; i++)
|
|
{
|
|
if (debug_registers[i] != 0)
|
|
any = 1;
|
|
store_debug_register (lp->ptid, i, debug_registers[i]);
|
|
}
|
|
|
|
if (any)
|
|
enable_watchpoints_in_psr (lp->ptid);
|
|
}
|
|
|
|
static int
|
|
ia64_linux_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p)
|
|
{
|
|
CORE_ADDR psr;
|
|
siginfo_t siginfo;
|
|
struct regcache *regcache = get_current_regcache ();
|
|
|
|
if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
|
|
return 0;
|
|
|
|
if (siginfo.si_signo != SIGTRAP
|
|
|| (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
|
|
return 0;
|
|
|
|
regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
|
|
psr |= IA64_PSR_DD; /* Set the dd bit - this will disable the watchpoint
|
|
for the next instruction. */
|
|
regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
|
|
|
|
*addr_p = (CORE_ADDR) siginfo.si_addr;
|
|
return 1;
|
|
}
|
|
|
|
static int
|
|
ia64_linux_stopped_by_watchpoint (struct target_ops *ops)
|
|
{
|
|
CORE_ADDR addr;
|
|
return ia64_linux_stopped_data_address (ops, &addr);
|
|
}
|
|
|
|
static int
|
|
ia64_linux_can_use_hw_breakpoint (struct target_ops *self,
|
|
int type, int cnt, int othertype)
|
|
{
|
|
return 1;
|
|
}
|
|
|
|
|
|
/* Fetch register REGNUM from the inferior. */
|
|
|
|
static void
|
|
ia64_linux_fetch_register (struct regcache *regcache, int regnum)
|
|
{
|
|
struct gdbarch *gdbarch = get_regcache_arch (regcache);
|
|
CORE_ADDR addr;
|
|
size_t size;
|
|
PTRACE_TYPE_RET *buf;
|
|
int pid, i;
|
|
|
|
/* r0 cannot be fetched but is always zero. */
|
|
if (regnum == IA64_GR0_REGNUM)
|
|
{
|
|
const gdb_byte zero[8] = { 0 };
|
|
|
|
gdb_assert (sizeof (zero) == register_size (gdbarch, regnum));
|
|
regcache_raw_supply (regcache, regnum, zero);
|
|
return;
|
|
}
|
|
|
|
/* fr0 cannot be fetched but is always zero. */
|
|
if (regnum == IA64_FR0_REGNUM)
|
|
{
|
|
const gdb_byte f_zero[16] = { 0 };
|
|
|
|
gdb_assert (sizeof (f_zero) == register_size (gdbarch, regnum));
|
|
regcache_raw_supply (regcache, regnum, f_zero);
|
|
return;
|
|
}
|
|
|
|
/* fr1 cannot be fetched but is always one (1.0). */
|
|
if (regnum == IA64_FR1_REGNUM)
|
|
{
|
|
const gdb_byte f_one[16] =
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 };
|
|
|
|
gdb_assert (sizeof (f_one) == register_size (gdbarch, regnum));
|
|
regcache_raw_supply (regcache, regnum, f_one);
|
|
return;
|
|
}
|
|
|
|
if (ia64_cannot_fetch_register (gdbarch, regnum))
|
|
{
|
|
regcache_raw_supply (regcache, regnum, NULL);
|
|
return;
|
|
}
|
|
|
|
/* Cater for systems like GNU/Linux, that implement threads as
|
|
separate processes. */
|
|
pid = ptid_get_lwp (inferior_ptid);
|
|
if (pid == 0)
|
|
pid = ptid_get_pid (inferior_ptid);
|
|
|
|
/* This isn't really an address, but ptrace thinks of it as one. */
|
|
addr = ia64_register_addr (gdbarch, regnum);
|
|
size = register_size (gdbarch, regnum);
|
|
|
|
gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
|
|
buf = alloca (size);
|
|
|
|
/* Read the register contents from the inferior a chunk at a time. */
|
|
for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
|
|
{
|
|
errno = 0;
|
|
buf[i] = ptrace (PT_READ_U, pid, (PTRACE_TYPE_ARG3)addr, 0);
|
|
if (errno != 0)
|
|
error (_("Couldn't read register %s (#%d): %s."),
|
|
gdbarch_register_name (gdbarch, regnum),
|
|
regnum, safe_strerror (errno));
|
|
|
|
addr += sizeof (PTRACE_TYPE_RET);
|
|
}
|
|
regcache_raw_supply (regcache, regnum, buf);
|
|
}
|
|
|
|
/* Fetch register REGNUM from the inferior. If REGNUM is -1, do this
|
|
for all registers. */
|
|
|
|
static void
|
|
ia64_linux_fetch_registers (struct target_ops *ops,
|
|
struct regcache *regcache, int regnum)
|
|
{
|
|
if (regnum == -1)
|
|
for (regnum = 0;
|
|
regnum < gdbarch_num_regs (get_regcache_arch (regcache));
|
|
regnum++)
|
|
ia64_linux_fetch_register (regcache, regnum);
|
|
else
|
|
ia64_linux_fetch_register (regcache, regnum);
|
|
}
|
|
|
|
/* Store register REGNUM into the inferior. */
|
|
|
|
static void
|
|
ia64_linux_store_register (const struct regcache *regcache, int regnum)
|
|
{
|
|
struct gdbarch *gdbarch = get_regcache_arch (regcache);
|
|
CORE_ADDR addr;
|
|
size_t size;
|
|
PTRACE_TYPE_RET *buf;
|
|
int pid, i;
|
|
|
|
if (ia64_cannot_store_register (gdbarch, regnum))
|
|
return;
|
|
|
|
/* Cater for systems like GNU/Linux, that implement threads as
|
|
separate processes. */
|
|
pid = ptid_get_lwp (inferior_ptid);
|
|
if (pid == 0)
|
|
pid = ptid_get_pid (inferior_ptid);
|
|
|
|
/* This isn't really an address, but ptrace thinks of it as one. */
|
|
addr = ia64_register_addr (gdbarch, regnum);
|
|
size = register_size (gdbarch, regnum);
|
|
|
|
gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
|
|
buf = alloca (size);
|
|
|
|
/* Write the register contents into the inferior a chunk at a time. */
|
|
regcache_raw_collect (regcache, regnum, buf);
|
|
for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
|
|
{
|
|
errno = 0;
|
|
ptrace (PT_WRITE_U, pid, (PTRACE_TYPE_ARG3)addr, buf[i]);
|
|
if (errno != 0)
|
|
error (_("Couldn't write register %s (#%d): %s."),
|
|
gdbarch_register_name (gdbarch, regnum),
|
|
regnum, safe_strerror (errno));
|
|
|
|
addr += sizeof (PTRACE_TYPE_RET);
|
|
}
|
|
}
|
|
|
|
/* Store register REGNUM back into the inferior. If REGNUM is -1, do
|
|
this for all registers. */
|
|
|
|
static void
|
|
ia64_linux_store_registers (struct target_ops *ops,
|
|
struct regcache *regcache, int regnum)
|
|
{
|
|
if (regnum == -1)
|
|
for (regnum = 0;
|
|
regnum < gdbarch_num_regs (get_regcache_arch (regcache));
|
|
regnum++)
|
|
ia64_linux_store_register (regcache, regnum);
|
|
else
|
|
ia64_linux_store_register (regcache, regnum);
|
|
}
|
|
|
|
|
|
static target_xfer_partial_ftype *super_xfer_partial;
|
|
|
|
static LONGEST
|
|
ia64_linux_xfer_partial (struct target_ops *ops,
|
|
enum target_object object,
|
|
const char *annex,
|
|
gdb_byte *readbuf, const gdb_byte *writebuf,
|
|
ULONGEST offset, ULONGEST len)
|
|
{
|
|
if (object == TARGET_OBJECT_UNWIND_TABLE && writebuf == NULL && offset == 0)
|
|
return syscall (__NR_getunwind, readbuf, len);
|
|
|
|
return super_xfer_partial (ops, object, annex, readbuf, writebuf,
|
|
offset, len);
|
|
}
|
|
|
|
/* For break.b instruction ia64 CPU forgets the immediate value and generates
|
|
SIGILL with ILL_ILLOPC instead of more common SIGTRAP with TRAP_BRKPT.
|
|
ia64 does not use gdbarch_decr_pc_after_break so we do not have to make any
|
|
difference for the signals here. */
|
|
|
|
static int
|
|
ia64_linux_status_is_event (int status)
|
|
{
|
|
return WIFSTOPPED (status) && (WSTOPSIG (status) == SIGTRAP
|
|
|| WSTOPSIG (status) == SIGILL);
|
|
}
|
|
|
|
void _initialize_ia64_linux_nat (void);
|
|
|
|
void
|
|
_initialize_ia64_linux_nat (void)
|
|
{
|
|
struct target_ops *t;
|
|
|
|
/* Fill in the generic GNU/Linux methods. */
|
|
t = linux_target ();
|
|
|
|
/* Override the default fetch/store register routines. */
|
|
t->to_fetch_registers = ia64_linux_fetch_registers;
|
|
t->to_store_registers = ia64_linux_store_registers;
|
|
|
|
/* Override the default to_xfer_partial. */
|
|
super_xfer_partial = t->to_xfer_partial;
|
|
t->to_xfer_partial = ia64_linux_xfer_partial;
|
|
|
|
/* Override watchpoint routines. */
|
|
|
|
/* The IA-64 architecture can step over a watch point (without triggering
|
|
it again) if the "dd" (data debug fault disable) bit in the processor
|
|
status word is set.
|
|
|
|
This PSR bit is set in ia64_linux_stopped_by_watchpoint when the
|
|
code there has determined that a hardware watchpoint has indeed
|
|
been hit. The CPU will then be able to execute one instruction
|
|
without triggering a watchpoint. */
|
|
|
|
t->to_have_steppable_watchpoint = 1;
|
|
t->to_can_use_hw_breakpoint = ia64_linux_can_use_hw_breakpoint;
|
|
t->to_stopped_by_watchpoint = ia64_linux_stopped_by_watchpoint;
|
|
t->to_stopped_data_address = ia64_linux_stopped_data_address;
|
|
t->to_insert_watchpoint = ia64_linux_insert_watchpoint;
|
|
t->to_remove_watchpoint = ia64_linux_remove_watchpoint;
|
|
|
|
/* Register the target. */
|
|
linux_nat_add_target (t);
|
|
linux_nat_set_new_thread (t, ia64_linux_new_thread);
|
|
linux_nat_set_status_is_event (t, ia64_linux_status_is_event);
|
|
}
|