475 lines
14 KiB
C
475 lines
14 KiB
C
/* Simulator cache routines for CGEN simulators (and maybe others).
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Copyright (C) 1996-2014 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#define SCACHE_DEFINE_INLINE
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#include "sim-main.h"
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#ifdef HAVE_STDLIB_H
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#include <stdlib.h>
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#endif
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#include "libiberty.h"
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#include "sim-options.h"
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#include "sim-io.h"
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#define MAX(a,b) ((a) > (b) ? (a) : (b))
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/* Unused address. */
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#define UNUSED_ADDR 0xffffffff
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/* Scache configuration parameters.
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??? Experiments to determine reasonable values is wip.
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These are just guesses. */
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/* Default number of scache elements.
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The size of an element is typically 32-64 bytes, so the size of the
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default scache will be between 512K and 1M bytes. */
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#ifdef CONFIG_SIM_CACHE_SIZE
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#define SCACHE_DEFAULT_CACHE_SIZE CONFIG_SIM_CACHE_SIZE
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#else
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#define SCACHE_DEFAULT_CACHE_SIZE 16384
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#endif
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/* Minimum cache size.
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The m32r port assumes a cache size of at least 2 so it can decode both 16
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bit insns. When compiling we need an extra for the chain entry. And this
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must be a multiple of 2. Hence 4 is the minimum (though, for those with
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featuritis or itchy pedantic bits, we could make this conditional on
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WITH_SCACHE_PBB). */
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#define MIN_SCACHE_SIZE 4
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/* Ratio of size of text section to size of scache.
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When compiling, we don't want to flush the scache more than we have to
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but we also don't want it to be exorbitantly(sp?) large. So we pick a high
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default value, then reduce it by the size of the program being simulated,
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but we don't override any value specified on the command line.
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If not specified on the command line, the size to use is computed as
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max (MIN_SCACHE_SIZE,
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min (DEFAULT_SCACHE_SIZE,
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text_size / (base_insn_size * INSN_SCACHE_RATIO))). */
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/* ??? Interesting idea but not currently used. */
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#define INSN_SCACHE_RATIO 4
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/* Default maximum insn chain length.
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The only reason for a maximum is so we can place a maximum size on the
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profiling table. Chain lengths are determined by cti's.
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32 is a more reasonable number, but when profiling, the before/after
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handlers take up that much more space. The scache is filled from front to
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back so all this determines is when the scache needs to be flushed. */
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#define MAX_CHAIN_LENGTH 64
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/* Default maximum hash list length. */
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#define MAX_HASH_CHAIN_LENGTH 4
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/* Minimum hash table size. */
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#define MIN_HASH_CHAINS 32
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/* Ratio of number of scache elements to number of hash lists.
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Since the user can only specify the size of the scache, we compute the
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size of the hash table as
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max (MIN_HASH_CHAINS, scache_size / SCACHE_HASH_RATIO). */
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#define SCACHE_HASH_RATIO 8
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/* Hash a PC value.
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FIXME: May wish to make the hashing architecture specific.
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FIXME: revisit */
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#define HASH_PC(pc) (((pc) >> 2) + ((pc) >> 5))
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static MODULE_INIT_FN scache_init;
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static MODULE_UNINSTALL_FN scache_uninstall;
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static DECLARE_OPTION_HANDLER (scache_option_handler);
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#define OPTION_PROFILE_SCACHE (OPTION_START + 0)
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static const OPTION scache_options[] = {
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{ {"scache-size", optional_argument, NULL, 'c'},
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'c', "[SIZE]", "Specify size of simulator execution cache",
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scache_option_handler },
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#if WITH_SCACHE_PBB
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/* ??? It might be nice to allow the user to specify the size of the hash
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table, the maximum hash list length, and the maximum chain length, but
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for now that might be more akin to featuritis. */
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#endif
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{ {"profile-scache", optional_argument, NULL, OPTION_PROFILE_SCACHE},
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'\0', "on|off", "Perform simulator execution cache profiling",
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scache_option_handler },
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{ {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
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};
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static SIM_RC
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scache_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt,
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char *arg, int is_command)
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{
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switch (opt)
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{
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case 'c' :
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if (WITH_SCACHE)
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{
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if (arg != NULL)
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{
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int n = strtol (arg, NULL, 0);
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if (n < MIN_SCACHE_SIZE)
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{
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sim_io_eprintf (sd, "invalid scache size `%d', must be at least 4", n);
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return SIM_RC_FAIL;
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}
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/* Ensure it's a multiple of 2. */
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if ((n & (n - 1)) != 0)
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{
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sim_io_eprintf (sd, "scache size `%d' not a multiple of 2\n", n);
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{
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/* round up to nearest multiple of 2 */
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int i;
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for (i = 1; i < n; i <<= 1)
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continue;
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n = i;
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}
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sim_io_eprintf (sd, "rounding scache size up to %d\n", n);
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}
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if (cpu == NULL)
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STATE_SCACHE_SIZE (sd) = n;
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else
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CPU_SCACHE_SIZE (cpu) = n;
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}
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else
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{
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if (cpu == NULL)
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STATE_SCACHE_SIZE (sd) = SCACHE_DEFAULT_CACHE_SIZE;
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else
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CPU_SCACHE_SIZE (cpu) = SCACHE_DEFAULT_CACHE_SIZE;
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}
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}
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else
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sim_io_eprintf (sd, "Simulator execution cache not enabled, `--scache-size' ignored\n");
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break;
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case OPTION_PROFILE_SCACHE :
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if (WITH_SCACHE && WITH_PROFILE_SCACHE_P)
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{
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/* FIXME: handle cpu != NULL. */
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return sim_profile_set_option (sd, "-scache", PROFILE_SCACHE_IDX,
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arg);
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}
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else
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sim_io_eprintf (sd, "Simulator cache profiling not compiled in, `--profile-scache' ignored\n");
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break;
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}
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return SIM_RC_OK;
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}
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SIM_RC
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scache_install (SIM_DESC sd)
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{
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sim_add_option_table (sd, NULL, scache_options);
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sim_module_add_init_fn (sd, scache_init);
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sim_module_add_uninstall_fn (sd, scache_uninstall);
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/* This is the default, it may be overridden on the command line. */
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STATE_SCACHE_SIZE (sd) = WITH_SCACHE;
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return SIM_RC_OK;
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}
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static SIM_RC
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scache_init (SIM_DESC sd)
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{
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int c;
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for (c = 0; c < MAX_NR_PROCESSORS; ++c)
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{
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SIM_CPU *cpu = STATE_CPU (sd, c);
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int elm_size = IMP_PROPS_SCACHE_ELM_SIZE (MACH_IMP_PROPS (CPU_MACH (cpu)));
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/* elm_size is 0 if the cpu doesn't not have scache support */
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if (elm_size == 0)
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{
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CPU_SCACHE_SIZE (cpu) = 0;
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CPU_SCACHE_CACHE (cpu) = NULL;
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}
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else
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{
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if (CPU_SCACHE_SIZE (cpu) == 0)
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CPU_SCACHE_SIZE (cpu) = STATE_SCACHE_SIZE (sd);
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CPU_SCACHE_CACHE (cpu) =
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(SCACHE *) xmalloc (CPU_SCACHE_SIZE (cpu) * elm_size);
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#if WITH_SCACHE_PBB
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CPU_SCACHE_MAX_CHAIN_LENGTH (cpu) = MAX_CHAIN_LENGTH;
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CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu) = MAX_HASH_CHAIN_LENGTH;
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CPU_SCACHE_NUM_HASH_CHAINS (cpu) = MAX (MIN_HASH_CHAINS,
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CPU_SCACHE_SIZE (cpu)
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/ SCACHE_HASH_RATIO);
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CPU_SCACHE_HASH_TABLE (cpu) =
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(SCACHE_MAP *) xmalloc (CPU_SCACHE_NUM_HASH_CHAINS (cpu)
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* CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu)
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* sizeof (SCACHE_MAP));
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CPU_SCACHE_PBB_BEGIN (cpu) = (SCACHE *) zalloc (elm_size);
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CPU_SCACHE_CHAIN_LENGTHS (cpu) =
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(unsigned long *) zalloc ((CPU_SCACHE_MAX_CHAIN_LENGTH (cpu) + 1)
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* sizeof (long));
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#endif
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}
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}
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scache_flush (sd);
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return SIM_RC_OK;
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}
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static void
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scache_uninstall (SIM_DESC sd)
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{
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int c;
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for (c = 0; c < MAX_NR_PROCESSORS; ++c)
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{
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SIM_CPU *cpu = STATE_CPU (sd, c);
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if (CPU_SCACHE_CACHE (cpu) != NULL)
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free (CPU_SCACHE_CACHE (cpu));
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#if WITH_SCACHE_PBB
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if (CPU_SCACHE_HASH_TABLE (cpu) != NULL)
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free (CPU_SCACHE_HASH_TABLE (cpu));
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if (CPU_SCACHE_PBB_BEGIN (cpu) != NULL)
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free (CPU_SCACHE_PBB_BEGIN (cpu));
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if (CPU_SCACHE_CHAIN_LENGTHS (cpu) != NULL)
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free (CPU_SCACHE_CHAIN_LENGTHS (cpu));
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#endif
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}
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}
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void
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scache_flush (SIM_DESC sd)
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{
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int c;
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for (c = 0; c < MAX_NR_PROCESSORS; ++c)
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{
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SIM_CPU *cpu = STATE_CPU (sd, c);
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scache_flush_cpu (cpu);
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}
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}
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void
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scache_flush_cpu (SIM_CPU *cpu)
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{
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int i,n;
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/* Don't bother if cache not in use. */
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if (CPU_SCACHE_SIZE (cpu) == 0)
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return;
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#if WITH_SCACHE_PBB
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/* It's important that this be reasonably fast as this can be done when
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the simulation is running. */
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CPU_SCACHE_NEXT_FREE (cpu) = CPU_SCACHE_CACHE (cpu);
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n = CPU_SCACHE_NUM_HASH_CHAINS (cpu) * CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu);
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/* ??? Might be faster to just set the first entry, then update the
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"last entry" marker during allocation. */
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for (i = 0; i < n; ++i)
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CPU_SCACHE_HASH_TABLE (cpu) [i] . pc = UNUSED_ADDR;
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#else
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{
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int elm_size = IMP_PROPS_SCACHE_ELM_SIZE (MACH_IMP_PROPS (CPU_MACH (cpu)));
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SCACHE *sc;
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/* Technically, this may not be necessary, but it helps debugging. */
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memset (CPU_SCACHE_CACHE (cpu), 0,
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CPU_SCACHE_SIZE (cpu) * elm_size);
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for (i = 0, sc = CPU_SCACHE_CACHE (cpu); i < CPU_SCACHE_SIZE (cpu);
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++i, sc = (SCACHE *) ((char *) sc + elm_size))
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{
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sc->argbuf.addr = UNUSED_ADDR;
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}
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}
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#endif
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}
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#if WITH_SCACHE_PBB
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/* Look up PC in the hash table of scache entry points.
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Returns the entry or NULL if not found. */
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SCACHE *
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scache_lookup (SIM_CPU *cpu, IADDR pc)
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{
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/* FIXME: hash computation is wrong, doesn't take into account
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NUM_HASH_CHAIN_ENTRIES. A lot of the hash table will be unused! */
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unsigned int slot = HASH_PC (pc) & (CPU_SCACHE_NUM_HASH_CHAINS (cpu) - 1);
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int i, max_i = CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu);
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SCACHE_MAP *scm;
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/* We don't update hit/miss statistics as this is only used when recording
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branch target addresses. */
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scm = & CPU_SCACHE_HASH_TABLE (cpu) [slot];
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for (i = 0; i < max_i && scm->pc != UNUSED_ADDR; ++i, ++scm)
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{
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if (scm->pc == pc)
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return scm->sc;
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}
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return 0;
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}
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/* Look up PC and if not found create an entry for it.
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If found the result is a pointer to the SCACHE entry.
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If not found the result is NULL, and the address of a buffer of at least
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N entries is stored in BUFP.
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It's done this way so the caller can still distinguish found/not-found.
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If the table is full, it is emptied to make room.
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If the maximum length of a hash list is reached a random entry is thrown out
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to make room.
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??? One might want to try to make this smarter, but let's see some
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measurable benefit first. */
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SCACHE *
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scache_lookup_or_alloc (SIM_CPU *cpu, IADDR pc, int n, SCACHE **bufp)
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{
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/* FIXME: hash computation is wrong, doesn't take into account
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NUM_HASH_CHAIN_ENTRIES. A lot of the hash table will be unused! */
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unsigned int slot = HASH_PC (pc) & (CPU_SCACHE_NUM_HASH_CHAINS (cpu) - 1);
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int i, max_i = CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu);
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SCACHE_MAP *scm;
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SCACHE *sc;
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scm = & CPU_SCACHE_HASH_TABLE (cpu) [slot];
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for (i = 0; i < max_i && scm->pc != UNUSED_ADDR; ++i, ++scm)
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{
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if (scm->pc == pc)
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{
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PROFILE_COUNT_SCACHE_HIT (cpu);
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return scm->sc;
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}
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}
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PROFILE_COUNT_SCACHE_MISS (cpu);
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/* The address we want isn't cached. Bummer.
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If the hash chain we have for this address is full, throw out an entry
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to make room. */
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if (i == max_i)
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{
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/* Rather than do something sophisticated like LRU, we just throw out
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a semi-random entry. Let someone else have the joy of saying how
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wrong this is. NEXT_FREE is the entry to throw out and cycles
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through all possibilities. */
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static int next_free = 0;
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scm = & CPU_SCACHE_HASH_TABLE (cpu) [slot];
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/* FIXME: This seems rather clumsy. */
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for (i = 0; i < next_free; ++i, ++scm)
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continue;
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++next_free;
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if (next_free == CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu))
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next_free = 0;
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}
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/* At this point SCM points to the hash table entry to use.
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Now make sure there's room in the cache. */
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/* FIXME: Kinda weird to use a next_free adjusted scm when cache is
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flushed. */
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{
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int elm_size = IMP_PROPS_SCACHE_ELM_SIZE (MACH_IMP_PROPS (CPU_MACH (cpu)));
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int elms_used = (((char *) CPU_SCACHE_NEXT_FREE (cpu)
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- (char *) CPU_SCACHE_CACHE (cpu))
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/ elm_size);
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int elms_left = CPU_SCACHE_SIZE (cpu) - elms_used;
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if (elms_left < n)
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{
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PROFILE_COUNT_SCACHE_FULL_FLUSH (cpu);
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scache_flush_cpu (cpu);
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}
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}
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sc = CPU_SCACHE_NEXT_FREE (cpu);
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scm->pc = pc;
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scm->sc = sc;
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*bufp = sc;
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return NULL;
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}
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#endif /* WITH_SCACHE_PBB */
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/* Print cache access statics for CPU. */
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void
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scache_print_profile (SIM_CPU *cpu, int verbose)
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{
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SIM_DESC sd = CPU_STATE (cpu);
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unsigned long hits = CPU_SCACHE_HITS (cpu);
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unsigned long misses = CPU_SCACHE_MISSES (cpu);
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char buf[20];
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unsigned long max_val;
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unsigned long *lengths;
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int i;
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if (CPU_SCACHE_SIZE (cpu) == 0)
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return;
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sim_io_printf (sd, "Simulator Cache Statistics\n\n");
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/* One could use PROFILE_LABEL_WIDTH here. I chose not to. */
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sim_io_printf (sd, " Cache size: %s\n",
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sim_add_commas (buf, sizeof (buf), CPU_SCACHE_SIZE (cpu)));
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sim_io_printf (sd, " Hits: %s\n",
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sim_add_commas (buf, sizeof (buf), hits));
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sim_io_printf (sd, " Misses: %s\n",
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sim_add_commas (buf, sizeof (buf), misses));
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if (hits + misses != 0)
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sim_io_printf (sd, " Hit rate: %.2f%%\n",
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((double) hits / ((double) hits + (double) misses)) * 100);
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#if WITH_SCACHE_PBB
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sim_io_printf (sd, "\n");
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sim_io_printf (sd, " Hash table size: %s\n",
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sim_add_commas (buf, sizeof (buf), CPU_SCACHE_NUM_HASH_CHAINS (cpu)));
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sim_io_printf (sd, " Max hash list length: %s\n",
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sim_add_commas (buf, sizeof (buf), CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu)));
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sim_io_printf (sd, " Max insn chain length: %s\n",
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sim_add_commas (buf, sizeof (buf), CPU_SCACHE_MAX_CHAIN_LENGTH (cpu)));
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sim_io_printf (sd, " Cache full flushes: %s\n",
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sim_add_commas (buf, sizeof (buf), CPU_SCACHE_FULL_FLUSHES (cpu)));
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sim_io_printf (sd, "\n");
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if (verbose)
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{
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sim_io_printf (sd, " Insn chain lengths:\n\n");
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max_val = 0;
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lengths = CPU_SCACHE_CHAIN_LENGTHS (cpu);
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for (i = 1; i < CPU_SCACHE_MAX_CHAIN_LENGTH (cpu); ++i)
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if (lengths[i] > max_val)
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max_val = lengths[i];
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for (i = 1; i < CPU_SCACHE_MAX_CHAIN_LENGTH (cpu); ++i)
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{
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sim_io_printf (sd, " %2d: %*s: ",
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i,
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max_val < 10000 ? 5 : 10,
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sim_add_commas (buf, sizeof (buf), lengths[i]));
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sim_profile_print_bar (sd, cpu, PROFILE_HISTOGRAM_WIDTH,
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lengths[i], max_val);
|
|
sim_io_printf (sd, "\n");
|
|
}
|
|
sim_io_printf (sd, "\n");
|
|
}
|
|
#endif /* WITH_SCACHE_PBB */
|
|
}
|