337 lines
12 KiB
C++
337 lines
12 KiB
C++
/* Opcode table header for Visium.
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Copyright (C) 2003-2015 Free Software Foundation, Inc.
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This file is part of GDB, GAS, and GNU binutils.
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GDB, GAS and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version 3,
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or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING3. If not, write to the Free
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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enum visium_opcode_arch_val
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{
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VISIUM_OPCODE_ARCH_DEF = 0,
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VISIUM_OPCODE_ARCH_GR5,
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VISIUM_OPCODE_ARCH_GR6,
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VISIUM_OPCODE_ARCH_BAD
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};
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/* The highest architecture in the table. */
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#define VISIUM_OPCODE_ARCH_MAX (VISIUM_OPCODE_ARCH_BAD - 1)
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/* Given an enum visium_opcode_arch_val, return the bitmask to use in
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insn encoding/decoding. */
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#define VISIUM_OPCODE_ARCH_MASK(arch) (1 << (arch))
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/* Some defines to make life easy. */
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#define MASK_DEF VISIUM_OPCODE_ARCH_MASK (VISIUM_OPCODE_ARCH_DEF)
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#define MASK_GR5 VISIUM_OPCODE_ARCH_MASK (VISIUM_OPCODE_ARCH_GR5)
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#define MASK_GR6 VISIUM_OPCODE_ARCH_MASK (VISIUM_OPCODE_ARCH_GR6)
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/* Bit masks of architectures supporting the insn. */
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#define def (MASK_DEF | MASK_GR5 | MASK_GR6)
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#define gr5 (MASK_GR5 | MASK_GR6)
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#define gr6 (MASK_GR6)
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/* The condition code field is not used (zero) for most instructions.
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BRR and BRA make normal use of it. Floating point instructions use
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it as a sub-opcode. */
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#define CC_MASK (0xf << 27)
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/* It seems a shame not to use these bits in a class 0 instruction,
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since they could be used to extend the range of the branch. */
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#define CLASS0_UNUSED_MASK (0x1f << 16)
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/* For class 1 instructions the following bit is unused. */
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#define CLASS1_UNUSED_MASK (1 << 9)
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/* For class 1 instructions this field gives the index for a write
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instruction, the specific operation for an EAM instruction, or
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the floating point destination register for a floating point
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instruction. */
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#define CLASS1_INDEX_MASK (0x1f << 10)
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/* For class 3 instructions the following field gives the destination
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general register. */
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#define CLASS3_DEST_MASK (0x1f << 10)
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/* For class 1 and class 3 instructions the following bit selects an
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EAM write/read rather than a memory write/read. */
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#define EAM_SELECT_MASK (1 << 15)
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/* Floating point instructions are distinguished from general EAM
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instructions by the following bit. */
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#define FP_SELECT_MASK (1 << 3)
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/* For both class 1 and class 3 the following fields give, where
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appropriate the srcA and srcB registers whether floating point
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or general. */
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#define SRCA_MASK (0x1f << 16)
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#define SRCB_MASK (0x1f << 4)
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/* The class 3 interrupt bit. It turns a BRA into a SYS1, and an
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RFLAG into a SYS2. This bit should not be set in the user's
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class 3 instructions. This bit is also used in class 3
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to distinguish between floating point and other EAM operations.
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(see FP_SELECT_MASK). */
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#define CLASS3_INT (1 << 3)
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/* Class 3 shift instructions use this bit to indicate that the
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srcB field is a 5 bit immediate shift count rather than a
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register number. */
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#define CLASS3_SOURCEB_IMMED (1 << 9)
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#define BMD 0x02630004
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#define BMI 0x82230004
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#define DSI 0x82800004
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#define ENI 0x02a00004
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#define RFI 0x82fe01d4
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struct reg_entry
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{
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char *name;
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unsigned char code;
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};
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const struct reg_entry gen_reg_table[] =
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{
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{"fp", 0x16},
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{"r0", 0x0},
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{"r1", 0x1},
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{"r10", 0xA},
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{"r11", 0xB},
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{"r12", 0xC},
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{"r13", 0xD},
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{"r14", 0xE},
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{"r15", 0xF},
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{"r16", 0x10},
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{"r17", 0x11},
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{"r18", 0x12},
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{"r19", 0x13},
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{"r2", 0x2},
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{"r20", 0x14},
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{"r21", 0x15},
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{"r22", 0x16},
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{"r23", 0x17},
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{"r24", 0x18},
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{"r25", 0x19},
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{"r26", 0x1a},
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{"r27", 0x1b},
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{"r28", 0x1c},
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{"r29", 0x1d},
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{"r3", 0x3},
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{"r30", 0x1e},
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{"r31", 0x1f},
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{"r4", 0x4},
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{"r5", 0x5},
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{"r6", 0x6},
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{"r7", 0x7},
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{"r8", 0x8},
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{"r9", 0x9},
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{"sp", 0x17},
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};
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const struct reg_entry fp_reg_table[] =
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{
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{"f0", 0x0},
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{"f1", 0x1},
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{"f10", 0xa},
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{"f11", 0xb},
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{"f12", 0xc},
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{"f13", 0xd},
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{"f14", 0xe},
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{"f15", 0xf},
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{"f2", 0x2},
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{"f3", 0x3},
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{"f4", 0x4},
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{"f5", 0x5},
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{"f6", 0x6},
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{"f7", 0x7},
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{"f8", 0x8},
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{"f9", 0x9},
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};
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const struct cc_entry
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{
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char *name;
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int code;
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} cc_table [] =
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{
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{"cc", 6},
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{"cs", 2},
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{"eq", 1},
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{"fa", 0},
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{"ge", 9},
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{"gt", 10},
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{"hi", 11},
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{"le", 12},
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{"ls", 13},
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{"lt", 14},
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{"nc", 8},
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{"ne", 5},
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{"ns", 4},
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{"oc", 7},
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{"os", 3},
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{"tr", 15},
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};
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enum addressing_mode
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{
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mode_d, /* register := */
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mode_a, /* op= register */
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mode_da, /* register := register */
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mode_ab, /* register * register */
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mode_dab, /* register := register * register */
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mode_iab, /* 5-bit immediate * register * register */
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mode_0ab, /* zero * register * register */
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mode_da0, /* register := register * zero */
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mode_cad, /* condition * register * register */
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mode_das, /* register := register * 5-bit immed/register shift count */
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mode_di, /* register := 5-bit immediate */
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mode_ir, /* 5-bit immediate * register */
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mode_ai, /* register 16-bit unsigned immediate */
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mode_i, /* 16-bit unsigned immediate */
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mode_bax, /* register * register * 5-bit immediate */
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mode_dax, /* register := register * 5-bit immediate */
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mode_s, /* special mode */
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mode_sr, /* special mode with register */
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mode_ci, /* condition * 16-bit signed word displacement */
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mode_fdab, /* float := float * float */
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mode_ifdab, /* fpinst: 4-bit immediate * float * float * float */
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mode_idfab, /* fpuread: 4-bit immediate * register * float * float */
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mode_fda, /* float := float */
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mode_fdra, /* float := register */
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mode_rdfab, /* register := float * float */
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mode_rdfa, /* register := float */
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mode_rrr, /* 3 register sources and destinations (block move) */
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};
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#define class0 (0<<25)
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#define class1 (1<<25)
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#define class2 (2<<25)
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#define class3 (3<<25)
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static const struct opcode_entry
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{
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char *mnem;
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enum addressing_mode mode;
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unsigned code;
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char flags;
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}
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opcode_table[] =
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{
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{ "adc.b", mode_dab, class3|(1<<21)|(1), def },
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{ "adc.l", mode_dab, class3|(1<<21)|(4), def },
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{ "adc.w", mode_dab, class3|(1<<21)|(2), def },
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{ "add.b", mode_dab, class3|(0<<21)|(1), def },
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{ "add.l", mode_dab, class3|(0<<21)|(4), def },
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{ "add.w", mode_dab, class3|(0<<21)|(2), def },
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{ "addi", mode_ai, class2, def },
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{ "and.b", mode_dab, class3|(10<<21)|(1), def},
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{ "and.l", mode_dab, class3|(10<<21)|(4), def },
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{ "and.w", mode_dab, class3|(10<<21)|(2), def },
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{ "asl.b", mode_das, class3|(7<<21)|(1), def },
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{ "asl.l", mode_das, class3|(7<<21)|(4), def },
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{ "asl.w", mode_das, class3|(7<<21)|(2), def },
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{ "asld", mode_a, class1|(15<<21)|(1<<15)|(11<<10)|(4), def },
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{ "asr.b", mode_das, class3|(5<<21)|(1), def },
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{ "asr.l", mode_das, class3|(5<<21)|(4), def },
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{ "asr.w", mode_das, class3|(5<<21)|(2), def },
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{ "asrd", mode_a, class1|(15<<21)|(1<<15)|(9<<10)|(4), def },
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{ "bmd", mode_rrr, class1|(3<<21)|(3<<16)|(4), gr6 },
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{ "bmi", mode_rrr, class1|(1<<21)|(3<<16)|(4), gr6 },
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{ "bra", mode_cad, class3|(12<<21)|(4), def },
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{ "brr", mode_ci, class0, def },
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{ "cmp.b", mode_0ab, class3|(2<<21)|(1), def },
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{ "cmp.l", mode_0ab, class3|(2<<21)|(4), def },
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{ "cmp.w", mode_0ab, class3|(2<<21)|(2), def },
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{ "cmpc.b", mode_0ab, class3|(3<<21)|(1), def },
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{ "cmpc.l", mode_0ab, class3|(3<<21)|(4), def },
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{ "cmpc.w", mode_0ab, class3|(3<<21)|(2), def },
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{ "divds", mode_a, class1|(15<<21)|(1<<15)|(6<<10)|(4), def },
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{ "divdu", mode_a, class1|(15<<21)|(1<<15)|(7<<10)|(4), def },
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{ "divs", mode_a, class1|(15<<21)|(1<<15)|(2<<10)|(4), def },
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{ "divu", mode_a, class1|(15<<21)|(1<<15)|(3<<10)|(4), def },
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{ "dsi", mode_s, class1|(4<<21)|(4), def },
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{ "eamread", mode_di, class3|(15<<21)|(1<<15)|(1<<9)|(4), def },
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{ "eamwrite", mode_iab, class1|(15<<21)|(1<<15)|(4), def },
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{ "eni", mode_s, class1|(5<<21)|(4), def },
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{ "extb.b", mode_da, class3|(14<<21)|(1), def },
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{ "extb.l", mode_da, class3|(14<<21)|(4), def },
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{ "extb.w", mode_da, class3|(14<<21)|(2), def },
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{ "extw.l", mode_da, class3|(4<<21)|(4), def },
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{ "extw.w", mode_da, class3|(4<<21)|(2), def },
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{ "fabs", mode_fda, class1|(7<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 },
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{ "fadd", mode_fdab, class1|(1<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 },
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{ "fcmp", mode_rdfab,class3|(10<<27)|(15<<21)|(1<<15)|(1<<9)|(1<<3)|(4), gr5 },
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{ "fcmpe", mode_rdfab,class3|(11<<27)|(15<<21)|(1<<15)|(1<<9)|(1<<3)|(4), gr5 },
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{ "fdiv", mode_fdab, class1|(4<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 },
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{ "fload", mode_fdra, class1|(15<<21)|(1<<15)|(1<<3)|(4), gr5 },
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{ "fmove", mode_fda, class1|(12<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5},
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{ "fmult", mode_fdab, class1|(3<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 },
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{ "fneg", mode_fda, class1|(6<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 },
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{ "fpinst", mode_ifdab,class1|(15<<21)|(1<<15)|(1<<3)|(4), gr5 },
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{ "fpuread", mode_idfab,class3|(15<<21)|(1<<15)|(1<<9)|(1<<3)|(4), gr5 },
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{ "fsqrt", mode_fda, class1|(5<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 },
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{ "fstore", mode_rdfa, class3|(15<<21)|(1<<15)|(1<<9)|(1<<3)|(4), gr5 },
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{ "fsub", mode_fdab, class1|(2<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 },
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{ "ftoi", mode_fda, class1|(8<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 },
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{ "itof", mode_fda, class1|(9<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 },
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{ "lsr.b", mode_das, class3|(6<<21)|(1), def },
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{ "lsr.l", mode_das, class3|(6<<21)|(4), def },
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{ "lsr.w", mode_das, class3|(6<<21)|(2), def },
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{ "lsrd", mode_a, class1|(15<<21)|(1<<15)|(10<<10)|(4), def },
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{ "move.b", mode_da0, class3|(9<<21)|(1), def },
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{ "move.l", mode_da0, class3|(9<<21)|(4), def },
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{ "move.w", mode_da0, class3|(9<<21)|(2), def },
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{ "movil", mode_ai, class2|(4<<21), def },
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{ "moviq", mode_ai, class2|(6<<21), def },
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{ "moviu", mode_ai, class2|(5<<21), def },
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{ "mults", mode_ab, class1|(15<<21)|(1<<15)|(0<<10)|(4), def },
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{ "multu", mode_ab, class1|(15<<21)|(1<<15)|(1<<10)|(4), def },
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{ "nop", mode_s, class0, def },
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{ "not.b", mode_da, class3|(11<<21)|(1), def },
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{ "not.l", mode_da, class3|(11<<21)|(4), def },
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{ "not.w", mode_da, class3|(11<<21)|(2), def },
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{ "or.b", mode_dab, class3|(9<<21)|(1), def },
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{ "or.l", mode_dab, class3|(9<<21)|(4), def },
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{ "or.w", mode_dab, class3|(9<<21)|(2), def },
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{ "read.b", mode_dax, class3|(15<<21)|(1<<9)|(1), def },
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{ "read.l", mode_dax, class3|(15<<21)|(1<<9)|(4), def },
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{ "read.w", mode_dax, class3|(15<<21)|(1<<9)|(2), def },
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{ "readmda", mode_d, class3|(15<<21)|(1<<15)|(1<<9)|(4), def },
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{ "readmdb", mode_d, class3|(15<<21)|(1<<15)|(1<<9)|(1<<4)|(4), def },
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{ "readmdc", mode_d, class3|(15<<21)|(1<<15)|(1<<9)|(2<<4)|(4), def },
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{ "rfi", mode_s, class1|(7<<21)|(30<<16)|(29<<4)|(4), def },
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{ "rflag", mode_d, class3|(13<<21)|(4), def },
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{ "stop", mode_ir, class1|(0<<21)|(4), def },
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{ "sub.b", mode_dab, class3|(2<<21)|(1), def },
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{ "sub.l", mode_dab, class3|(2<<21)|(4), def },
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{ "sub.w", mode_dab, class3|(2<<21)|(2), def },
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{ "subc.b", mode_dab, class3|(3<<21)|(1), def },
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{ "subc.l", mode_dab, class3|(3<<21)|(4), def },
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{ "subc.w", mode_dab, class3|(3<<21)|(2), def },
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{ "subi", mode_ai, class2|(2<<21), def },
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{ "trace", mode_ir, class1|(13<<21), def },
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{ "write.b", mode_bax, class1|(15<<21)|(1), def },
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{ "write.l", mode_bax, class1|(15<<21)|(4), def },
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{ "write.w", mode_bax, class1|(15<<21)|(2), def },
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{ "writemd", mode_ab, class1|(15<<21)|(1<<15)|(4<<10)|(4), def },
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{ "writemdc", mode_a, class1|(15<<21)|(1<<15)|(5<<10)|(4), def },
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{ "wrtl", mode_i, class2|(8<<21), gr6 },
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{ "wrtu", mode_i, class2|(9<<21), gr6 },
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{ "xor.b", mode_dab, class3|(8<<21)|(1), def },
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{ "xor.l", mode_dab, class3|(8<<21)|(4), def },
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{ "xor.w", mode_dab, class3|(8<<21)|(2), def },
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};
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