7d5c6c43ca
Many ports have the same sim syscall logic, so add some helpers to handle all the common details. The arches still have to deal with the unpacking and packing of the syscall arguments, but the rest of the sim<->callback glue is now shared.
184 lines
4.1 KiB
C
184 lines
4.1 KiB
C
#include "sim-main.h"
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#include "sim-syscall.h"
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#include "targ-vals.h"
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#ifdef HAVE_UTIME_H
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#include <utime.h>
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#endif
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#ifdef HAVE_TIME_H
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#include <time.h>
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#endif
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#ifdef HAVE_UNISTD_H
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#include <unistd.h>
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#endif
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#ifdef HAVE_STRING_H
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#include <string.h>
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#else
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#ifdef HAVE_STRINGS_H
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#include <strings.h>
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#endif
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#endif
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#include <sys/stat.h>
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#include <sys/times.h>
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#include <sys/time.h>
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#define REG0(X) ((X) & 0x3)
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#define REG1(X) (((X) & 0xc) >> 2)
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#define REG0_4(X) (((X) & 0x30) >> 4)
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#define REG0_8(X) (((X) & 0x300) >> 8)
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#define REG1_8(X) (((X) & 0xc00) >> 10)
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#define REG0_16(X) (((X) & 0x30000) >> 16)
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#define REG1_16(X) (((X) & 0xc0000) >> 18)
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INLINE_SIM_MAIN (void)
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genericAdd(unsigned32 source, unsigned32 destReg)
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{
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int z, c, n, v;
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unsigned32 dest, sum;
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dest = State.regs[destReg];
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sum = source + dest;
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State.regs[destReg] = sum;
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z = (sum == 0);
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n = (sum & 0x80000000);
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c = (sum < source) || (sum < dest);
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v = ((dest & 0x80000000) == (source & 0x80000000)
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&& (dest & 0x80000000) != (sum & 0x80000000));
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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}
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INLINE_SIM_MAIN (void)
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genericSub(unsigned32 source, unsigned32 destReg)
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{
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int z, c, n, v;
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unsigned32 dest, difference;
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dest = State.regs[destReg];
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difference = dest - source;
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State.regs[destReg] = difference;
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z = (difference == 0);
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n = (difference & 0x80000000);
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c = (source > dest);
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v = ((dest & 0x80000000) != (source & 0x80000000)
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&& (dest & 0x80000000) != (difference & 0x80000000));
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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}
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INLINE_SIM_MAIN (void)
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genericCmp(unsigned32 leftOpnd, unsigned32 rightOpnd)
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{
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int z, c, n, v;
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unsigned32 value;
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value = rightOpnd - leftOpnd;
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z = (value == 0);
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n = (value & 0x80000000);
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c = (leftOpnd > rightOpnd);
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v = ((rightOpnd & 0x80000000) != (leftOpnd & 0x80000000)
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&& (rightOpnd & 0x80000000) != (value & 0x80000000));
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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}
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INLINE_SIM_MAIN (void)
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genericOr(unsigned32 source, unsigned32 destReg)
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{
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int n, z;
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State.regs[destReg] |= source;
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z = (State.regs[destReg] == 0);
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n = (State.regs[destReg] & 0x80000000) != 0;
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
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}
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INLINE_SIM_MAIN (void)
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genericXor(unsigned32 source, unsigned32 destReg)
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{
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int n, z;
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State.regs[destReg] ^= source;
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z = (State.regs[destReg] == 0);
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n = (State.regs[destReg] & 0x80000000) != 0;
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
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}
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INLINE_SIM_MAIN (void)
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genericBtst(unsigned32 leftOpnd, unsigned32 rightOpnd)
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{
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unsigned32 temp;
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int z, n;
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temp = rightOpnd;
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temp &= leftOpnd;
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n = (temp & 0x80000000) != 0;
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z = (temp == 0);
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
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}
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/* syscall */
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INLINE_SIM_MAIN (void)
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do_syscall (void)
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{
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/* Registers passed to trap 0. */
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/* Function number. */
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reg_t func = State.regs[0];
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/* Parameters. */
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reg_t parm1 = State.regs[1];
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reg_t parm2 = load_word (State.regs[REG_SP] + 12);
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reg_t parm3 = load_word (State.regs[REG_SP] + 16);
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reg_t parm4 = load_word (State.regs[REG_SP] + 20);
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/* We use this for simulated system calls; we may need to change
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it to a reserved instruction if we conflict with uses at
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Matsushita. */
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int save_errno = errno;
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errno = 0;
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if (func == TARGET_SYS_exit)
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{
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/* EXIT - caller can look in parm1 to work out the reason */
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sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
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(parm1 == 0xdead ? SIM_SIGABRT : sim_exited), parm1);
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}
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else
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{
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long result, result2;
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int errcode;
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sim_syscall_multi (STATE_CPU (simulator, 0), func, parm1, parm2,
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parm3, parm4, &result, &result2, &errcode);
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/* Registers set by trap 0. */
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State.regs[0] = errcode;
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State.regs[1] = result;
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}
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errno = save_errno;
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}
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