454de2ee15
* armcopro.c: Remove extraneous whitespace. * armdefs.h: Likewise. * armfpe.h: Likewise. * arminit.c: Likewise. * armopts.h: Likewise. * armos.c: Likewise. * armos.h: Likewise. * armrdi.c: Likewise. * armsupp.c: Likewise. * armvirt.c: Likewise. * bag.c: Likewise. * bag.h: Likewise. * communicate.c: Likewise. * communicate.h: Likewise. * dbg_conf.h: Likewise. * dbg_cp.h: Likewise. * dbg_hif.h: Likewise. * dbg_rdi.h: Likewise. * gdbhost.c: Likewise. * gdbhost.h: Likewise. * iwmmxt.c: Likewise. * iwmmxt.h: Likewise. * kid.c: Likewise. * main.c: Likewise. * maverick.c: Likewise. * parent.c: Likewise. * thumbemu.c: Likewise. * wrapper.c: Likewise.
1700 lines
37 KiB
C
1700 lines
37 KiB
C
/* armsupp.c -- ARMulator support code: ARM6 Instruction Emulator.
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Copyright (C) 1994 Advanced RISC Machines Ltd.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see <http://www.gnu.org/licenses/>. */
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#include "armdefs.h"
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#include "armemu.h"
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#include "ansidecl.h"
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#include <math.h>
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/* Definitions for the support routines. */
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static ARMword ModeToBank (ARMword);
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static void EnvokeList (ARMul_State *, unsigned long, unsigned long);
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struct EventNode
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{ /* An event list node. */
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unsigned (*func) (ARMul_State *); /* The function to call. */
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struct EventNode *next;
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};
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/* This routine returns the value of a register from a mode. */
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ARMword
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ARMul_GetReg (ARMul_State * state, unsigned mode, unsigned reg)
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{
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mode &= MODEBITS;
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if (mode != state->Mode)
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return (state->RegBank[ModeToBank ((ARMword) mode)][reg]);
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else
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return (state->Reg[reg]);
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}
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/* This routine sets the value of a register for a mode. */
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void
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ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg, ARMword value)
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{
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mode &= MODEBITS;
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if (mode != state->Mode)
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state->RegBank[ModeToBank ((ARMword) mode)][reg] = value;
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else
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state->Reg[reg] = value;
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}
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/* This routine returns the value of the PC, mode independently. */
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ARMword
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ARMul_GetPC (ARMul_State * state)
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{
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if (state->Mode > SVC26MODE)
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return state->Reg[15];
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else
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return R15PC;
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}
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/* This routine returns the value of the PC, mode independently. */
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ARMword
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ARMul_GetNextPC (ARMul_State * state)
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{
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if (state->Mode > SVC26MODE)
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return state->Reg[15] + isize;
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else
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return (state->Reg[15] + isize) & R15PCBITS;
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}
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/* This routine sets the value of the PC. */
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void
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ARMul_SetPC (ARMul_State * state, ARMword value)
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{
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if (ARMul_MODE32BIT)
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state->Reg[15] = value & PCBITS;
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else
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state->Reg[15] = R15CCINTMODE | (value & R15PCBITS);
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FLUSHPIPE;
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}
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/* This routine returns the value of register 15, mode independently. */
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ARMword
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ARMul_GetR15 (ARMul_State * state)
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{
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if (state->Mode > SVC26MODE)
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return (state->Reg[15]);
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else
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return (R15PC | ECC | ER15INT | EMODE);
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}
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/* This routine sets the value of Register 15. */
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void
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ARMul_SetR15 (ARMul_State * state, ARMword value)
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{
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if (ARMul_MODE32BIT)
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state->Reg[15] = value & PCBITS;
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else
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{
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state->Reg[15] = value;
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ARMul_R15Altered (state);
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}
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FLUSHPIPE;
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}
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/* This routine returns the value of the CPSR. */
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ARMword
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ARMul_GetCPSR (ARMul_State * state)
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{
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return (CPSR | state->Cpsr);
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}
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/* This routine sets the value of the CPSR. */
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void
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ARMul_SetCPSR (ARMul_State * state, ARMword value)
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{
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state->Cpsr = value;
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ARMul_CPSRAltered (state);
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}
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/* This routine does all the nasty bits involved in a write to the CPSR,
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including updating the register bank, given a MSR instruction. */
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void
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ARMul_FixCPSR (ARMul_State * state, ARMword instr, ARMword rhs)
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{
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state->Cpsr = ARMul_GetCPSR (state);
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if (state->Mode != USER26MODE
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&& state->Mode != USER32MODE)
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{
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/* In user mode, only write flags. */
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if (BIT (16))
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SETPSR_C (state->Cpsr, rhs);
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if (BIT (17))
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SETPSR_X (state->Cpsr, rhs);
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if (BIT (18))
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SETPSR_S (state->Cpsr, rhs);
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}
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if (BIT (19))
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SETPSR_F (state->Cpsr, rhs);
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ARMul_CPSRAltered (state);
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}
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/* Get an SPSR from the specified mode. */
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ARMword
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ARMul_GetSPSR (ARMul_State * state, ARMword mode)
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{
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ARMword bank = ModeToBank (mode & MODEBITS);
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if (! BANK_CAN_ACCESS_SPSR (bank))
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return ARMul_GetCPSR (state);
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return state->Spsr[bank];
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}
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/* This routine does a write to an SPSR. */
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void
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ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value)
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{
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ARMword bank = ModeToBank (mode & MODEBITS);
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if (BANK_CAN_ACCESS_SPSR (bank))
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state->Spsr[bank] = value;
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}
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/* This routine does a write to the current SPSR, given an MSR instruction. */
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void
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ARMul_FixSPSR (ARMul_State * state, ARMword instr, ARMword rhs)
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{
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if (BANK_CAN_ACCESS_SPSR (state->Bank))
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{
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if (BIT (16))
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SETPSR_C (state->Spsr[state->Bank], rhs);
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if (BIT (17))
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SETPSR_X (state->Spsr[state->Bank], rhs);
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if (BIT (18))
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SETPSR_S (state->Spsr[state->Bank], rhs);
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if (BIT (19))
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SETPSR_F (state->Spsr[state->Bank], rhs);
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}
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}
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/* This routine updates the state of the emulator after the Cpsr has been
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changed. Both the processor flags and register bank are updated. */
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void
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ARMul_CPSRAltered (ARMul_State * state)
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{
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ARMword oldmode;
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if (state->prog32Sig == LOW)
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state->Cpsr &= (CCBITS | INTBITS | R15MODEBITS);
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oldmode = state->Mode;
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if (state->Mode != (state->Cpsr & MODEBITS))
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{
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state->Mode =
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ARMul_SwitchMode (state, state->Mode, state->Cpsr & MODEBITS);
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state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
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}
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state->Cpsr &= ~MODEBITS;
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ASSIGNINT (state->Cpsr & INTBITS);
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state->Cpsr &= ~INTBITS;
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ASSIGNN ((state->Cpsr & NBIT) != 0);
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state->Cpsr &= ~NBIT;
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ASSIGNZ ((state->Cpsr & ZBIT) != 0);
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state->Cpsr &= ~ZBIT;
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ASSIGNC ((state->Cpsr & CBIT) != 0);
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state->Cpsr &= ~CBIT;
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ASSIGNV ((state->Cpsr & VBIT) != 0);
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state->Cpsr &= ~VBIT;
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ASSIGNS ((state->Cpsr & SBIT) != 0);
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state->Cpsr &= ~SBIT;
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#ifdef MODET
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ASSIGNT ((state->Cpsr & TBIT) != 0);
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state->Cpsr &= ~TBIT;
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#endif
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if (oldmode > SVC26MODE)
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{
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if (state->Mode <= SVC26MODE)
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{
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state->Emulate = CHANGEMODE;
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state->Reg[15] = ECC | ER15INT | EMODE | R15PC;
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}
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}
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else
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{
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if (state->Mode > SVC26MODE)
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{
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state->Emulate = CHANGEMODE;
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state->Reg[15] = R15PC;
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}
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else
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state->Reg[15] = ECC | ER15INT | EMODE | R15PC;
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}
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}
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/* This routine updates the state of the emulator after register 15 has
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been changed. Both the processor flags and register bank are updated.
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This routine should only be called from a 26 bit mode. */
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void
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ARMul_R15Altered (ARMul_State * state)
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{
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if (state->Mode != R15MODE)
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{
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state->Mode = ARMul_SwitchMode (state, state->Mode, R15MODE);
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state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
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}
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if (state->Mode > SVC26MODE)
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state->Emulate = CHANGEMODE;
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ASSIGNR15INT (R15INT);
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ASSIGNN ((state->Reg[15] & NBIT) != 0);
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ASSIGNZ ((state->Reg[15] & ZBIT) != 0);
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ASSIGNC ((state->Reg[15] & CBIT) != 0);
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ASSIGNV ((state->Reg[15] & VBIT) != 0);
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}
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/* This routine controls the saving and restoring of registers across mode
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changes. The regbank matrix is largely unused, only rows 13 and 14 are
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used across all modes, 8 to 14 are used for FIQ, all others use the USER
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column. It's easier this way. old and new parameter are modes numbers.
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Notice the side effect of changing the Bank variable. */
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ARMword
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ARMul_SwitchMode (ARMul_State * state, ARMword oldmode, ARMword newmode)
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{
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unsigned i;
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ARMword oldbank;
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ARMword newbank;
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oldbank = ModeToBank (oldmode);
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newbank = state->Bank = ModeToBank (newmode);
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/* Do we really need to do it? */
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if (oldbank != newbank)
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{
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/* Save away the old registers. */
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switch (oldbank)
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{
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case USERBANK:
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case IRQBANK:
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case SVCBANK:
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case ABORTBANK:
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case UNDEFBANK:
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if (newbank == FIQBANK)
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for (i = 8; i < 13; i++)
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state->RegBank[USERBANK][i] = state->Reg[i];
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state->RegBank[oldbank][13] = state->Reg[13];
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state->RegBank[oldbank][14] = state->Reg[14];
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break;
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case FIQBANK:
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for (i = 8; i < 15; i++)
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state->RegBank[FIQBANK][i] = state->Reg[i];
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break;
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case DUMMYBANK:
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for (i = 8; i < 15; i++)
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state->RegBank[DUMMYBANK][i] = 0;
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break;
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default:
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abort ();
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}
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/* Restore the new registers. */
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switch (newbank)
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{
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case USERBANK:
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case IRQBANK:
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case SVCBANK:
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case ABORTBANK:
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case UNDEFBANK:
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if (oldbank == FIQBANK)
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for (i = 8; i < 13; i++)
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state->Reg[i] = state->RegBank[USERBANK][i];
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state->Reg[13] = state->RegBank[newbank][13];
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state->Reg[14] = state->RegBank[newbank][14];
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break;
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case FIQBANK:
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for (i = 8; i < 15; i++)
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state->Reg[i] = state->RegBank[FIQBANK][i];
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break;
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case DUMMYBANK:
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for (i = 8; i < 15; i++)
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state->Reg[i] = 0;
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break;
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default:
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abort ();
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}
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}
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return newmode;
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}
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/* Given a processor mode, this routine returns the
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register bank that will be accessed in that mode. */
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static ARMword
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ModeToBank (ARMword mode)
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{
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static ARMword bankofmode[] =
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{
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USERBANK, FIQBANK, IRQBANK, SVCBANK,
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DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
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DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
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DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
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USERBANK, FIQBANK, IRQBANK, SVCBANK,
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DUMMYBANK, DUMMYBANK, DUMMYBANK, ABORTBANK,
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DUMMYBANK, DUMMYBANK, DUMMYBANK, UNDEFBANK,
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DUMMYBANK, DUMMYBANK, DUMMYBANK, SYSTEMBANK
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};
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if (mode >= (sizeof (bankofmode) / sizeof (bankofmode[0])))
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return DUMMYBANK;
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return bankofmode[mode];
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}
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/* Returns the register number of the nth register in a reg list. */
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unsigned
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ARMul_NthReg (ARMword instr, unsigned number)
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{
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unsigned bit, upto;
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for (bit = 0, upto = 0; upto <= number; bit ++)
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if (BIT (bit))
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upto ++;
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return (bit - 1);
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}
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/* Assigns the N and Z flags depending on the value of result. */
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void
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ARMul_NegZero (ARMul_State * state, ARMword result)
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{
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if (NEG (result))
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{
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SETN;
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CLEARZ;
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}
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else if (result == 0)
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{
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CLEARN;
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SETZ;
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}
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else
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{
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CLEARN;
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CLEARZ;
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}
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}
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/* Compute whether an addition of A and B, giving RESULT, overflowed. */
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int
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AddOverflow (ARMword a, ARMword b, ARMword result)
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{
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return ((NEG (a) && NEG (b) && POS (result))
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|| (POS (a) && POS (b) && NEG (result)));
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}
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/* Compute whether a subtraction of A and B, giving RESULT, overflowed. */
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int
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SubOverflow (ARMword a, ARMword b, ARMword result)
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{
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return ((NEG (a) && POS (b) && POS (result))
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|| (POS (a) && NEG (b) && NEG (result)));
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}
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/* Assigns the C flag after an addition of a and b to give result. */
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void
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ARMul_AddCarry (ARMul_State * state, ARMword a, ARMword b, ARMword result)
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{
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ASSIGNC ((NEG (a) && NEG (b)) ||
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(NEG (a) && POS (result)) || (NEG (b) && POS (result)));
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}
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/* Assigns the V flag after an addition of a and b to give result. */
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void
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ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result)
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{
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ASSIGNV (AddOverflow (a, b, result));
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}
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/* Assigns the C flag after an subtraction of a and b to give result. */
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void
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ARMul_SubCarry (ARMul_State * state, ARMword a, ARMword b, ARMword result)
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{
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ASSIGNC ((NEG (a) && POS (b)) ||
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(NEG (a) && POS (result)) || (POS (b) && POS (result)));
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}
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/* Assigns the V flag after an subtraction of a and b to give result. */
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void
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ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result)
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{
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ASSIGNV (SubOverflow (a, b, result));
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}
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static void
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handle_VFP_xfer (ARMul_State * state, ARMword instr)
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{
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if (TOPBITS (28) == NV)
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{
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fprintf (stderr, "SIM: UNDEFINED VFP instruction\n");
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return;
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}
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if (BITS (25, 27) != 0x6)
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{
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fprintf (stderr, "SIM: ISE: VFP handler called incorrectly\n");
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return;
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}
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switch (BITS (20, 24))
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{
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case 0x04:
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case 0x05:
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{
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/* VMOV double precision to/from two ARM registers. */
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int vm = BITS (0, 3);
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int rt1 = BITS (12, 15);
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int rt2 = BITS (16, 19);
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/* FIXME: UNPREDICTABLE if rt1 == 15 or rt2 == 15. */
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if (BIT (20))
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{
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/* Transfer to ARM. */
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/* FIXME: UPPREDICTABLE if rt1 == rt2. */
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state->Reg[rt1] = VFP_dword (vm) & 0xffffffff;
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state->Reg[rt2] = VFP_dword (vm) >> 32;
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}
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else
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{
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VFP_dword (vm) = state->Reg[rt2];
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VFP_dword (vm) <<= 32;
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VFP_dword (vm) |= (state->Reg[rt1] & 0xffffffff);
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}
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return;
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}
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case 0x08:
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case 0x0A:
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case 0x0C:
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case 0x0E:
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{
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/* VSTM with PUW=011 or PUW=010. */
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int n = BITS (16, 19);
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int imm8 = BITS (0, 7);
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ARMword address = state->Reg[n];
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if (BIT (21))
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state->Reg[n] = address + (imm8 << 2);
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if (BIT (8))
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{
|
|
int src = (BIT (22) << 4) | BITS (12, 15);
|
|
imm8 >>= 1;
|
|
while (imm8--)
|
|
{
|
|
if (state->bigendSig)
|
|
{
|
|
ARMul_StoreWordN (state, address, VFP_dword (src) >> 32);
|
|
ARMul_StoreWordN (state, address + 4, VFP_dword (src));
|
|
}
|
|
else
|
|
{
|
|
ARMul_StoreWordN (state, address, VFP_dword (src));
|
|
ARMul_StoreWordN (state, address + 4, VFP_dword (src) >> 32);
|
|
}
|
|
address += 8;
|
|
src += 1;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
int src = (BITS (12, 15) << 1) | BIT (22);
|
|
while (imm8--)
|
|
{
|
|
ARMul_StoreWordN (state, address, VFP_uword (src));
|
|
address += 4;
|
|
src += 1;
|
|
}
|
|
}
|
|
}
|
|
return;
|
|
|
|
case 0x10:
|
|
case 0x14:
|
|
case 0x18:
|
|
case 0x1C:
|
|
{
|
|
/* VSTR */
|
|
ARMword imm32 = BITS (0, 7) << 2;
|
|
int base = state->Reg[LHSReg];
|
|
ARMword address;
|
|
int dest;
|
|
|
|
if (LHSReg == 15)
|
|
base = (base + 3) & ~3;
|
|
|
|
address = base + (BIT (23) ? imm32 : - imm32);
|
|
|
|
if (CPNum == 10)
|
|
{
|
|
dest = (DESTReg << 1) + BIT (22);
|
|
|
|
ARMul_StoreWordN (state, address, VFP_uword (dest));
|
|
}
|
|
else
|
|
{
|
|
dest = (BIT (22) << 4) + DESTReg;
|
|
|
|
if (state->bigendSig)
|
|
{
|
|
ARMul_StoreWordN (state, address, VFP_dword (dest) >> 32);
|
|
ARMul_StoreWordN (state, address + 4, VFP_dword (dest));
|
|
}
|
|
else
|
|
{
|
|
ARMul_StoreWordN (state, address, VFP_dword (dest));
|
|
ARMul_StoreWordN (state, address + 4, VFP_dword (dest) >> 32);
|
|
}
|
|
}
|
|
}
|
|
return;
|
|
|
|
case 0x12:
|
|
case 0x16:
|
|
if (BITS (16, 19) == 13)
|
|
{
|
|
/* VPUSH */
|
|
ARMword address = state->Reg[13] - (BITS (0, 7) << 2);
|
|
state->Reg[13] = address;
|
|
|
|
if (BIT (8))
|
|
{
|
|
int dreg = (BIT (22) << 4) | BITS (12, 15);
|
|
int num = BITS (0, 7) >> 1;
|
|
while (num--)
|
|
{
|
|
if (state->bigendSig)
|
|
{
|
|
ARMul_StoreWordN (state, address, VFP_dword (dreg) >> 32);
|
|
ARMul_StoreWordN (state, address + 4, VFP_dword (dreg));
|
|
}
|
|
else
|
|
{
|
|
ARMul_StoreWordN (state, address, VFP_dword (dreg));
|
|
ARMul_StoreWordN (state, address + 4, VFP_dword (dreg) >> 32);
|
|
}
|
|
address += 8;
|
|
dreg += 1;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
int sreg = (BITS (12, 15) << 1) | BIT (22);
|
|
int num = BITS (0, 7);
|
|
while (num--)
|
|
{
|
|
ARMul_StoreWordN (state, address, VFP_uword (sreg));
|
|
address += 4;
|
|
sreg += 1;
|
|
}
|
|
}
|
|
}
|
|
else if (BITS (9, 11) != 0x5)
|
|
break;
|
|
else
|
|
{
|
|
/* VSTM PUW=101 */
|
|
int n = BITS (16, 19);
|
|
int imm8 = BITS (0, 7);
|
|
ARMword address = state->Reg[n] - (imm8 << 2);
|
|
state->Reg[n] = address;
|
|
|
|
if (BIT (8))
|
|
{
|
|
int src = (BIT (22) << 4) | BITS (12, 15);
|
|
|
|
imm8 >>= 1;
|
|
while (imm8--)
|
|
{
|
|
if (state->bigendSig)
|
|
{
|
|
ARMul_StoreWordN (state, address, VFP_dword (src) >> 32);
|
|
ARMul_StoreWordN (state, address + 4, VFP_dword (src));
|
|
}
|
|
else
|
|
{
|
|
ARMul_StoreWordN (state, address, VFP_dword (src));
|
|
ARMul_StoreWordN (state, address + 4, VFP_dword (src) >> 32);
|
|
}
|
|
address += 8;
|
|
src += 1;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
int src = (BITS (12, 15) << 1) | BIT (22);
|
|
|
|
while (imm8--)
|
|
{
|
|
ARMul_StoreWordN (state, address, VFP_uword (src));
|
|
address += 4;
|
|
src += 1;
|
|
}
|
|
}
|
|
}
|
|
return;
|
|
|
|
case 0x13:
|
|
case 0x17:
|
|
/* VLDM PUW=101 */
|
|
case 0x09:
|
|
case 0x0D:
|
|
/* VLDM PUW=010 */
|
|
{
|
|
int n = BITS (16, 19);
|
|
int imm8 = BITS (0, 7);
|
|
|
|
ARMword address = state->Reg[n];
|
|
if (BIT (23) == 0)
|
|
address -= imm8 << 2;
|
|
if (BIT (21))
|
|
state->Reg[n] = BIT (23) ? address + (imm8 << 2) : address;
|
|
|
|
if (BIT (8))
|
|
{
|
|
int dest = (BIT (22) << 4) | BITS (12, 15);
|
|
imm8 >>= 1;
|
|
while (imm8--)
|
|
{
|
|
if (state->bigendSig)
|
|
{
|
|
VFP_dword (dest) = ARMul_LoadWordN (state, address);
|
|
VFP_dword (dest) <<= 32;
|
|
VFP_dword (dest) |= ARMul_LoadWordN (state, address + 4);
|
|
}
|
|
else
|
|
{
|
|
VFP_dword (dest) = ARMul_LoadWordN (state, address + 4);
|
|
VFP_dword (dest) <<= 32;
|
|
VFP_dword (dest) |= ARMul_LoadWordN (state, address);
|
|
}
|
|
|
|
if (trace)
|
|
fprintf (stderr, " VFP: VLDM: D%d = %g\n", dest, VFP_dval (dest));
|
|
|
|
address += 8;
|
|
dest += 1;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
int dest = (BITS (12, 15) << 1) | BIT (22);
|
|
|
|
while (imm8--)
|
|
{
|
|
VFP_uword (dest) = ARMul_LoadWordN (state, address);
|
|
address += 4;
|
|
dest += 1;
|
|
}
|
|
}
|
|
}
|
|
return;
|
|
|
|
case 0x0B:
|
|
case 0x0F:
|
|
if (BITS (16, 19) == 13)
|
|
{
|
|
/* VPOP */
|
|
ARMword address = state->Reg[13];
|
|
state->Reg[13] = address + (BITS (0, 7) << 2);
|
|
|
|
if (BIT (8))
|
|
{
|
|
int dest = (BIT (22) << 4) | BITS (12, 15);
|
|
int num = BITS (0, 7) >> 1;
|
|
|
|
while (num--)
|
|
{
|
|
if (state->bigendSig)
|
|
{
|
|
VFP_dword (dest) = ARMul_LoadWordN (state, address);
|
|
VFP_dword (dest) <<= 32;
|
|
VFP_dword (dest) |= ARMul_LoadWordN (state, address + 4);
|
|
}
|
|
else
|
|
{
|
|
VFP_dword (dest) = ARMul_LoadWordN (state, address + 4);
|
|
VFP_dword (dest) <<= 32;
|
|
VFP_dword (dest) |= ARMul_LoadWordN (state, address);
|
|
}
|
|
|
|
if (trace)
|
|
fprintf (stderr, " VFP: VPOP: D%d = %g\n", dest, VFP_dval (dest));
|
|
|
|
address += 8;
|
|
dest += 1;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
int sreg = (BITS (12, 15) << 1) | BIT (22);
|
|
int num = BITS (0, 7);
|
|
|
|
while (num--)
|
|
{
|
|
VFP_uword (sreg) = ARMul_LoadWordN (state, address);
|
|
address += 4;
|
|
sreg += 1;
|
|
}
|
|
}
|
|
}
|
|
else if (BITS (9, 11) != 0x5)
|
|
break;
|
|
else
|
|
{
|
|
/* VLDM PUW=011 */
|
|
int n = BITS (16, 19);
|
|
int imm8 = BITS (0, 7);
|
|
ARMword address = state->Reg[n];
|
|
state->Reg[n] += imm8 << 2;
|
|
|
|
if (BIT (8))
|
|
{
|
|
int dest = (BIT (22) << 4) | BITS (12, 15);
|
|
|
|
imm8 >>= 1;
|
|
while (imm8--)
|
|
{
|
|
if (state->bigendSig)
|
|
{
|
|
VFP_dword (dest) = ARMul_LoadWordN (state, address);
|
|
VFP_dword (dest) <<= 32;
|
|
VFP_dword (dest) |= ARMul_LoadWordN (state, address + 4);
|
|
}
|
|
else
|
|
{
|
|
VFP_dword (dest) = ARMul_LoadWordN (state, address + 4);
|
|
VFP_dword (dest) <<= 32;
|
|
VFP_dword (dest) |= ARMul_LoadWordN (state, address);
|
|
}
|
|
|
|
if (trace)
|
|
fprintf (stderr, " VFP: VLDM: D%d = %g\n", dest, VFP_dval (dest));
|
|
|
|
address += 8;
|
|
dest += 1;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
int dest = (BITS (12, 15) << 1) | BIT (22);
|
|
while (imm8--)
|
|
{
|
|
VFP_uword (dest) = ARMul_LoadWordN (state, address);
|
|
address += 4;
|
|
dest += 1;
|
|
}
|
|
}
|
|
}
|
|
return;
|
|
|
|
case 0x11:
|
|
case 0x15:
|
|
case 0x19:
|
|
case 0x1D:
|
|
{
|
|
/* VLDR */
|
|
ARMword imm32 = BITS (0, 7) << 2;
|
|
int base = state->Reg[LHSReg];
|
|
ARMword address;
|
|
int dest;
|
|
|
|
if (LHSReg == 15)
|
|
base = (base + 3) & ~3;
|
|
|
|
address = base + (BIT (23) ? imm32 : - imm32);
|
|
|
|
if (CPNum == 10)
|
|
{
|
|
dest = (DESTReg << 1) + BIT (22);
|
|
|
|
VFP_uword (dest) = ARMul_LoadWordN (state, address);
|
|
}
|
|
else
|
|
{
|
|
dest = (BIT (22) << 4) + DESTReg;
|
|
|
|
if (state->bigendSig)
|
|
{
|
|
VFP_dword (dest) = ARMul_LoadWordN (state, address);
|
|
VFP_dword (dest) <<= 32;
|
|
VFP_dword (dest) |= ARMul_LoadWordN (state, address + 4);
|
|
}
|
|
else
|
|
{
|
|
VFP_dword (dest) = ARMul_LoadWordN (state, address + 4);
|
|
VFP_dword (dest) <<= 32;
|
|
VFP_dword (dest) |= ARMul_LoadWordN (state, address);
|
|
}
|
|
|
|
if (trace)
|
|
fprintf (stderr, " VFP: VLDR: D%d = %g\n", dest, VFP_dval (dest));
|
|
}
|
|
}
|
|
return;
|
|
}
|
|
|
|
fprintf (stderr, "SIM: VFP: Unimplemented: %0x\n", BITS (20, 24));
|
|
}
|
|
|
|
/* This function does the work of generating the addresses used in an
|
|
LDC instruction. The code here is always post-indexed, it's up to the
|
|
caller to get the input address correct and to handle base register
|
|
modification. It also handles the Busy-Waiting. */
|
|
|
|
void
|
|
ARMul_LDC (ARMul_State * state, ARMword instr, ARMword address)
|
|
{
|
|
unsigned cpab;
|
|
ARMword data;
|
|
|
|
if (CPNum == 10 || CPNum == 11)
|
|
{
|
|
handle_VFP_xfer (state, instr);
|
|
return;
|
|
}
|
|
|
|
UNDEF_LSCPCBaseWb;
|
|
|
|
if (! CP_ACCESS_ALLOWED (state, CPNum))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
return;
|
|
}
|
|
|
|
if (ADDREXCEPT (address))
|
|
INTERNALABORT (address);
|
|
|
|
cpab = (state->LDC[CPNum]) (state, ARMul_FIRST, instr, 0);
|
|
while (cpab == ARMul_BUSY)
|
|
{
|
|
ARMul_Icycles (state, 1, 0);
|
|
|
|
if (IntPending (state))
|
|
{
|
|
cpab = (state->LDC[CPNum]) (state, ARMul_INTERRUPT, instr, 0);
|
|
return;
|
|
}
|
|
else
|
|
cpab = (state->LDC[CPNum]) (state, ARMul_BUSY, instr, 0);
|
|
}
|
|
if (cpab == ARMul_CANT)
|
|
{
|
|
CPTAKEABORT;
|
|
return;
|
|
}
|
|
|
|
cpab = (state->LDC[CPNum]) (state, ARMul_TRANSFER, instr, 0);
|
|
data = ARMul_LoadWordN (state, address);
|
|
BUSUSEDINCPCN;
|
|
|
|
if (BIT (21))
|
|
LSBase = state->Base;
|
|
cpab = (state->LDC[CPNum]) (state, ARMul_DATA, instr, data);
|
|
|
|
while (cpab == ARMul_INC)
|
|
{
|
|
address += 4;
|
|
data = ARMul_LoadWordN (state, address);
|
|
cpab = (state->LDC[CPNum]) (state, ARMul_DATA, instr, data);
|
|
}
|
|
|
|
if (state->abortSig || state->Aborted)
|
|
TAKEABORT;
|
|
}
|
|
|
|
/* This function does the work of generating the addresses used in an
|
|
STC instruction. The code here is always post-indexed, it's up to the
|
|
caller to get the input address correct and to handle base register
|
|
modification. It also handles the Busy-Waiting. */
|
|
|
|
void
|
|
ARMul_STC (ARMul_State * state, ARMword instr, ARMword address)
|
|
{
|
|
unsigned cpab;
|
|
ARMword data;
|
|
|
|
if (CPNum == 10 || CPNum == 11)
|
|
{
|
|
handle_VFP_xfer (state, instr);
|
|
return;
|
|
}
|
|
|
|
UNDEF_LSCPCBaseWb;
|
|
|
|
if (! CP_ACCESS_ALLOWED (state, CPNum))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
return;
|
|
}
|
|
|
|
if (ADDREXCEPT (address) || VECTORACCESS (address))
|
|
INTERNALABORT (address);
|
|
|
|
cpab = (state->STC[CPNum]) (state, ARMul_FIRST, instr, &data);
|
|
while (cpab == ARMul_BUSY)
|
|
{
|
|
ARMul_Icycles (state, 1, 0);
|
|
if (IntPending (state))
|
|
{
|
|
cpab = (state->STC[CPNum]) (state, ARMul_INTERRUPT, instr, 0);
|
|
return;
|
|
}
|
|
else
|
|
cpab = (state->STC[CPNum]) (state, ARMul_BUSY, instr, &data);
|
|
}
|
|
|
|
if (cpab == ARMul_CANT)
|
|
{
|
|
CPTAKEABORT;
|
|
return;
|
|
}
|
|
#ifndef MODE32
|
|
if (ADDREXCEPT (address) || VECTORACCESS (address))
|
|
INTERNALABORT (address);
|
|
#endif
|
|
BUSUSEDINCPCN;
|
|
if (BIT (21))
|
|
LSBase = state->Base;
|
|
cpab = (state->STC[CPNum]) (state, ARMul_DATA, instr, &data);
|
|
ARMul_StoreWordN (state, address, data);
|
|
|
|
while (cpab == ARMul_INC)
|
|
{
|
|
address += 4;
|
|
cpab = (state->STC[CPNum]) (state, ARMul_DATA, instr, &data);
|
|
ARMul_StoreWordN (state, address, data);
|
|
}
|
|
|
|
if (state->abortSig || state->Aborted)
|
|
TAKEABORT;
|
|
}
|
|
|
|
/* This function does the Busy-Waiting for an MCR instruction. */
|
|
|
|
void
|
|
ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source)
|
|
{
|
|
unsigned cpab;
|
|
|
|
if (! CP_ACCESS_ALLOWED (state, CPNum))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
return;
|
|
}
|
|
|
|
cpab = (state->MCR[CPNum]) (state, ARMul_FIRST, instr, source);
|
|
|
|
while (cpab == ARMul_BUSY)
|
|
{
|
|
ARMul_Icycles (state, 1, 0);
|
|
|
|
if (IntPending (state))
|
|
{
|
|
cpab = (state->MCR[CPNum]) (state, ARMul_INTERRUPT, instr, 0);
|
|
return;
|
|
}
|
|
else
|
|
cpab = (state->MCR[CPNum]) (state, ARMul_BUSY, instr, source);
|
|
}
|
|
|
|
if (cpab == ARMul_CANT)
|
|
ARMul_Abort (state, ARMul_UndefinedInstrV);
|
|
else
|
|
{
|
|
BUSUSEDINCPCN;
|
|
ARMul_Ccycles (state, 1, 0);
|
|
}
|
|
}
|
|
|
|
/* This function does the Busy-Waiting for an MRC instruction. */
|
|
|
|
ARMword
|
|
ARMul_MRC (ARMul_State * state, ARMword instr)
|
|
{
|
|
unsigned cpab;
|
|
ARMword result = 0;
|
|
|
|
if (! CP_ACCESS_ALLOWED (state, CPNum))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
return result;
|
|
}
|
|
|
|
cpab = (state->MRC[CPNum]) (state, ARMul_FIRST, instr, &result);
|
|
while (cpab == ARMul_BUSY)
|
|
{
|
|
ARMul_Icycles (state, 1, 0);
|
|
if (IntPending (state))
|
|
{
|
|
cpab = (state->MRC[CPNum]) (state, ARMul_INTERRUPT, instr, 0);
|
|
return (0);
|
|
}
|
|
else
|
|
cpab = (state->MRC[CPNum]) (state, ARMul_BUSY, instr, &result);
|
|
}
|
|
if (cpab == ARMul_CANT)
|
|
{
|
|
ARMul_Abort (state, ARMul_UndefinedInstrV);
|
|
/* Parent will destroy the flags otherwise. */
|
|
result = ECC;
|
|
}
|
|
else
|
|
{
|
|
BUSUSEDINCPCN;
|
|
ARMul_Ccycles (state, 1, 0);
|
|
ARMul_Icycles (state, 1, 0);
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
static void
|
|
handle_VFP_op (ARMul_State * state, ARMword instr)
|
|
{
|
|
int dest;
|
|
int srcN;
|
|
int srcM;
|
|
|
|
if (BITS (9, 11) != 0x5 || BIT (4) != 0)
|
|
{
|
|
fprintf (stderr, "SIM: VFP: Unimplemented: Float op: %08x\n", BITS (0,31));
|
|
return;
|
|
}
|
|
|
|
if (BIT (8))
|
|
{
|
|
dest = BITS(12,15) + (BIT (22) << 4);
|
|
srcN = LHSReg + (BIT (7) << 4);
|
|
srcM = BITS (0,3) + (BIT (5) << 4);
|
|
}
|
|
else
|
|
{
|
|
dest = (BITS(12,15) << 1) + BIT (22);
|
|
srcN = (LHSReg << 1) + BIT (7);
|
|
srcM = (BITS (0,3) << 1) + BIT (5);
|
|
}
|
|
|
|
switch (BITS (20, 27))
|
|
{
|
|
case 0xE0:
|
|
case 0xE4:
|
|
/* VMLA VMLS */
|
|
if (BIT (8))
|
|
{
|
|
ARMdval val = VFP_dval (srcN) * VFP_dval (srcM);
|
|
|
|
if (BIT (6))
|
|
{
|
|
if (trace)
|
|
fprintf (stderr, " VFP: VMLS: %g = %g - %g * %g\n",
|
|
VFP_dval (dest) - val,
|
|
VFP_dval (dest), VFP_dval (srcN), VFP_dval (srcM));
|
|
VFP_dval (dest) -= val;
|
|
}
|
|
else
|
|
{
|
|
if (trace)
|
|
fprintf (stderr, " VFP: VMLA: %g = %g + %g * %g\n",
|
|
VFP_dval (dest) + val,
|
|
VFP_dval (dest), VFP_dval (srcN), VFP_dval (srcM));
|
|
VFP_dval (dest) += val;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
ARMfval val = VFP_fval (srcN) * VFP_fval (srcM);
|
|
|
|
if (BIT (6))
|
|
{
|
|
if (trace)
|
|
fprintf (stderr, " VFP: VMLS: %g = %g - %g * %g\n",
|
|
VFP_fval (dest) - val,
|
|
VFP_fval (dest), VFP_fval (srcN), VFP_fval (srcM));
|
|
VFP_fval (dest) -= val;
|
|
}
|
|
else
|
|
{
|
|
if (trace)
|
|
fprintf (stderr, " VFP: VMLA: %g = %g + %g * %g\n",
|
|
VFP_fval (dest) + val,
|
|
VFP_fval (dest), VFP_fval (srcN), VFP_fval (srcM));
|
|
VFP_fval (dest) += val;
|
|
}
|
|
}
|
|
return;
|
|
|
|
case 0xE1:
|
|
case 0xE5:
|
|
if (BIT (8))
|
|
{
|
|
ARMdval product = VFP_dval (srcN) * VFP_dval (srcM);
|
|
|
|
if (BIT (6))
|
|
{
|
|
/* VNMLA */
|
|
if (trace)
|
|
fprintf (stderr, " VFP: VNMLA: %g = -(%g + (%g * %g))\n",
|
|
-(VFP_dval (dest) + product),
|
|
VFP_dval (dest), VFP_dval (srcN), VFP_dval (srcM));
|
|
VFP_dval (dest) = -(product + VFP_dval (dest));
|
|
}
|
|
else
|
|
{
|
|
/* VNMLS */
|
|
if (trace)
|
|
fprintf (stderr, " VFP: VNMLS: %g = -(%g + (%g * %g))\n",
|
|
-(VFP_dval (dest) + product),
|
|
VFP_dval (dest), VFP_dval (srcN), VFP_dval (srcM));
|
|
VFP_dval (dest) = product - VFP_dval (dest);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
ARMfval product = VFP_fval (srcN) * VFP_fval (srcM);
|
|
|
|
if (BIT (6))
|
|
/* VNMLA */
|
|
VFP_fval (dest) = -(product + VFP_fval (dest));
|
|
else
|
|
/* VNMLS */
|
|
VFP_fval (dest) = product - VFP_fval (dest);
|
|
}
|
|
return;
|
|
|
|
case 0xE2:
|
|
case 0xE6:
|
|
if (BIT (8))
|
|
{
|
|
ARMdval product = VFP_dval (srcN) * VFP_dval (srcM);
|
|
|
|
if (BIT (6))
|
|
{
|
|
if (trace)
|
|
fprintf (stderr, " VFP: VMUL: %g = %g * %g\n",
|
|
- product, VFP_dval (srcN), VFP_dval (srcM));
|
|
/* VNMUL */
|
|
VFP_dval (dest) = - product;
|
|
}
|
|
else
|
|
{
|
|
if (trace)
|
|
fprintf (stderr, " VFP: VMUL: %g = %g * %g\n",
|
|
product, VFP_dval (srcN), VFP_dval (srcM));
|
|
/* VMUL */
|
|
VFP_dval (dest) = product;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
ARMfval product = VFP_fval (srcN) * VFP_fval (srcM);
|
|
|
|
if (BIT (6))
|
|
{
|
|
if (trace)
|
|
fprintf (stderr, " VFP: VNMUL: %g = %g * %g\n",
|
|
- product, VFP_fval (srcN), VFP_fval (srcM));
|
|
|
|
VFP_fval (dest) = - product;
|
|
}
|
|
else
|
|
{
|
|
if (trace)
|
|
fprintf (stderr, " VFP: VMUL: %g = %g * %g\n",
|
|
product, VFP_fval (srcN), VFP_fval (srcM));
|
|
|
|
VFP_fval (dest) = product;
|
|
}
|
|
}
|
|
return;
|
|
|
|
case 0xE3:
|
|
case 0xE7:
|
|
if (BIT (6) == 0)
|
|
{
|
|
/* VADD */
|
|
if (BIT(8))
|
|
{
|
|
if (trace)
|
|
fprintf (stderr, " VFP: VADD %g = %g + %g\n",
|
|
VFP_dval (srcN) + VFP_dval (srcM),
|
|
VFP_dval (srcN),
|
|
VFP_dval (srcM));
|
|
VFP_dval (dest) = VFP_dval (srcN) + VFP_dval (srcM);
|
|
}
|
|
else
|
|
VFP_fval (dest) = VFP_fval (srcN) + VFP_fval (srcM);
|
|
|
|
}
|
|
else
|
|
{
|
|
/* VSUB */
|
|
if (BIT(8))
|
|
{
|
|
if (trace)
|
|
fprintf (stderr, " VFP: VSUB %g = %g - %g\n",
|
|
VFP_dval (srcN) - VFP_dval (srcM),
|
|
VFP_dval (srcN),
|
|
VFP_dval (srcM));
|
|
VFP_dval (dest) = VFP_dval (srcN) - VFP_dval (srcM);
|
|
}
|
|
else
|
|
VFP_fval (dest) = VFP_fval (srcN) - VFP_fval (srcM);
|
|
}
|
|
return;
|
|
|
|
case 0xE8:
|
|
case 0xEC:
|
|
if (BIT (6) == 1)
|
|
break;
|
|
|
|
/* VDIV */
|
|
if (BIT (8))
|
|
{
|
|
ARMdval res = VFP_dval (srcN) / VFP_dval (srcM);
|
|
if (trace)
|
|
fprintf (stderr, " VFP: VDIV (64bit): %g = %g / %g\n",
|
|
res, VFP_dval (srcN), VFP_dval (srcM));
|
|
VFP_dval (dest) = res;
|
|
}
|
|
else
|
|
{
|
|
if (trace)
|
|
fprintf (stderr, " VFP: VDIV: %g = %g / %g\n",
|
|
VFP_fval (srcN) / VFP_fval (srcM),
|
|
VFP_fval (srcN), VFP_fval (srcM));
|
|
|
|
VFP_fval (dest) = VFP_fval (srcN) / VFP_fval (srcM);
|
|
}
|
|
return;
|
|
|
|
case 0xEB:
|
|
case 0xEF:
|
|
if (BIT (6) != 1)
|
|
break;
|
|
|
|
switch (BITS (16, 19))
|
|
{
|
|
case 0x0:
|
|
if (BIT (7) == 0)
|
|
{
|
|
if (BIT (8))
|
|
{
|
|
/* VMOV.F64 <Dd>, <Dm>. */
|
|
VFP_dval (dest) = VFP_dval (srcM);
|
|
if (trace)
|
|
fprintf (stderr, " VFP: VMOV d%d, d%d: %g\n", dest, srcM, VFP_dval (srcM));
|
|
}
|
|
else
|
|
{
|
|
/* VMOV.F32 <Sd>, <Sm>. */
|
|
VFP_fval (dest) = VFP_fval (srcM);
|
|
if (trace)
|
|
fprintf (stderr, " VFP: VMOV s%d, s%d: %g\n", dest, srcM, VFP_fval (srcM));
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* VABS */
|
|
if (BIT (8))
|
|
{
|
|
ARMdval src = VFP_dval (srcM);
|
|
|
|
VFP_dval (dest) = fabs (src);
|
|
if (trace)
|
|
fprintf (stderr, " VFP: VABS (%g) = %g\n", src, VFP_dval (dest));
|
|
}
|
|
else
|
|
{
|
|
ARMfval src = VFP_fval (srcM);
|
|
|
|
VFP_fval (dest) = fabsf (src);
|
|
if (trace)
|
|
fprintf (stderr, " VFP: VABS (%g) = %g\n", src, VFP_fval (dest));
|
|
}
|
|
}
|
|
return;
|
|
|
|
case 0x1:
|
|
if (BIT (7) == 0)
|
|
{
|
|
/* VNEG */
|
|
if (BIT (8))
|
|
VFP_dval (dest) = - VFP_dval (srcM);
|
|
else
|
|
VFP_fval (dest) = - VFP_fval (srcM);
|
|
}
|
|
else
|
|
{
|
|
/* VSQRT */
|
|
if (BIT (8))
|
|
{
|
|
if (trace)
|
|
fprintf (stderr, " VFP: %g = root(%g)\n",
|
|
sqrt (VFP_dval (srcM)), VFP_dval (srcM));
|
|
|
|
VFP_dval (dest) = sqrt (VFP_dval (srcM));
|
|
}
|
|
else
|
|
{
|
|
if (trace)
|
|
fprintf (stderr, " VFP: %g = root(%g)\n",
|
|
sqrtf (VFP_fval (srcM)), VFP_fval (srcM));
|
|
|
|
VFP_fval (dest) = sqrtf (VFP_fval (srcM));
|
|
}
|
|
}
|
|
return;
|
|
|
|
case 0x4:
|
|
case 0x5:
|
|
/* VCMP, VCMPE */
|
|
if (BIT(8))
|
|
{
|
|
ARMdval res = VFP_dval (dest);
|
|
|
|
if (BIT (16) == 0)
|
|
{
|
|
ARMdval src = VFP_dval (srcM);
|
|
|
|
if (isinf (res) && isinf (src))
|
|
{
|
|
if (res > 0.0 && src > 0.0)
|
|
res = 0.0;
|
|
else if (res < 0.0 && src < 0.0)
|
|
res = 0.0;
|
|
/* else leave res alone. */
|
|
}
|
|
else
|
|
res -= src;
|
|
}
|
|
|
|
/* FIXME: Add handling of signalling NaNs and the E bit. */
|
|
|
|
state->FPSCR &= 0x0FFFFFFF;
|
|
if (res < 0.0)
|
|
state->FPSCR |= NBIT;
|
|
else
|
|
state->FPSCR |= CBIT;
|
|
if (res == 0.0)
|
|
state->FPSCR |= ZBIT;
|
|
if (isnan (res))
|
|
state->FPSCR |= VBIT;
|
|
|
|
if (trace)
|
|
fprintf (stderr, " VFP: VCMP (64bit) %g vs %g res %g, flags: %c%c%c%c\n",
|
|
VFP_dval (dest), BIT (16) ? 0.0 : VFP_dval (srcM), res,
|
|
state->FPSCR & NBIT ? 'N' : '-',
|
|
state->FPSCR & ZBIT ? 'Z' : '-',
|
|
state->FPSCR & CBIT ? 'C' : '-',
|
|
state->FPSCR & VBIT ? 'V' : '-');
|
|
}
|
|
else
|
|
{
|
|
ARMfval res = VFP_fval (dest);
|
|
|
|
if (BIT (16) == 0)
|
|
{
|
|
ARMfval src = VFP_fval (srcM);
|
|
|
|
if (isinf (res) && isinf (src))
|
|
{
|
|
if (res > 0.0 && src > 0.0)
|
|
res = 0.0;
|
|
else if (res < 0.0 && src < 0.0)
|
|
res = 0.0;
|
|
/* else leave res alone. */
|
|
}
|
|
else
|
|
res -= src;
|
|
}
|
|
|
|
/* FIXME: Add handling of signalling NaNs and the E bit. */
|
|
|
|
state->FPSCR &= 0x0FFFFFFF;
|
|
if (res < 0.0)
|
|
state->FPSCR |= NBIT;
|
|
else
|
|
state->FPSCR |= CBIT;
|
|
if (res == 0.0)
|
|
state->FPSCR |= ZBIT;
|
|
if (isnan (res))
|
|
state->FPSCR |= VBIT;
|
|
|
|
if (trace)
|
|
fprintf (stderr, " VFP: VCMP (32bit) %g vs %g res %g, flags: %c%c%c%c\n",
|
|
VFP_fval (dest), BIT (16) ? 0.0 : VFP_fval (srcM), res,
|
|
state->FPSCR & NBIT ? 'N' : '-',
|
|
state->FPSCR & ZBIT ? 'Z' : '-',
|
|
state->FPSCR & CBIT ? 'C' : '-',
|
|
state->FPSCR & VBIT ? 'V' : '-');
|
|
}
|
|
return;
|
|
|
|
case 0x7:
|
|
if (BIT (8))
|
|
{
|
|
dest = (DESTReg << 1) + BIT (22);
|
|
VFP_fval (dest) = VFP_dval (srcM);
|
|
}
|
|
else
|
|
{
|
|
dest = DESTReg + (BIT (22) << 4);
|
|
VFP_dval (dest) = VFP_fval (srcM);
|
|
}
|
|
return;
|
|
|
|
case 0x8:
|
|
case 0xC:
|
|
case 0xD:
|
|
/* VCVT integer <-> FP */
|
|
if (BIT (18))
|
|
{
|
|
/* To integer. */
|
|
if (BIT (8))
|
|
{
|
|
dest = (BITS(12,15) << 1) + BIT (22);
|
|
if (BIT (16))
|
|
VFP_sword (dest) = VFP_dval (srcM);
|
|
else
|
|
VFP_uword (dest) = VFP_dval (srcM);
|
|
}
|
|
else
|
|
{
|
|
if (BIT (16))
|
|
VFP_sword (dest) = VFP_fval (srcM);
|
|
else
|
|
VFP_uword (dest) = VFP_fval (srcM);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* From integer. */
|
|
if (BIT (8))
|
|
{
|
|
srcM = (BITS (0,3) << 1) + BIT (5);
|
|
if (BIT (7))
|
|
VFP_dval (dest) = VFP_sword (srcM);
|
|
else
|
|
VFP_dval (dest) = VFP_uword (srcM);
|
|
}
|
|
else
|
|
{
|
|
if (BIT (7))
|
|
VFP_fval (dest) = VFP_sword (srcM);
|
|
else
|
|
VFP_fval (dest) = VFP_uword (srcM);
|
|
}
|
|
}
|
|
return;
|
|
}
|
|
|
|
fprintf (stderr, "SIM: VFP: Unimplemented: Float op3: %03x\n", BITS (16,27));
|
|
return;
|
|
}
|
|
|
|
fprintf (stderr, "SIM: VFP: Unimplemented: Float op2: %02x\n", BITS (20, 27));
|
|
return;
|
|
}
|
|
|
|
/* This function does the Busy-Waiting for an CDP instruction. */
|
|
|
|
void
|
|
ARMul_CDP (ARMul_State * state, ARMword instr)
|
|
{
|
|
unsigned cpab;
|
|
|
|
if (CPNum == 10 || CPNum == 11)
|
|
{
|
|
handle_VFP_op (state, instr);
|
|
return;
|
|
}
|
|
|
|
if (! CP_ACCESS_ALLOWED (state, CPNum))
|
|
{
|
|
ARMul_UndefInstr (state, instr);
|
|
return;
|
|
}
|
|
|
|
cpab = (state->CDP[CPNum]) (state, ARMul_FIRST, instr);
|
|
while (cpab == ARMul_BUSY)
|
|
{
|
|
ARMul_Icycles (state, 1, 0);
|
|
if (IntPending (state))
|
|
{
|
|
cpab = (state->CDP[CPNum]) (state, ARMul_INTERRUPT, instr);
|
|
return;
|
|
}
|
|
else
|
|
cpab = (state->CDP[CPNum]) (state, ARMul_BUSY, instr);
|
|
}
|
|
if (cpab == ARMul_CANT)
|
|
ARMul_Abort (state, ARMul_UndefinedInstrV);
|
|
else
|
|
BUSUSEDN;
|
|
}
|
|
|
|
/* This function handles Undefined instructions, as CP isntruction. */
|
|
|
|
void
|
|
ARMul_UndefInstr (ARMul_State * state, ARMword instr ATTRIBUTE_UNUSED)
|
|
{
|
|
ARMul_Abort (state, ARMul_UndefinedInstrV);
|
|
}
|
|
|
|
/* Return TRUE if an interrupt is pending, FALSE otherwise. */
|
|
|
|
unsigned
|
|
IntPending (ARMul_State * state)
|
|
{
|
|
if (state->Exception)
|
|
{
|
|
/* Any exceptions. */
|
|
if (state->NresetSig == LOW)
|
|
{
|
|
ARMul_Abort (state, ARMul_ResetV);
|
|
return TRUE;
|
|
}
|
|
else if (!state->NfiqSig && !FFLAG)
|
|
{
|
|
ARMul_Abort (state, ARMul_FIQV);
|
|
return TRUE;
|
|
}
|
|
else if (!state->NirqSig && !IFLAG)
|
|
{
|
|
ARMul_Abort (state, ARMul_IRQV);
|
|
return TRUE;
|
|
}
|
|
}
|
|
|
|
return FALSE;
|
|
}
|
|
|
|
/* Align a word access to a non word boundary. */
|
|
|
|
ARMword
|
|
ARMul_Align (ARMul_State *state ATTRIBUTE_UNUSED, ARMword address, ARMword data)
|
|
{
|
|
/* This code assumes the address is really unaligned,
|
|
as a shift by 32 is undefined in C. */
|
|
|
|
address = (address & 3) << 3; /* Get the word address. */
|
|
return ((data >> address) | (data << (32 - address))); /* rot right */
|
|
}
|
|
|
|
/* This routine is used to call another routine after a certain number of
|
|
cycles have been executed. The first parameter is the number of cycles
|
|
delay before the function is called, the second argument is a pointer
|
|
to the function. A delay of zero doesn't work, just call the function. */
|
|
|
|
void
|
|
ARMul_ScheduleEvent (ARMul_State * state, unsigned long delay,
|
|
unsigned (*what) (ARMul_State *))
|
|
{
|
|
unsigned long when;
|
|
struct EventNode *event;
|
|
|
|
if (state->EventSet++ == 0)
|
|
state->Now = ARMul_Time (state);
|
|
when = (state->Now + delay) % EVENTLISTSIZE;
|
|
event = (struct EventNode *) malloc (sizeof (struct EventNode));
|
|
event->func = what;
|
|
event->next = *(state->EventPtr + when);
|
|
*(state->EventPtr + when) = event;
|
|
}
|
|
|
|
/* This routine is called at the beginning of
|
|
every cycle, to envoke scheduled events. */
|
|
|
|
void
|
|
ARMul_EnvokeEvent (ARMul_State * state)
|
|
{
|
|
static unsigned long then;
|
|
|
|
then = state->Now;
|
|
state->Now = ARMul_Time (state) % EVENTLISTSIZE;
|
|
if (then < state->Now)
|
|
/* Schedule events. */
|
|
EnvokeList (state, then, state->Now);
|
|
else if (then > state->Now)
|
|
{
|
|
/* Need to wrap around the list. */
|
|
EnvokeList (state, then, EVENTLISTSIZE - 1L);
|
|
EnvokeList (state, 0L, state->Now);
|
|
}
|
|
}
|
|
|
|
/* Envokes all the entries in a range. */
|
|
|
|
static void
|
|
EnvokeList (ARMul_State * state, unsigned long from, unsigned long to)
|
|
{
|
|
for (; from <= to; from++)
|
|
{
|
|
struct EventNode *anevent;
|
|
|
|
anevent = *(state->EventPtr + from);
|
|
while (anevent)
|
|
{
|
|
(anevent->func) (state);
|
|
state->EventSet--;
|
|
anevent = anevent->next;
|
|
}
|
|
*(state->EventPtr + from) = NULL;
|
|
}
|
|
}
|
|
|
|
/* This routine is returns the number of clock ticks since the last reset. */
|
|
|
|
unsigned long
|
|
ARMul_Time (ARMul_State * state)
|
|
{
|
|
return (state->NumScycles + state->NumNcycles +
|
|
state->NumIcycles + state->NumCcycles + state->NumFcycles);
|
|
}
|