# PKE tests for code coverage
#
#
#
# ---- STCYCL/CYCLE ----
#
# Test STCYCL instruction
0 0x0100fedc_00000000_00000000_00000000 0x00000000 PPPP
# Attempt erroneous write to CYCLE register
! 0x10003840 0x0000dead
# Read CYCLE register; confirm proper value
? 0x10003840 0x0000fedc 0xffffffff
# Read STAT register; confirm ER1 not set
? 0x10003800 0x00000000 0x00002000
#
#
# ---- OFFSET/OFST ----
#
# Test OFFSET instruction on PKE1
1 0x0200ffff_00000000_00000000_00000000 0x00000000 PPPP
# Attempt erroneous write to OFFSET register
! 0x10003cb0 0x0000dead
# Read OFST register; confirm proper 10-bit value
? 0x10003cb0 0x000003ff 0xffffffff
# Read STAT register; confirm DBF=0
? 0x10003c00 0x00000000 0x00000080
# Read DBF register; confirm DBF=0
? 0x10003cf0 0x00000000 0x00000001
# Read STAT register; confirm ER1 not set
? 0x10003c00 0x00000000 0x00002000
#
#
# ---- BASE/BASE ----
#
# Test BASE instruction on PKE1
1 0x0300ffff_00000000_00000000_00000000 0x00000000 PPPP
# Attempt erroneous write to BASE register
! 0x10003ca0 0x0000dead
# Read BASE register; confirm proper 10-bit value
? 0x10003ca0 0x000003ff 0xffffffff
# Read STAT register; confirm DBF=0
? 0x10003c00 0x00000000 0x00000080
# Read DBF register; confirm DBF=0
? 0x10003cf0 0x00000000 0x00000001
#
#
# ---- ITOP/ITOPS ----
#
# Test ITOP instruction
0 0x0400ffff_00000000_00000000_00000000 0x00000000 PPPP
# Attempt erroneous write to ITOPS register
! 0x10003890 0x0000dead
# Read ITOPS register; confirm proper 10-bit value
? 0x10003890 0x000003ff 0xffffffff
# Read STAT register; confirm ER1 not set
? 0x10003800 0x00000000 0x00002000
#
#
# ---- STMOD/MODE ----
#
# Test STMOD instruction
0 0x05000003_00000000_00000000_00000000 0x00000000 PPPP
# Attempt erroneous write to MODE register
! 0x10003850 0x0000dead
# Read MODE register; confirm proper value
? 0x10003850 0x00000003 0xffffffff
# Test STMOD instruction with junk upper bits
0 0x0500dad1_00000000_00000000_00000000 0x00000000 PPPP
# Read MODE register; confirm proper value
? 0x10003850 0x00000001 0xffffffff
# Read STAT register; confirm ER1 not set
? 0x10003800 0x00000000 0x00002000
#
#
# ---- STMARK/MARK ----
#
# Test MARK instruction
0 0x0700abcd_00000000_00000000_00000000 0x00000000 PPPP
# Read STAT register; confirm MRK bit set
? 0x10003800 0x00000040 0x00000040
# Read MARK register
? 0x10003830 0x0000abcd 0xffffffff
# Write MARK register
! 0x10003830 0x00001234
# Read STAT register; confirm MRK bit clear
? 0x10003800 0x00000000 0x00000040
# Read MARK register
? 0x10003830 0x00001234 0xffffffff
#
#
# ---- bad PKEcode/ER1, interrupts ----
#
# A bad PKEcode
1 0x00000000_00000000_00000000_08000000 0x00000000 PPPP
# should put PKE into stalled mode, not executing following PKENOPs
# Read STAT register; confirm ER1 bit set
? 0x10003c00 0x00002000 0x00002000
# Read CODE register; confirm PKE is stuck at bad code
? 0x10003c80 0x08000000 0xffffffff
# Reset PKE
! 0x10003c10 0x00000001
# Read STAT register; confirm ER1 no longer set
? 0x10003c00 0x00000000 0x00002000
# 
# Mask ME1 (ER1 stall) this time
! 0x10003c20 0x00000004
# A bad PKEcode with ER1 masked
1 0x00000000_00000000_00000000_08000000 0x00000000 PPPP
# should not put PKE into stalled mode, should execute following PKENOPs
# Read STAT register; confirm ER1 bit set
? 0x10003c00 0x00002000 0x00002000
# Read CODE register; confirm PKE went past bad code
? 0x10003c80 0x00000000 0xffffffff
# Reset PKE
! 0x10003c10 0x00000001
# Read STAT register; confirm ER1 no longer set
? 0x10003c00 0x00000000 0x00002000
#
#
# A good PKEcode (STMOD) with interrupt
1 0x00000000_00000000_00000000_85000000 0x00000000 PPPP
# should put PKE into stalled mode, not executing following PKENOPs
# Read STAT register; confirm PIS & INT bits set
? 0x10003c00 0x00000c00 0x00000c00
# Read CODE register; confirm PKE is stuck at bad code
? 0x10003c80 0x85000000 0xffffffff
# Resume PKE with STC
! 0x10003c10 0x00000008
# Read STAT register; confirm PIS & INT no longer set
? 0x10003c00 0x00000000 0x00000c00
# Read CODE register; confirm PKE executed trailing no-ops
? 0x10003c80 0x00000000 0xffffffff
#
#
# ---- STMASK/MASK ----
#
# Test STMASK instruction; leave operand out for now
0 0x20000000_00000000_00000000_00000000 0x00000000 PPPP
# Read STAT register; confirm PPS field set at WAIT
? 0x10003800 0x00000001 0x00000003
# Add operand for STMASK instruction
0 0x00000000_00000000_00000000_1234abcd 0x00000000 PPPP
# Erroneous write to MASK register
! 0x10003870 0x98765432
# Read MASK register
? 0x10003870 0x1234abcd 0xffffffff
# Read STAT register; confirm ER1 not set
? 0x10003800 0x00000000 0x00002000
#
#
# ---- DIRECT ----
#
# Test DIRECT instruction; leave operand out for now
1 0x50000001_00000000_00000000_00000000 0x00000000 PPPP
# Read STAT register; confirm PPS field set at WAIT
? 0x10003c00 0x00000001 0x00000003
# Supply operand - it's a bad GPUIF tag
1 0x00000000_00000000_00000000_00000000 0x00000000 ....
# Test DIRECT instruction with bad operand alignment
1 0x00000000_50000001_00000000_00000000 0x00000000 PPPP
# Read STAT register; confirm ER1 bit set
? 0x10003c00 0x00002000 0x00002000
# Reset PKE
! 0x10003c10 0x00000001
# Read STAT register; confirm ER1 no longer set
? 0x10003c00 0x00000000 0x00002000
# Test DIRECT instruction with bad operand alignment
1 0x00000000_00000000_50000001_00000000 0x00000000 PPPP
# Read STAT register; confirm ER1 bit set
? 0x10003c00 0x00002000 0x00002000
# Reset PKE
! 0x10003c10 0x00000001
# Read STAT register; confirm ER1 no longer set
? 0x10003c00 0x00000000 0x00002000
# Test DIRECT instruction with bad operand alignment
1 0x00000000_00000000_00000000_50000001 0x00000000 PPPP
# Read STAT register; confirm ER1 bit set
? 0x10003c00 0x00002000 0x00002000
# Reset PKE
! 0x10003c10 0x00000001
# Read STAT register; confirm ER1 no longer set
? 0x10003c00 0x00000000 0x00002000
#
#
# ---- MPG - PKE0 ----
#
# Test MPG instruction; leave operand out for now
0 0x4a080000_00000000_00000000_00000000 0x00000000 PPPP
# Read STAT register; confirm PPS field set at WAIT
? 0x10003800 0x00000001 0x00000003
# Supply operands - eight two junk VU instruction word-pairs with real source-addr's
0 0xdeadbeef_0bad0bad_beef0bad_2bad2bad 0x00000010 ....
0 0xabcdbeef_44332211_12987423_95555999 0x00000100 ....
0 0xdeadabcd_75577588_beef0bad_89abcdef 0x00001000 ....
0 0xa5a5a5a5_5aaa5533_01234567_77889900 0x00010000 ....
# Check that instructions were loaded properly
? 0x11000000 0x2bad2bad 0xffffffff
? 0x11000004 0xbeef0bad 0xffffffff
? 0x11000014 0x12987423 0xffffffff
? 0x11000028 0x75577588 0xffffffff
? 0x1100003c 0xa5a5a5a5 0xffffffff
# Check that source addresses were loaded properly
? 0x21000000 0x00000010 0xffffffff
? 0x21000004 0x00000010 0xffffffff
? 0x21000008 0x00000100 0xffffffff
? 0x2100000c 0x00000100 0xffffffff
? 0x21000010 0x00001000 0xffffffff
? 0x21000014 0x00001000 0xffffffff
? 0x21000018 0x00010000 0xffffffff
? 0x2100001c 0x00010000 0xffffffff
# Test MPG instruction with bad operand alignment
0 0x00000000_4a020000_00000000_00000000 0x00000000 PPPP
# Read STAT register; confirm ER1 bit set
? 0x10003800 0x00002000 0x00002000
# Reset PKE
! 0x10003810 0x00000001
# Read STAT register; confirm ER1 no longer set
? 0x10003800 0x00000000 0x00002000
# Test MPG instruction with good operand alignment
0 0x00000000_00000000_4a010000_00000000 0x00000000 ..PP
# Read STAT register; confirm ER1 bit not set
? 0x10003800 0x00000000 0x00002000
# Test MPG instruction with bad operand alignment
0 0x00000000_00000000_00000000_4a010000 0x00000000 PPPP
# Read STAT register; confirm ER1 bit set
? 0x10003800 0x00002000 0x00002000
# Reset PKE
! 0x10003810 0x00000001
# Read STAT register; confirm ER1 no longer set
? 0x10003800 0x00000000 0x00002000
#
#
# ---- MPG - PKE1 ----
#
# Test MPG instruction; leave operand out for now
1 0x4a080000_00000000_00000000_00000000 0x00000000 PPPP
# Read STAT register; confirm PPS field set at WAIT
? 0x10003c00 0x00000001 0x00000003
# Supply operands - eight two junk VU instruction word-pairs with real source-addr's
1 0xdeadbeef_0bad0bad_beef0bad_2bad2bad 0x00000010 ....
1 0xabcdbeef_44332211_12987423_95555999 0x00000100 ....
1 0xdeadabcd_75577588_beef0bad_89abcdef 0x00001000 ....
1 0xa5a5a5a5_5aaa5533_01234567_77889900 0x00010000 ....
# Check that instructions were loaded properly
? 0x11008000 0x2bad2bad 0xffffffff
? 0x11008004 0xbeef0bad 0xffffffff
? 0x11008014 0x12987423 0xffffffff
? 0x11008028 0x75577588 0xffffffff
? 0x1100803c 0xa5a5a5a5 0xffffffff
# Check that source addresses were loaded properly
? 0x21008000 0x00000010 0xffffffff
? 0x21008004 0x00000010 0xffffffff
? 0x21008008 0x00000100 0xffffffff
? 0x2100800c 0x00000100 0xffffffff
? 0x21008010 0x00001000 0xffffffff
? 0x21008014 0x00001000 0xffffffff
? 0x21008018 0x00010000 0xffffffff
? 0x2100801c 0x00010000 0xffffffff
# Test MPG instruction with bad operand alignment
1 0x00000000_4a020000_00000000_00000000 0x00000000 PPPP
# Read STAT register; confirm ER1 bit set
? 0x10003c00 0x00002000 0x00002000
# Reset PKE
! 0x10003c10 0x00000001
# Read STAT register; confirm ER1 no longer set
? 0x10003c00 0x00000000 0x00002000
# Test MPG instruction with good operand alignment
1 0x00000000_00000000_4a010000_00000000 0x00000000 ..PP
# Read STAT register; confirm ER1 bit not set
? 0x10003c00 0x00000000 0x00002000
# Test MPG instruction with bad operand alignment
1 0x00000000_00000000_00000000_4a010000 0x00000000 PPPP
# Read STAT register; confirm ER1 bit set
? 0x10003c00 0x00002000 0x00002000
# Reset PKE
! 0x10003c10 0x00000001
# Read STAT register; confirm ER1 no longer set
? 0x10003c00 0x00000000 0x00002000
#
#
# ---- STROW/ROW + DMA mismatch ----
#
# Test STROW instruction; leave operand out for now
0 0x30000000_00000000_00000000_00000000 0x00000000 PPPP
# Read STAT register; confirm PPS field set at WAIT
? 0x10003800 0x00000001 0x00000003
# Write ERR register; mask ER0 stalling
! 0x10003820 0x00000002
# Supply operand - four words
0 0x1234abcd_2345bcde_ffffffff_ffffffff 0x00000000 ..DD
0 0x00000000_00000000_5432dcba_76543210 0x00000000 PP..
# Read STAT register; confirm ER0 (DMA mismatch)
? 0x10003800 0x00001000 0x00001000
# Make erroneous write
! 0x10003900 0x11111111
! 0x10003910 0x22222222
! 0x10003920 0x33333333
! 0x10003930 0x44444444
# Check row registers for value
? 0x10003900 0x2345bcde 0xffffffff
? 0x10003910 0x1234abcd 0xffffffff
? 0x10003920 0x76543210 0xffffffff
? 0x10003930 0x5432dcba 0xffffffff
# Read STAT register; confirm ER1 not set
? 0x10003800 0x00000000 0x00002000
# Reset PKE
! 0x10003810 0x00000001
#
#
# ---- STCOL/COL + STOP/CONTINUE ----
#
# Test STCOL instruction; leave operand out for now
0 0x31000000_00000000_00000000_00000000 0x00000000 PPPP
# Read STAT register; confirm PPS field set at WAIT
? 0x10003800 0x00000001 0x00000003
# Stop PKE with FBK bit
! 0x10003810 0x00000002
# Supply operand - four words
0 0x1234abcd_2345bcde_5432dcba_76543210 0x00000000 ....
# Confirm that PKE is continuing to stall due to FBK
? 0x10003800 0x00000200 0x00000200
? 0x10003800 0x00000200 0x00000200
? 0x10003800 0x00000200 0x00000200
# Resume PKE with STC bit
! 0x10003810 0x00000008
# Read STAT register; confirm FBK no longer set
? 0x10003800 0x00000000 0x00000200
# Check column registers for value
? 0x10003940 0x76543210 0xffffffff
? 0x10003950 0x5432dcba 0xffffffff
? 0x10003960 0x2345bcde 0xffffffff
? 0x10003970 0x1234abcd 0xffffffff
# Read STAT register; confirm ER1 not set
? 0x10003800 0x00000000 0x00002000
#
# Try stopping using STP bit this time
# Test STCOL instruction; leave operand out for now
1 0x31000000_00000000_00000000_00000000 0x00000000 PPPP
# Read STAT register; confirm PPS field set at WAIT
? 0x10003c00 0x00000001 0x00000003
# Stop PKE after current instruction with STP bit
! 0x10003c10 0x00000004
# Supply operand - four words
1 0x1234abcd_2345bcde_5432dcba_76543210 0x00000000 ....
# Check column registers for value
? 0x10003d40 0x76543210 0xffffffff
? 0x10003d50 0x5432dcba 0xffffffff
? 0x10003d60 0x2345bcde 0xffffffff
? 0x10003d70 0x1234abcd 0xffffffff
# Now send a new instruction with operands; this should stall
1 0x31000000_00000000_00000000_00000000 0x00000000 PPPP
1 0x11111111_22222222_33333333_44444444 0x00000000 ....
# Confirm that PKE is continuing to stall due to PSS
? 0x10003c00 0x00000100 0x00000100
? 0x10003c00 0x00000100 0x00000100
? 0x10003c00 0x00000100 0x00000100
# Resume PKE with STC bit; it should process pent-up STCOL
! 0x10003c10 0x00000008
# Check column registers for value
? 0x10003d40 0x44444444 0xffffffff
? 0x10003d50 0x33333333 0xffffffff
? 0x10003d60 0x22222222 0xffffffff
? 0x10003d70 0x11111111 0xffffffff
# Read STAT register; confirm ER1 not set
? 0x10003c00 0x00000000 0x00002000
#
#
# ---- MSKPATH3 ----
#
# Set then clear MSKPATH3 on PKE1
1 0x06008000_00000000_06000000_00000000 0x00000000 PPPP
# Read STAT register; confirm ER1 not set
? 0x10003c00 0x00000000 0x00002000
# Erroneously run this on PKE0
0 0x06008000_00000000_06000000_00000000 0x00000000 PPPP
# Read STAT register; confirm ER1 set
? 0x10003800 0x00002000 0x00002000
# Reset PKE0
! 0x10003810 0x00000001
#
#
# ---- memory-mapped port reading ----
#
# Erroneously read words from FIFO ports
? 0x10004000 0x00000000 0xffffffff
? 0x10004004 0x00000000 0xffffffff
? 0x10004008 0x00000000 0xffffffff
? 0x1000400c 0x00000000 0xffffffff
? 0x10005000 0x00000000 0xffffffff
? 0x10005004 0x00000000 0xffffffff
? 0x10005008 0x00000000 0xffffffff
? 0x1000500c 0x00000000 0xffffffff
#
# Erroneously read PKE1-only registers on PKE0
? 0x100038a0 0x00000000 0xffffffff
? 0x100038b0 0x00000000 0xffffffff
? 0x100038c0 0x00000000 0xffffffff
? 0x100038e0 0x00000000 0xffffffff
? 0x100038f0 0x00000000 0xffffffff
#
# Erroneously write PKE1-only registers on PKE0
! 0x100038a0 0x00000000
! 0x100038b0 0x00000000
! 0x100038c0 0x00000000
! 0x100038e0 0x00000000
! 0x100038f0 0x00000000
#
# Erroneously read write-only registers
? 0x10003810 0x00000000 0xffffffff
? 0x10003c10 0x00000000 0xffffffff
#
# Erroneously write read-only registers
! 0x10003c00 0x00000000
! 0x10003c40 0x00000000
! 0x10003c50 0x00000000
! 0x10003c60 0x00000000
! 0x10003c70 0x00000000
! 0x10003c80 0x00000000
! 0x10003c90 0x00000000
! 0x10003ca0 0x00000000
! 0x10003cb0 0x00000000
! 0x10003cc0 0x00000000
! 0x10003cd0 0x00000000
! 0x10003ce0 0x00000000
! 0x10003cf0 0x00000000
! 0x10003d00 0x00000000
! 0x10003d10 0x00000000
! 0x10003d20 0x00000000
! 0x10003d30 0x00000000
! 0x10003d40 0x00000000
! 0x10003d50 0x00000000
! 0x10003d60 0x00000000
! 0x10003d70 0x00000000
#