Commit graph

730 commits

Author SHA1 Message Date
Doug Evans
fbc8134df6 * cgen-opc.in (@arch@_cgen_lookup_insn): Update call to
CGEN_EXTRACT_FN.
	(@arch@_cgen_get_insn_operands): @arch@_cgen_get_operand renamed to
	@arch_cgen_get_int_operand.
	* cgen-asm.in (insert_insn_normal): New arg `pc', callers updated.
	Update call to @arch@_cgen_insert_operand.
	(@arch@_cgen_assemble_insn): Update call to CGEN_INSERT_FN.
	* cgen-dis.in (print_normal): Delete use of CGEN_PCREL_OFFSET.
	(extract_insn_normal): New arg `pc', callers updated.
	Update call to @arch@_cgen_extract_operand.
	(print_insn): Update call to CGEN_EXTRACT_FN.
	* m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c: Regenerate.
1998-07-21 20:59:23 +00:00
Jeff Law
f10a9bdead * m10300-opc.c (mn10300_opcodes): Fix opcode for 4 operand "mul" and
"mulu".
1998-07-17 00:06:55 +00:00
Ian Lance Taylor
33b111fa62 Mon Jul 13 14:53:59 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
* i386-dis.c (ckprefix): Handle fwait specially only when it isn't
	the first prefix.
	(dofloat): Correct test for fnstsw.  Print `fnstsw %ax' rather
	than `fnstsw %eax'.
	(OP_J): Remove unnecessary subtraction when 16-bit displacement
	will be masked later.
1998-07-13 18:54:43 +00:00
Jeff Law
228695a5d8 * m10300-opc.c (mn10300_opcodes): Fix destination operand for 3 operand
instructions.
1998-07-11 05:12:03 +00:00
Jeff Law
ccd5eb2da9 * m10300-dis.c (disassemble): When printing RREGs and XRREGs, map
from raw register #s to symbolic names to make debugging easier.
1998-07-08 17:38:15 +00:00
Doug Evans
1b9ec81e15 * m32r-opc.h (CGEN_MIN_INSN_SIZE): New #define. 1998-07-03 00:11:25 +00:00
Doug Evans
0499462e76 * Makefile.am (CGENDIR): Set via configure.
(CGEN): New variable.
	(CGENFILES): object.scm renamed to cos.scm.
	(run-cgen): Renamed from cgen.  stamp file renamed to stamp-$prefix.
	(stamp-m32r): Pass prefix to run-cgen.
	* Makefile.in: Regenerate.
	* cgen-asm.in: @arch@-opc.h renamed to @prefix@-opc.h.
	* cgen-dis.in: Ditto.
	* cgen-opc.in: Ditto.
	* cgen.sh: New args cgen,prefix.  Delete args scheme,schemeflags.
	* configure.in: AC_SUBST cgen,cgendir.  No longer look for guile.
	* configure: Regenerate.
	* m32r-asm.c,m32r-dis.c,m32r-opc.c,m32r-opc.h: Regenerate.
1998-07-01 23:31:27 +00:00
Doug Evans
3c88e9a988 * dvp-opc.c (DVP_OPERAND_RELOC_11_S4): Temporarily back out
the DVP_OPERAND_RELOC_11_S4 relocation.
	* dvp-opc.c (LIMM11, LUIMM15): New symbol types
	DVP_OPERAND_RELOC_U15_S3 and DVP_OPERAND_RELOC_11_S4 to allow labels to
	be used as immediate values.
1998-07-01 19:34:55 +00:00
Nick Clifton
e38a77d3ca Replace object.scm with cos.scm 1998-07-01 16:42:36 +00:00
Jeff Law
ff7a9bc9b4 * m10300-opc.c: Reorder "movbu" and "movhu" instructions too.
Why oh why didn't they take our advice about register prefixing.  It would
have avoided the ambigious syntax issues.  Sigh.
1998-06-30 16:04:44 +00:00
Jeff Law
a841b47c4b * m10300-opc.c: Reorder more instructions so that we do not
accidentally match a mn10300 instruction when we really
        wanted an am33 instruction.
1998-06-29 20:57:25 +00:00
Jeff Law
0c9b3858c1 * m10300-dis.c: Only recognize instructions from the currently
selected machine.
        * m10300-opc.c: Add field indicating the particular variant of
        the mn10300 each instruction is available on.
1998-06-26 17:12:10 +00:00
Ian Lance Taylor
69ad8cac12 * configure.in: For bfd_vax_arch, build vax-dis.lo.
* Makefile.am: Rebuild dependencies.
 	(CFILES): Add vax-dis.c.
	(ALL_MACHINES): Add vax-dis.lo.
	* aclocal.m4: Rebuild with current libtool.
	* configure, Makefile.in: Rebuild.

Fri Jun 26 12:03:20 1998  Klaus Kaempf  <kkaempf@progis.de>

	* vax-dis.c: New file, from work by Pauline Middelink
	<middelin@polyware.iaf.nl>.
	* disassemble.c (ARCH_vax): Define if ARCH_all.
	(disassembler): Add case for ARCH_vax.
	* makefile.vms: Support compilation on vms/vax.
1998-06-26 16:08:02 +00:00
Jeff Law
1c2a961d56 * m10300-dis.c (print_insn_mn10300): 0xf7 opcode prefix specifies
4 byte instructions.
        (disassemble): Correctly handle FMT_D10 instructions.
1998-06-24 19:04:06 +00:00
Jeff Law
59557be25d * mn10300-opc.c (mn10300_opcodes): Fix typo in IMM24 versions of the
am33 shift instructions.
1998-06-24 19:02:27 +00:00
Jeff Law
c29d7797d2 * mn10300-dis.c (print_insn_mn10300): 0xf9 opcode prefix specifies
3 byte instructions.
        (disassemble): Handle new instruction formats FMT_D6, FMT_D7, FMT_D8
        FMT_D9 and FMT_D10.  Handle various new opcode flags for the am33.
1998-06-24 16:00:43 +00:00
Jeff Law
4da06098ff * mn10300-opc.c (IMM32_HIGH8_MEM): New operand type.
(mn10300_opcodes): Reorder so as to try and select opcodes from
        the core chip when multiple alternatives exist.  Change several
        am33 instructions to use IMM32_HIGH8_MEM.  Fix typos in "mac" and
        "macbu" instructions.  Fix typos in a couple DSP instructions too.
1998-06-24 15:56:40 +00:00
Mark Alexander
42fc298244 * m10200-dis.c (print_insn_mn10200): Fix various non-portabilities
related to sign extension and the size of ints.
1998-06-24 02:49:07 +00:00
Jeff Law
8b727aa4d3 * m10300-opc.c: Support one operand "asr", "lsr" and "asl"
instructions.  Support (sp) addressing mode by expanding it into
        (0,sp).
1998-06-23 17:01:44 +00:00
Jeff Law
c5a6e18b2e * m10300-opc.c: Support 4 byte DSP instructions. 1998-06-22 19:38:35 +00:00
Jeff Law
d7f444fd7a * m10300-opc.c: Support 6 and 7 byte am33 instructions. 1998-06-19 22:49:43 +00:00
Mark Alexander
7b61b0945f * m10200-dis.c (print_insn_mn10200): Recognize 'break' pseudo-op. 1998-06-19 16:19:12 +00:00
Jeff Law
b17af7f6ef * m10300-opc.c: Support for 3 byte and 4 byte extended instructions
found on the mn10300.
1998-06-19 15:45:13 +00:00
Ulrich Drepper
d2a24cee53 Update. 1998-06-19 01:58:48 +00:00
Jeff Law
a145a5ac84 Rework ChangeLog entry to avoid mentioning vr5400 in a r5900 entry. 1998-06-18 19:14:20 +00:00
John Metzler
20af011086 * mips-dis.c (print_insn_little_mips): Previously, instruction
printing references the symbol table to determine whether the
 	instruction resides in a block regular instructions or mips16
 	instructions. However, when the disassembler gets used in other
 	environments where the symbol table is not present, we no longer
 	rely in the symbol table, rather, use the low bit of the
 	instructions address to guess. There should be no change for usage
 	of the disassembler in host based programse, gdb ,objdump.
	(print_insn_big_mips): ditto.
	(print_insn_mips): ditto
1998-06-18 17:30:26 +00:00
Jeff Law
9eb61c7c61 start-sanitize-am33
* m10300-opc.c (USP, SSP, MSP, PC, IMM4, EPSW, RN0, RM1): New
        operands for the am33.
        (mn10300_opcodes): Add new instructions from the am33.
end-sanitize-am33
        * m10300-opc.c (mn10300_opcodes): Change opcode for "syscall".

Snapshot current work.
1998-06-17 23:54:25 +00:00
Ian Lance Taylor
e6db632454 Tue Jun 16 13:10:51 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
* i386-dis.c (index16): Add '%' to register names.  Use ','
	instead of '+'.
1998-06-16 17:11:47 +00:00
Ian Lance Taylor
5f90dab190 Sat Jun 13 11:33:55 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
* i386-dis.c: Don't print opcode suffix when we can figure out the
	size (and gas can!) by register operands, or from the default
	size.
	(putop): Handle 'A', 'B', 'L', 'P', 'Q', 'R' macros.  Rename 'C'
	macro to 'E'.
	(dis386, dis386_twobyte, grps): Use new suffix macros.
	(dis386): Correct imul Ib to imul sIb.  Change jnl to jge to be
	consistent.  Add suffix for call, jmp, lcall, ljmp, iret.  Reverse
	order of cmps operands to agree with Intel docs.  Correct operand
	of aad and aam (Ib -> sIb).  Change ud2b from 0fb8 to 0fb9 to
	agree with Intel docs.
	(print_insn_x86): Print orphan fwait before other prefixes.
	Return correct byte count for orphan fwait with prefixes.  Don't
	print `bound' operands in reverse order.
	(ckprefix): Stop accumulating prefixes if we get fwait.
	(OP_DIR): Print `$' before Ap operands of ljmp, lcall.
1998-06-13 15:38:32 +00:00
Tom Tromey
3d935b64eb * po/Make-in (all-yes): If maintainer mode, depend on .pot file.
($(PACKAGE).pot): Unconditionally depend on POTFILES.
1998-06-12 22:39:34 +00:00
Ian Lance Taylor
80ade9931a Fri Jun 12 11:04:06 1998 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
Fix problems when bfd_vma is wider than long.
	* i386-dis.c: Make op_address and start_pc unsigned.
	(set_op): Make parameter unsigned.
	(print_insn_x86): Cast to bfd_vma when passing a value to
	print_address_func.
	* ns32k-dis.c (CORE_ADDR): Don't define.
 	(print_insn_ns32k): Change type of addr to bfd_vma.  Use
	bfd_scan_vma to read back address.
	(print_insn_arg): Change type of addr to bfd_vma.  Use sprintf_vma
	to format it.
	* m68k-dis.c (COERCE32): Cast to bfd_signed_vma to avoid overflow.
	(NEXTULONG): New definition.
	(print_insn_m68k): Avoid overflow when computing third argument of
	print_insn_arg.
	(print_insn_arg): Use NEXTULONG to fetch 32 bit address values.
	Use disp instead of val to store offset values.
	(print_indexed): Use base_disp instead of word to store base
	displacement, to avoid overflow.
	* m10300-dis.c (disassemble): Cast value to long when computing
	pc-relative address, to get correct sign extension.
1998-06-12 15:13:28 +00:00
Doug Evans
aead84dc65 * m32r-opc.c: Regenerate.
Updates from better VoidMode handling in cgen.
1998-06-10 23:00:10 +00:00
Nick Clifton
c36224ac5a Disassemble 'add rX, rY, #0' as 'mov rX, rY'. 1998-06-09 21:30:56 +00:00
Nick Clifton
f79ebb2c0f Fix for PR16116 - remove FLAG_MUL32 attribute from MULX2H insn. 1998-06-09 01:18:34 +00:00
Ian Lance Taylor
80119c9ee4 Fri Jun 5 23:47:55 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
* i386-dis.c:  Combine aflag and dflag into sizeflag.  Change OP_*
	functions to void.
	(OP_DSreg): Rename from OP_DSSI.
	(OP_ESreg): Rename from OP_ESDI.
	(Xb, Xv, Yb, Yv): Use index reg code, not b_mode or v_mode.
	(DSBX): Define.
	(append_seg): Rename from append_prefix.
	(ptr_reg): New function.
	(dis386): Add S suffix to pushf, popf, ret, lret, enter, leave.
	Add DSBX for xlat.
	(PREFIX_ADDR): Rename from PREFIX_ADR.
	(float_reg): Add non-broken opcodes for people who don't want
	UNIXWARE_COMPAT.
1998-06-06 03:54:24 +00:00
Ian Lance Taylor
587b388d85 Fri Jun 5 19:15:04 1998 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
* m68k-opc.c (tstb, tstw, tstl): Don't allow pcrel on
	68000/68008/68010.
1998-06-05 23:15:45 +00:00
Ian Lance Taylor
06f9c743fc x 1998-06-03 22:57:17 +00:00
Ian Lance Taylor
ea81d2f627 Tue Jun 2 15:06:46 1998 Geoff Keating <geoffk@ozemail.com.au>
* ppc-opc.c (powerpc_macros): Support shifts and rotates of size
	0; produce error message for shifts of size 32 (or 64 for 64-bit
	shifts), because the hardware doesn't support them.
1998-06-02 19:07:44 +00:00
Jeff Law
e10f900fac * mips-opc.c (c.lt.s): Remove r5900 specific variant.
(c.le.s): Likewise.
1998-06-01 18:25:20 +00:00
Jeff Law
7d3d00f846 * vu0.h (sqc2): Fix opcode. 1998-06-01 16:36:09 +00:00
Jeff Law
d2c9a57bc6 * mips-opc.c (rsqrt.s): Update based on r5900 ISA manual version 2.1
(sqrt.s): Likewise.
1998-06-01 16:28:52 +00:00
Stan Cox
e2cb37fee1 sparclite 86x big endian instruction / little endian data support. 1998-05-27 00:51:33 +00:00
Nick Clifton
3db24c6bc8 Fix PR15984 - Add flags to various opcodes 1998-05-26 23:53:12 +00:00
Nick Clifton
42b5fd3608 Fix Pr15998 - Make SHORT_B3(b) formats examin but not modify their first register argument. 1998-05-26 23:15:23 +00:00
Doug Evans
cbc6c9b2bf * cgen-asm.in (insert_normal): Handle empty fields and 64 bit hosts.
* cgen-dis.in (extract_normal): Likewise.
	* m32r-asm.c,m32r-dis.c: Regenerate.
1998-05-22 23:03:45 +00:00
Doug Evans
05f704645d * cgen-asm.in (insert_normal): Handle empty fields and 64 bit hosts.
* cgen-dis.in (extract_normal): Likewise.
1998-05-22 23:02:40 +00:00
Doug Evans
b2158e2f1b * dvp-opc.c (parse_dotdest): Missing dest -> xyzw. 1998-05-22 18:45:19 +00:00
Jeff Law
3366d0655b * mips-opc.c (multu1): Add two operand variant for the r5900. 1998-05-20 06:21:01 +00:00
Ian Lance Taylor
7e9e8c361d * mips-dis.c (print_mips16_insn_arg): Handle type ']' correctly
with a shift count of 0.
1998-05-19 21:36:42 +00:00
Frank Ch. Eigler
10c3731d9c * Followup for SCEI PR 15853: 2-operand R5900 "mult1" instruction.
Mon May 18 14:27:06 1998  Frank Ch. Eigler  <fche@cygnus.com>
	* mips-opc.c (mult1): Add two-operand variety of mult1 for R5900.
1998-05-18 17:46:35 +00:00