into call and jmp instructions with 32bit offsets.
Fix typo in bit test patterns.
* gas/mn10300/other.s: Tweak constants to improve
testsuite coverage.
movbu, movhu instructions. Check bit patterns for more bit
operations. Check bit patterns for various 16bit call, retf
and ret instructions.
* gas/mn10300/other.s: Update operands for better test coverage.
Improving testsuite coverage.
assembler now always builds a symbol table, which means that
objdump will no longer report `No symbols in FILE'. Change the
expected output accordingly.
with a single 8bit or 16bit immediate operand.
We should correctly assemble just about everything except opcodes with:
multiple immediate operands,
3 register operands,
really weird stuff
instructions. Add missing test in do_mov1.
* gas/mn10300/mov1.s: Add missing test.
We should now assemble just about anything without any
immediate operands.
* config/tc-arm.c (md_apply_fix3): Update two thumb instruction
slots when processing BL fixups.
* config/tc-arm.c (output_inst): Ensure Thumb BL fixup is marked
on the first half of the instruction.
Thu Sep 12 10:28:44 1996 James G. Smith <jsmith@cygnus.co.uk>
* gas/arm/thumb.s (back): Check assembly of Thumb BL.
* config/tc-mips.c (load_register): Remove unnecessary code that
was causing the high 32bits of 64bit constants to be lost.
Fixes PR10503. The compiler was producing the assembler code:
dli $3,0xfffffffffffff
when constructing the softfloat library. Unfortunately it was being
incorrectly assembled.
any given register table.
(register_name): Pass appropriate table and size to reg_name_search.
(system_register_name): New function.
(SYSREG_NAME_CNT): Define.
(md_assemble): Handle operands which are system registers.
Still working on the parser..
* config/tc-arm.c: Changed INSN_SIZE to variable insn_size, as
pre-cursor to adding Thumb support. Also added cpu_variant flag
information to each of the asm_flg structures.
(md_parse_option): Updated ARM7 parsing to allow 't' for
thumb/halfword support, aswell as 'm' for long multiply.
(md_show_usage): Updated help message.
(md_assemble): Check that instruction flags are applicated to the
current cpu variant.
(md_apply_fix3, tc_gen_reloc): Add BFD_RELOC_ARM_OFFSET_IMM8 and
BFD_RELOC_ARM_HWLITERAL relocation support for new halfword and
signextension instructions.
(do_ldst): Generate halfword and signextension variants if
mnemonic flags match.
(ldst_extend): Do not allow shifts in the offset field of halfword
or signextension instructions.
(validate_offset_imm): Provide check on halfword and signextension
immediate range.
(add_to_lit_pool): Merge identical literal pool values.
Wed Jul 31 15:55:12 1996 James G. Smith <jsmith@cygnus.co.uk>
* gas/arm/arm7t.s: Added.
* gas/arm/arm7t.d: Added.
* gas/arm/arm.exp: Updated to run the new test.
