Commit graph

4423 commits

Author SHA1 Message Date
H.J. Lu
293f5f6543 Reimplement .no87/.nommx/.nosse/.noavx directives
Move all .noXXX directives to cpu_noarch.

gas/

	* config/tc-i386.c (arch_entry): Remove negated.
	(noarch_entry): New struct.
	(cpu_arch): Updated.  Remove .no87, .nommx, .nosse and .noavx.
	(cpu_noarch): New.
	(set_cpu_arch): Check cpu_noarch after cpu_arch.
	(md_parse_option): Allow -march=+nosse.  Check cpu_noarch after
	cpu_arch.
	(output_message): New function.
	(show_arch): Use it.  Handle cpu_noarch.
	* testsuite/gas/i386/i386.exp: Run nommx-1, nommx-2, nommx-3,
	nosse-1, nosse-2, nosse-3, noavx-1 and noavx-2.
	* testsuite/gas/i386/noavx-1.l: New file.
	* testsuite/gas/i386/noavx-1.s: Likewise.
	* testsuite/gas/i386/noavx-2.s: Likewise.
	* testsuite/gas/i386/noavx-2.l: Likewise.
	* testsuite/gas/i386/nommx-1.s: Likewise.
	* testsuite/gas/i386/nommx-1.l: Likewise.
	* testsuite/gas/i386/nommx-2.s: Likewise.
	* testsuite/gas/i386/nommx-2.l: Likewise.
	* testsuite/gas/i386/nommx-3.s: Likewise.
	* testsuite/gas/i386/nommx-3.l: Likewise.
	* testsuite/gas/i386/nosse-1.s: Likewise.
	* testsuite/gas/i386/nosse-1.l: Likewise.
	* testsuite/gas/i386/nosse-2.s: Likewise.
	* testsuite/gas/i386/nosse-2.l: Likewise.
	* testsuite/gas/i386/nosse-3.s: Likewise.
	* testsuite/gas/i386/nosse-3.l: Likewise.

opcodes/

	* i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
	CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
	* i386-init.h: Regenerated.
2016-05-25 10:26:13 -07:00
Chua Zheng Leong
934c263269 Only generate VMOV.I64 instructions for loading constant floating point values if this instruction is supported by the currently selected fpu.
PR target/2006764
	* config/tc-arm.c (move_or_literal_pool): Only generate a VMOV.I64
	instruction if supported by the currently selected fpu variant.
	* testsuite/gas/arm/vfpv3-ldr_immediate.s: Add test of this PR.
	* testsuite/gas/arm/vfpv3-ldr_immediate.d: Update expected disassembly.
2016-05-25 13:09:51 +01:00
Maciej W. Rozycki
44d3da2338 MIPS/GAS: Treat local jump relocs the same no matter if REL or RELA
Do not convert jump relocs against local MIPS16 or microMIPS symbols to
refer to a section symbol instead even on RELA targets, as it makes it
impossible for the linker to make a JAL to JALX conversion based on ISA
symbol annotation, breaking regular and compressed MIPS interlinking.

	gas/
	* config/tc-mips.c (mips_fix_adjustable): Also return 0 for
	jump relocations against MIPS16 or microMIPS symbols on RELA
	targets.
	* testsuite/gas/mips/jalx-local.d: New test.
	* testsuite/gas/mips/jalx-local-n32.d: New test.
	* testsuite/gas/mips/jalx-local-n64.d: New test.
	* testsuite/gas/mips/jalx-local.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	ld/
	* testsuite/ld-mips-elf/jalx-local.d: New test.
	* testsuite/ld-mips-elf/jalx-local-n32.d: New test.
	* testsuite/ld-mips-elf/jalx-local-n64.d: New test.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-05-24 14:11:50 +01:00
Maciej W. Rozycki
4512dafa50 MIPS/GAS: Cut TLS reloc dead code path in `md_apply_fix'
With code refactoring made in commit b886a2ab0d and the addition of
`calculate_reloc' and a separate test for TLS relocs against constants
made there the preexisting fall-through from the TLS reloc switch case
has effectively become a dead execution path.  This is because the call
to `calculate_reloc' present there is only made if `fixP->fx_done' is
true, which can only be the case if `fixP->fx_addsy' is NULL, which in
turn has already triggered the TLS reloc test and made execution break
out of the switch statement.

Remove the fall-through then and reshape code accordingly.

	gas/
	* config/tc-mips.c (md_apply_fix)
	<BFD_RELOC_MIPS16_TLS_TPREL_LO16>: Remove fall-through, adjust
	code accordingly.
2016-05-24 14:09:03 +01:00
Trevor Saunders
cc34adb290 xtensa: make map_suffix_reloc_to_operator return operatorT
It always returns an element of the enum operatorT, so it should be clearer to
make that the return type.

gas/ChangeLog:

2016-05-24  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-xtensa.c (struct suffix_reloc_map): Change type of field
	operator to operatorT.
	(map_suffix_reloc_to_operator): Change return type to operatorT.
2016-05-24 08:57:36 -04:00
Trevor Saunders
c023823f5f d30v: make var type operatorT
gas/ChangeLog:

2016-05-24  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-d30v.c (find_format): Change type of X_op to operatorT.
2016-05-24 08:55:45 -04:00
Trevor Saunders
049efc6495 mmix: constify handler_charp
gas/ChangeLog:

2016-05-24  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-mmix.c (mmix_parse_predefined_name): Change type of
	handler_charp to const char *.
2016-05-24 08:52:45 -04:00
Trevor Saunders
b19e0aeb53 ft32: fixup TARGET_FORMAT
Nothing ever assigns to ft32_target_format, so its always null, which means the
bfd target arch is the default one.  It looks like ft32 only has one target
format, so we can just define TARGET_FORMAT to be that literal string.

gas/ChangeLog:

2016-05-24  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-ft32.h (DEFAULT_TARGET_FORMAT): Remove.
	(ft32_target_format): Likewise.
	(TARGET_FORMAT): Adjust.
2016-05-24 08:49:46 -04:00
Trevor Saunders
e5e27b0769 ia64: use XOBNEW and XOBNEWVEC
gas/ChangeLog:

2016-05-24  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-ia64.c (dot_rot): simplify allocations from obstacks.
	(ia64_frob_label): Likewise.
2016-05-24 08:47:02 -04:00
Trevor Saunders
6610dc6daa change some variable's type to op_err
They only hold values from the op_err enum, so it should be clearer to give
them the enum type.

gas/ChangeLog:

2016-05-24  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-cr16.c (check_range): Make type of retval op_err.
	* config/tc-crx.c: Likewise.
2016-05-24 08:44:19 -04:00
Claudiu Zissulescu
87789e08e5 [ARC] Add XY registers, update neg instruction.
gas/
2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/tc-arc.c (md_begin): Add XY registers.
	(cpu_types): Code density is default off for ARC EM.

opcodes/
2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-tbl.h (neg): New instruction variant.
2016-05-23 17:32:13 +02:00
Claudiu Zissulescu
c810e0b87a [ARC] Rename "class" named attributes.
gas/
2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>

	* config/tc-arc.c (attributes_t): Renamed attribute class to
	attr_class.
	(find_opcode_match, assemble_insn, tokenize_extinsn): Changed.

opcode/
2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>

	* arc-dis.c (find_format, find_format, get_auxreg)
	(print_insn_arc): Changed.
	* arc-ext.h (INSERT_XOP): Likewise.

include/
2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>

	* opcode/arc.h (struct arc_opcode): Renamed attribute class to
	insn_class.
	(struct arc_flag_class): Renamed attribute class to flag_class.
2016-05-23 17:25:46 +02:00
Trevor Saunders
f10e0aef4f tic54x: use concat more
gas/ChangeLog:

2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-tic54x.c (tic54x_sect): simplify string creation.
2016-05-23 01:21:07 -04:00
Trevor Saunders
2900e701e0 spu: make some constants unsigned
The field in spu_opcode is unsigned, and for some values of opcode we can end
up shifting into the high bit.  So avoid possibly creating a negative number
and then assigning it to a unsigned field by shifting an unsigned constant.

gas/ChangeLog:

2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-spu.c (APUOP): Use OPCODE as an unsigned constant.
2016-05-23 01:20:09 -04:00
Trevor Saunders
3d207518c1 tic54x: rename typedef of struct symbol_
generic gas code has a struct symbol, and tic54x typedefs a struct to symbol.
This seems at least rather confusing, and it seems like target specific headers
shouldn't  put such generic names in the global namespace preventing other
generic code from using them.

opcodes/ChangeLog:

2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* tic54x-dis.c (sprint_mmr): Adjust.
	* tic54x-opc.c: Likewise.

gas/ChangeLog:

2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-tic54x.c (tic54x_mmregs): Adjust.
	(md_begin): Likewise.
	(encode_condition): Likewise.
	(encode_cc3): Likewise.
	(encode_cc2): Likewise.
	(encode_operand): Likewise.
	(tic54x_undefined_symbol): Likewise.

include/ChangeLog:

2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* opcode/tic54x.h (struct symbol_): typedef to tic54x_symbol instead of
	plain symbol.
2016-05-23 01:17:12 -04:00
Matthew Fortune
a4968f42e7 MIPS: Add support for P6600
gas/
	* config/tc-mips.c (mips_cpu_info_table): Update comment. Add
	p6600 entry.
	* doc/c-mips.texi: Document p6600 -march option.
2016-05-20 15:21:10 +01:00
H.J. Lu
4e21640f67 Preserve addend for R_386_GOT32 and R_X86_64_GOT32
We should preserve addend for R_386_GOT32 and R_X86_64_GOT32 as in
"movl $foo@GOT + 4, %eax" and "movq $foo@GOT + 4, %rax".

	PR gas/19600
	* config/tc-i386.c (md_apply_fix): Preserve addend for
	BFD_RELOC_386_GOT32 and BFD_RELOC_X86_64_GOT32.
	* testsuite/gas/i386/addend.d: New file.
	* testsuite/gas/i386/addend.s: Likewise.
	* testsuite/gas/i386/x86-64-addend.d: Likewise.
	* testsuite/gas/i386/x86-64-addend.s: Likewise.
	* testsuite/gas/i386/i386.exp: Run addend and x86-64-addend.
	* testsuite/gas/i386/reloc32.d: Updated.
2016-05-20 06:01:28 -07:00
Maciej W. Rozycki
17c6c9d9f3 MIPS: Fix the encoding of immediates with microMIPS JALX
The microMIPS JALX instruction shares the R_MICROMIPS_26_S1 relocation
with microMIPS J/JAL/JALS instructions, however unlike the latters its
encoded immediate argument is unusually shifted left by 2 rather than 1
in calculating the value used for the operation requested.

We already handle this exception in `mips_elf_calculate_relocation' in
LD, in a scenario where JALX is produced as a result of relaxing JAL for
the purpose of making a cross-mode jump.  We also get it right in the
disassembler in `decode_micromips_operand'.

What we don't correctly do however is processing microMIPS JALX produced
by GAS from an assembly source, where a non-zero constant argument or a
symbol reference with a non-zero in-place addend has been used.  In this
case the same calculation is made as for microMIPS J/JAL/JALS, causing
the wrong encoding to be produced by GAS on making an object file, and
then again by LD in the final link.  The latter in particular causes the
calculation, where the addend fits in the relocatable field, to produce
different final addresses for the same source code depending on whether
REL or RELA relocations are used.

Correct these issues by special-casing microMIPS JALX in the places that
have been previously missed.

	bfd/
	* elfxx-mips.c (mips_elf_read_rel_addend): Adjust the addend for
	microMIPS JALX.

	gas/
	* config/tc-mips.c (append_insn): Correct the encoding of a
	constant argument for microMIPS JALX.
	(tc_gen_reloc): Correct the encoding of an in-place addend for
	microMIPS JALX.
	* testsuite/gas/mips/jalx-addend.d: New test.
	* testsuite/gas/mips/jalx-addend-n32.d: New test.
	* testsuite/gas/mips/jalx-addend-n64.d: New test.
	* testsuite/gas/mips/jalx-imm.d: New test.
	* testsuite/gas/mips/jalx-imm-n32.d: New test.
	* testsuite/gas/mips/jalx-imm-n64.d: New test.
	* testsuite/gas/mips/jalx-addend.s: New test source.
	* testsuite/gas/mips/jalx-imm.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	ld/
	* testsuite/ld-mips-elf/jalx-addend.d: New test.
	* testsuite/ld-mips-elf/jalx-addend-n32.d: New test.
	* testsuite/ld-mips-elf/jalx-addend-n64.d: New test.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-05-20 13:38:48 +01:00
Maciej W. Rozycki
134c0c8bf4 MIPS/GAS: Correct tab-after-space formatting mistakes
* config/tc-mips.c: Correct tab-after-space formatting mistakes
	throughout.
2016-05-20 12:41:50 +01:00
Andrew Burgess
38cd8a0de8 gas/arc: Make member of arc_flags const
By making the flgp field of struct arc_flags constant we can remove a
place where we cast away the const-ness of a variable.  Also, given that
the value assigned to this field almost always comes from compile-time
constant data, having the field non-constant is probably a bad thing.

gas/ChangeLog:

	* config/tc-arc.c (find_opcode_match): Remove casting away of
	const.
	* config/tc-arc.h (struct arc_flags): Make flgp field const.
2016-05-18 22:24:51 +01:00
Andrew Burgess
9e32d9ae97 gas/arc: Use BFD_VMA_FMT for printf format specifier
Some debug code has the wrong printf format specifier for some types
that are (ultimately) bfd_vma.  Fixed by using BFD_VMA_FMT string.  This
only becomes an issue when building the tc-arc.c file with -DDEBUG=1 to
build in the debug code.

gas/ChangeLog:

	* config/tc-arc.c (md_pcrel_from_section): Use BFD_VMA_FMT where
	appropriate.
	(md_convert_frag): Likewise.
2016-05-18 22:24:25 +01:00
Andrew Burgess
fe779266b3 gas/arc: Fix array overrun when checking opcode array
The opcode array iterator mechanism can, in some situations, result in
reading memory outside of the opcode array.  When using the
iterator-next mechanism to find the next possible arc_opcode, if we find
an opcode where the name field is NULL, or the name does not match, then
the cached opcode pointer is not set to NULL.  The result is that
another call to iterator-next will again increment the opcode
pointer (which might now point outside the opcode array) and attempt to
access the name field of this undefined opcode.

Fixed in this commit by clearing the cached opcode pointer.

I've added a test case, which currently shows the bug, however, this
will only expose this bug while the opcode used (dsp_fp_cmp) is the last
opcode in the table.

gas/ChangeLog:

	* config/tc-arc.c (arc_opcode_hash_entry_iterator_next): Set
	cached opcode to NULL when we reach a non-matching opcode.
	* testsuite/gas/arc/asm-errors-2.d: New file.
	* testsuite/gas/arc/asm-errors-2.err: New file.
	* testsuite/gas/arc/asm-errors-2.s: New file.
2016-05-18 22:23:40 +01:00
Andrew Burgess
3b889a7878 gas/arc: Add guard against operand array overflow.
Currently supplying an input file with too many operands to an
instruction will cause the assembler to overflow and array and trigger
undefined behaviour.

This change checks that we don't access outside the limits of the
operand array.

gas/ChangeLog:

	* config/tc-arc.c (tokenize_arguments): Add checks for array
	overflow.
	* testsuite/gas/arc/asm-errors.s: Addition test line added.
	* testsuite/gas/arc/asm-errors.err: Update expected results.
2016-05-18 22:22:49 +01:00
Trevor Saunders
42e58860e2 rx: make field type enum
gas/ChangeLog:

2016-05-18  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-rx.c (struct cpu_type): Change the type of a field from
	int to enum rx_cpu_types.
2016-05-18 06:26:27 -04:00
Trevor Saunders
4bfaa1cae7 change the type of some fields to bfd_reloc_code_real_type
gas/ChangeLog:

2016-05-18  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-dlx.c (struct machine_it): change the type of a field from
	int to bfd_reloc_code_real_type.
	* config/tc-tic4x.c: Likewise.
2016-05-18 06:26:07 -04:00
Trevor Saunders
b42e9fa8cc Change type of v850_target_arch to enum bfd_architecture
gas/ChangeLog:

2016-05-18  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-v850.c (v850_target_arch): change type to enum
	bfd_architecture.
	* config/tc-v850.h (v850_target_arch): Likewise.
2016-05-18 06:09:44 -04:00
Alan Modra
a255f00a28 PPC_OPERAND_SIGNOPT range.
Commit b84bf58a accidentally extended the range of allowed negative
numbers.

	* config/tc-ppc.c (ppc_insert_operand): Trim PPC_OPERAND_SIGNOPT
	allowed negative range.
	* testsuite/gas/ppc/power9.s: Test xxspltib of -128, not -256.
	* testsuite/gas/ppc/power9.d: Update.
2016-05-18 12:43:21 +09:30
Trevor Saunders
7b14583ef0 m32r: make mach_table static and const
It is only read in tc-m32r.c, so it might as well be static and const, and
that should help the compiler slightly.

gas/ChangeLog:

2016-05-16  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-m32r.c (mach_table): Make static and const.
2016-05-16 05:06:48 -04:00
Trevor Saunders
0591130a7c tc-vax.c: make prototype of flonum_gen2vax match its definition
gas/ChangeLog:

2016-05-16  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-vax.c (flonum_gen2vax): Adjust prototype to match
	definition.
2016-05-16 05:04:01 -04:00
Trevor Saunders
9117cd3e10 stop defining linkrelax in multiple places
Defining linkrelax to have different values in as.c and tc-msp430.c /
tc-mn10300.c is at least rather tricky, and seems fragile, when we can just set
it in md_begin instead.

gas/ChangeLog:

2016-05-16  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-mn10300.c (md_begin): set linkrelax here instead of
	defining it.
	* config/tc-msp430.c (md_begin): Likewise.
2016-05-16 05:01:52 -04:00
Trevor Saunders
e18382406c m68hc11: make some vars type bfd_reloc_code_real_type
These variables only hold values from the bfd_reloc_code_real_type enum, and
are passed to functions that expect the argument to be of type
bfd_reloc_code_real_type, so it seems to make sense that there type is
bfd_reloc_code_real_type rather than int.

gas/ChangeLog:

2016-05-16  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-m68hc11.c (fixup8): Change variables type from int to
	bfd_reloc_code_real_type where appropriate.
	(fixup16): Likewise.
	(fixup8_xg): Likewise.
2016-05-16 04:55:31 -04:00
Maciej W. Rozycki
9dfa3e6347 SH64/GAS: Fix a -Wwrite-strings build failure
Fix a commit 6757cf5769 ("enable -Wwrite-strings for gas") regression.

	gas/
	* config/tc-sh64.c (shmedia_check_limits): Constify `msg'.
2016-05-15 23:23:47 +01:00
Alan Modra
d2edc834f7 Fix build breakage
* config/obj-coff.c (weak_uniquify): Delete unused var.
2016-05-13 15:58:07 +09:30
Trevor Saunders
add39d2344 use XNEW and related macros more
Its a bit shorter and simpler than raw xmalloc.

gas/ChangeLog:

2016-05-13  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* app.c (app_push): Use XNEW and related macros.
	* as.c (parse_args): Likewise.
	* cgen.c (make_right_shifted_expr): Likewise.
	(gas_cgen_tc_gen_reloc): Likewise.
	* config/bfin-defs.h: Likewise.
	* config/bfin-parse.y: Likewise.
	* config/obj-coff.c (stack_init): Likewise.
	(stack_push): Likewise.
	(coff_obj_symbol_new_hook): Likewise.
	(coff_obj_symbol_clone_hook): Likewise.
	(add_lineno): Likewise.
	(coff_frob_symbol): Likewise.
	* config/obj-elf.c (obj_elf_section_name): Likewise.
	(build_group_lists): Likewise.
	* config/obj-evax.c (evax_symbol_new_hook): Likewise.
	* config/obj-macho.c (obj_mach_o_indirect_symbol): Likewise.
	* config/tc-aarch64.c (insert_reg_alias): Likewise.
	(find_or_make_literal_pool): Likewise.
	(add_to_lit_pool): Likewise.
	(fill_instruction_hash_table): Likewise.
	* config/tc-alpha.c (load_expression): Likewise.
	(emit_jsrjmp): Likewise.
	(s_alpha_ent): Likewise.
	(s_alpha_end): Likewise.
	(s_alpha_linkage): Likewise.
	(md_begin): Likewise.
	(tc_gen_reloc): Likewise.
	* config/tc-arc.c (arc_insert_opcode): Likewise.
	(arc_extcorereg): Likewise.
	* config/tc-bfin.c: Likewise.
	* config/tc-cr16.c: Likewise.
	* config/tc-cris.c: Likewise.
	* config/tc-crx.c (preprocess_reglist): Likewise.
	* config/tc-d10v.c: Likewise.
	* config/tc-frv.c (frv_insert_vliw_insn): Likewise.
	(frv_tomcat_shuffle): Likewise.
	* config/tc-h8300.c: Likewise.
	* config/tc-i370.c (i370_macro): Likewise.
	* config/tc-i386.c (lex_got): Likewise.
	(md_parse_option): Likewise.
	* config/tc-ia64.c (alloc_record): Likewise.
	(set_imask): Likewise.
	(save_prologue_count): Likewise.
	(dot_proc): Likewise.
	(dot_endp): Likewise.
	(ia64_frob_label): Likewise.
	(add_qp_imply): Likewise.
	(add_qp_mutex): Likewise.
	(mark_resource): Likewise.
	(dot_alias): Likewise.
	* config/tc-m68hc11.c: Likewise.
	* config/tc-m68k.c (m68k_frob_label): Likewise.
	(s_save): Likewise.
	(mri_control_label): Likewise.
	(push_mri_control): Likewise.
	(build_mri_control_operand): Likewise.
	(s_mri_else): Likewise.
	(s_mri_break): Likewise.
	(s_mri_next): Likewise.
	(s_mri_for): Likewise.
	(s_mri_endw): Likewise.
	* config/tc-metag.c (create_mnemonic_htab): Likewise.
	* config/tc-microblaze.c: Likewise.
	* config/tc-mmix.c (s_loc): Likewise.
	* config/tc-nds32.c (nds32_relax_hint): Likewise.
	* config/tc-nios2.c (nios2_insn_reloc_new): Likewise.
	* config/tc-rl78.c: Likewise.
	* config/tc-rx.c (rx_include): Likewise.
	* config/tc-sh.c: Likewise.
	* config/tc-sh64.c (shmedia_frob_section_type): Likewise.
	* config/tc-sparc.c: Likewise.
	* config/tc-spu.c: Likewise.
	* config/tc-tic6x.c (static tic6x_unwind_info *tic6x_get_unwind): Likewise.
	(tic6x_start_unwind_section): Likewise.
	* config/tc-tilegx.c: Likewise.
	* config/tc-tilepro.c: Likewise.
	* config/tc-v850.c: Likewise.
	* config/tc-visium.c: Likewise.
	* config/tc-xgate.c: Likewise.
	* config/tc-xtensa.c (xtensa_translate_old_userreg_ops): Likewise.
	(new_resource_table): Likewise.
	(resize_resource_table): Likewise.
	(xtensa_create_trampoline_frag): Likewise.
	(xtensa_maybe_create_literal_pool_frag): Likewise.
	(cache_literal_section): Likewise.
	* config/xtensa-relax.c (append_transition): Likewise.
	(append_condition): Likewise.
	(append_value_condition): Likewise.
	(append_constant_value_condition): Likewise.
	(append_literal_op): Likewise.
	(append_label_op): Likewise.
	(append_constant_op): Likewise.
	(append_field_op): Likewise.
	(append_user_fn_field_op): Likewise.
	(enter_opname_n): Likewise.
	(enter_opname): Likewise.
	(split_string): Likewise.
	(parse_insn_templ): Likewise.
	(clone_req_or_option_list): Likewise.
	(clone_req_option_list): Likewise.
	(parse_option_cond): Likewise.
	(parse_insn_pattern): Likewise.
	(parse_insn_repl): Likewise.
	(build_transition): Likewise.
	(build_transition_table): Likewise.
	* dw2gencfi.c (alloc_fde_entry): Likewise.
	(alloc_cfi_insn_data): Likewise.
	(cfi_add_CFA_remember_state): Likewise.
	(dot_cfi_escape): Likewise.
	(dot_cfi_fde_data): Likewise.
	(select_cie_for_fde): Likewise.
	* dwarf2dbg.c (dwarf2_directive_loc): Likewise.
	* ecoff.c (ecoff_add_bytes): Likewise.
	(ecoff_build_debug): Likewise.
	* input-scrub.c (input_scrub_push): Likewise.
	(input_scrub_begin): Likewise.
	(input_scrub_next_buffer): Likewise.
	* itbl-ops.c (append_insns_as_macros): Likewise.
	(alloc_entry): Likewise.
	(alloc_field): Likewise.
	* listing.c (listing_newline): Likewise.
	(listing_listing): Likewise.
	* macro.c (get_any_string): Likewise.
	(delete_macro): Likewise.
	* stabs.c (generate_asm_file): Likewise.
	(stabs_generate_asm_lineno): Likewise.
	* subsegs.c (subseg_change): Likewise.
	(subseg_get): Likewise.
	* symbols.c (define_dollar_label): Likewise.
	(symbol_relc_make_sym): Likewise.
	* write.c (write_relocs): Likewise.
2016-05-13 00:35:51 -04:00
Trevor Saunders
29a2809e42 use xstrdup, xmemdup0 and concat more
gas/ChangeLog:

2016-05-13  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/obj-coff.c (obj_coff_def): Simplify string copying.
	(weak_name2altname): Likewise.
	(weak_uniquify): Likewise.
	(obj_coff_section): Likewise.
	(obj_coff_init_stab_section): Likewise.
	* config/obj-elf.c (obj_elf_section_name): Likewise.
	(obj_elf_init_stab_section): Likewise.
	* config/obj-evax.c (evax_shorten_name): Likewise.
	* config/obj-macho.c (obj_mach_o_make_or_get_sect): Likewise.
	* config/tc-aarch64.c (create_register_alias): Likewise.
	* config/tc-alpha.c (load_expression): Likewise.
	(s_alpha_file): Likewise.
	(s_alpha_section_name): Likewise.
	(tc_gen_reloc): Likewise.
	* config/tc-arc.c (md_assemble): Likewise.
	* config/tc-arm.c (create_neon_reg_alias): Likewise.
	(start_unwind_section): Likewise.
	* config/tc-hppa.c (pa_build_unwind_subspace): Likewise.
	(hppa_elf_mark_end_of_function): Likewise.
	* config/tc-nios2.c (nios2_modify_arg): Likewise.
	(nios2_negate_arg): Likewise.
	* config/tc-rx.c (rx_section): Likewise.
	* config/tc-sh64.c (sh64_consume_datalabel): Likewise.
	* config/tc-tic30.c (tic30_find_parallel_insn): Likewise.
	* config/tc-tic54x.c (tic54x_include): Likewise.
	(tic54x_macro_info): Likewise.
	(subsym_get_arg): Likewise.
	(subsym_substitute): Likewise.
	(tic54x_start_line_hook): Likewise.
	* config/tc-xtensa.c (xtensa_literal_prefix): Likewise.
	(xg_reverse_shift_count): Likewise.
	* config/xtensa-relax.c (enter_opname_n): Likewise.
	(split_string): Likewise.
	* dwarf2dbg.c (get_filenum): Likewise.
	(process_entries): Likewise.
	* expr.c (operand): Likewise.
	* itbl-ops.c (alloc_entry): Likewise.
	* listing.c (listing_message): Likewise.
	(listing_title): Likewise.
	* macro.c (check_macro): Likewise.
	* stabs.c (s_xstab): Likewise.
	* symbols.c (symbol_relc_make_expr): Likewise.
	* write.c (compress_debug): Likewise.
2016-05-13 00:35:51 -04:00
Matthew Fortune
8f4f9071ad Add MIPS32 DSPr3 support.
bfd/

	* elfxx-mips.c (print_mips_ases): Add DSPR3.

binutils/

	* readelf.c (print_mips_ases): Add DSPR3.

gas/

	* config/tc-mips.c (options): Add OPTION_DSPR3 and
	OPTION_NO_DSPR3.
	(md_longopts): Likewise.
	(md_show_usage): Add help for -mdspr3 and -mno-dspr3.
	(mips_ases): Define availability for DSPr3.
	(mips_ase_groups): Add ASE_DSPR3 to the DSP group.
	(mips_convert_ase_flags): Map ASE_DSPR3 to AFL_ASE_DSPR3.
	* doc/as.texinfo: Document -mdspr3, -mno-dspr3.  Fix -mdspr2
	formatting.
	* doc/c-mips.texi: Document -mdspr3, -mno-dspr3, .set dspr3 and
	.set nodspr3.  Fix -mdspr2 formatting.
	* testsuite/gas/mips/mips32-dspr3.d: New file.
	* testsuite/gas/mips/mips32-dspr3.s: Likewise.
	* testsuite/gas/mips/mips.exp: Run mips32-dspr3 test.

include/

	* elf/mips.h (AFL_ASE_DSPR3): New macro.
	(AFL_ASE_MASK): Update to include AFL_ASE_DSPR3.
	* opcode/mips.h (ASE_DSPR3): New macro.

opcodes/

	* mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
	mips64r6.
	* mips-opc.c (D34): New macro.
	(mips_builtin_opcodes): Define bposge32c for DSPr3.
2016-05-11 17:06:13 +01:00
Nick Clifton
a6684f0ddd Ensure that padding in the constant pool uses constant values.
PR target/20068
	* config/tc-arm.c (add_to_lit_pool): Ensure that the padding added
	to the pool uses O_constant.
	* testsuite/gas/arm/pr20068.s: New test.
	* testsuite/gas/arm/pr20068.d: Test driver.
2016-05-11 12:53:12 +01:00
Alexander Fomin
8bc526963e Enable Intel RDPID instruction.
This patch enables Intel RDPID instruction described in Intel64 and
IA-32 Architectures Software Developer's Manual, April 2016.

gas/

	* config/tc-i386.c (cpu_arch): Add RDPID.
	* doc/c-i386.texi: Document RDPID.

gas/testsuite/

	* gas/i386/i386.exp: Run RDPID tests.
	* gas/i386/prefix.d: Adjust.
	* gas/i386/rdpid.s: New test.
	* gas/i386/rdpid.d: Ditto.
	* gas/i386/rdpid-intel.d: Ditto.
	* gas/i386/x86-64-rdpid.s: Ditto.
	* gas/i386/x86-64-rdpid.d: Ditto.
	* gas/i386/x86-64-rdpid-intel.d: Ditto.

opcodes/

	* i386-dis.c (prefix_table): Add RDPID instruction.
	* i386-gen.c (cpu_flag_init): Add RDPID flag.
	(cpu_flags): Add RDPID bitfield.
	* i386-opc.h (enum): Add RDPID element.
	(i386_cpu_flags): Add RDPID field.
	* i386-opc.tbl: Add RDPID instruction.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Regenerate.
2016-05-10 21:38:39 +03:00
Thomas Preud'homme
39d911fc3c Use getters/setters to access ARM branch type
2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>

bfd/
	* elf32-arm.c (elf32_arm_size_stubs): Use new macros
	ARM_GET_SYM_BRANCH_TYPE and ARM_SET_SYM_BRANCH_TYPE to respectively get
	and set branch type of a symbol.
	(bfd_elf32_arm_process_before_allocation): Likewise.
	(elf32_arm_relocate_section): Likewise and fix identation along the
	way.
	(allocate_dynrelocs_for_symbol): Likewise.
	(elf32_arm_finish_dynamic_symbol): Likewise.
	(elf32_arm_swap_symbol_in): Likewise.
	(elf32_arm_swap_symbol_out): Likewise.

gas/
	* config/tc-arm.c (arm_adjust_symtab): Use ARM_SET_SYM_BRANCH_TYPE to
	set branch type of a symbol.

gdb/
	* arm-tdep.c (arm_elf_make_msymbol_special): Use
	ARM_GET_SYM_BRANCH_TYPE to get branch type of a symbol.

include/
	* arm.h (enum arm_st_branch_type): Add new ST_BRANCH_ENUM_SIZE
	enumerator.
	(NUM_ENUM_ARM_ST_BRANCH_TYPE_BITS): New macro.
	(ENUM_ARM_ST_BRANCH_TYPE_BITMASK): Likewise.
	(ARM_SYM_BRANCH_TYPE): Replace by ...
	(ARM_GET_SYM_BRANCH_TYPE): This and ...
	(ARM_SET_SYM_BRANCH_TYPE): This in two versions depending on whether
	BFD_ASSERT is defined or not.

ld/
	* emultempl/armelf.em (gld${EMULATION_NAME}_finish): Use
	ARM_GET_SYM_BRANCH_TYPE to get branch type of a symbol.

opcodes/
	* arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
	branch type of a symbol.
	(print_insn): Likewise.
2016-05-10 16:17:04 +01:00
Thomas Preud'homme
15afaa63f3 Add support for ARMv8-M Mainline with DSP extension
2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>

bfd/
	(elf32_arm_merge_eabi_attributes): Add merging logic for
	Tag_DSP_extension.

binutils/
	* readelf.c (display_arm_attribute): Add output for Tag_DSP_extension.
	(arm_attr_public_tags): Define DSP_extension attribute.

gas/
	* NEWS: Document ARMv8-M and ARMv8-M Security and DSP Extensions.
	* config/tc-arm.c (arm_ext_dsp): New feature for Thumb DSP
	instructions.
	(arm_extensions): Add dsp extension for ARMv8-M Mainline.
	(aeabi_set_public_attributes): Memorize the feature bits of the
	architecture selected for Tag_CPU_arch.  Use it to set
	Tag_DSP_extension to 1 for ARMv8-M Mainline with DSP extension.
	(arm_convert_symbolic_attribute): Define Tag_DSP_extension.
	* testsuite/gas/arm/arch7em-bad.d: Rename to ...
	* testsuite/gas/arm/arch7em-bad-1.d: This.
	* testsuite/gas/arm/arch7em-bad-2.d: New file.
	* testsuite/gas/arm/arch7em-bad-3.d: Likewise.
	* testsuite/gas/arm/archv8m-main-dsp-1.d: Likewise.
	* testsuite/gas/arm/archv8m-main-dsp-2.d: Likewise.
	* testsuite/gas/arm/archv8m-main-dsp-3.d: Likewise.
	* testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
	* testsuite/gas/arm/archv8m-main-dsp-5.d: Likewise.
	* testsuite/gas/arm/attr-march-armv8m.main.dsp.d: Likewise.

include/
	* elf/arm.h (Tag_DSP_extension): Define.

ld/
	* testsuite/ld-arm/arm-elf.exp (EABI attribute merging 10 (DSP)): New
	test.
	* testsuite/ld-arm/attr-merge-10b-dsp.s: New file.
	* testsuite/ld-arm/attr-merge-10-dsp.attr: Likewise.
2016-05-10 15:24:10 +01:00
Thomas Preud'homme
d942732e82 Allow extension availability to depend on several architecture bits
2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>

gas/
	* config/tc-arm.c (struct arm_option_extension_value_table): Make
	allowed_archs an array with 2 entries.
	(ARM_EXT_OPT): Adapt to only fill the first entry of allowed_archs.
	(ARM_EXT_OPT2): New macro filling the two entries of allowed_archs.
	(arm_extensions): Use separate entries in allowed_archs when several
	archs are allowed to use an extension and change ARCH_ANY in
	ARM_ARCH_NONE in allowed_archs.
	(arm_parse_extension): Check that, for each allowed_archs entry, all
	bits are set in the current architecture, ignoring ARM_ANY entries.
	(s_arm_arch_extension): Likewise.

include/
	* arm.h (ARM_FSET_CPU_SUBSET): Define macro.
2016-05-10 15:12:11 +01:00
Thomas Preud'homme
16a1fa25be Add support for ARMv8-M security extensions instructions
2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>

gas/
	* config/tc-arm.c (arm_ext_m): Add feature bit ARM_EXT2_V8M_MAIN.
	(arm_ext_v8m_main): New feature set for bit ARM_EXT2_V8M_MAIN.
	(arm_ext_v8m_m_only): New feature set for instructions in ARMv8-M not
	shared with a non M profile architecture.
	(do_rn): New function.
	(known_t32_only_insn): Check opcode against arm_ext_v8m_m_only rather
	than arm_ext_v8m.
	(v7m_psrs): Add ARMv8-M security extensions new special registers.
	(insns): Add ARMv8-M Security Extensions instructions.
	(aeabi_set_public_attributes): Use arm_ext_v8m_m_only instead of
	arm_ext_v8m_m to decide the profile and the Thumb ISA.
	* testsuite/gas/arm/archv8m-cmse.s: New file.
	* testsuite/gas/arm/archv8m-cmse-main.s: Likewise..
	* testsuite/gas/arm/archv8m-cmse-msr.s: Likewise.
	* testsuite/gas/arm/any-cmse.d: Likewise.
	* testsuite/gas/arm/any-cmse-main.d: Likewise.
	* testsuite/gas/arm/archv8m-cmse-base.d: Likewise.
	* testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise.
	* testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise.
	* testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise.
	* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.

include/
	* opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit.
	(ARM_AEXT2_V8M_MAIN): New architecture extension feature set.
	(ARM_ARCH_V8M_MAIN): Use ARM_AEXT2_V8M_MAIN instead of ARM_AEXT2_V8M
	for the high core bits.

opcodes/
	* arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
	Mainline Security Extensions instructions.
	(thumb_opcodes): Add entries for narrow ARMv8-M Security
	Extensions instructions.
	(thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
	instructions.
	(psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
	special registers.
2016-05-10 15:03:38 +01:00
Kyrylo Tkachov
f85d59c306 [ARM][gas] Fix warnings about uninitialised uses and unused const variables
* config/tc-arm.c (fpu_arch_vfp_v1): Mark with ATTRIBUTE_UNUSED.
	(fpu_arch_vfp_v3): Likewise.
	(fpu_arch_neon_v1): Likewise.
	(arm_arch_full): Likewise.
	(parse_neon_el_struct_list): Initialize fields of firsttype.
2016-05-06 13:36:07 +01:00
Claudiu Zissulescu
945e0f82da [ARC] Add SYNTAX_NOP and SYNTAX_1OP for extension instructions
gas/
2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/tc-arc.c (syntaxclass): Add SYNTAX_NOP and SYNTAX_1OP.
	(arc_extinsn): Handle new introduced syntax.
	* testsuite/gas/arc/textinsn1op.d: New file.
	* testsuite/gas/arc/textinsn1op.s: Likewise.
	* doc/c-arc.texi: Document SYNTAX_NOP and SYNTAX_1OP.

opcodes/
2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
	(arcExtMap_genOpcode): Likewise.
	* arc-opc.c (arg_32bit_rc): Define new variable.
	(arg_32bit_u6): Likewise.
	(arg_32bit_limm): Likewise.

include/
2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>

	* opcode/arc.h (ARC_SYNTAX_1OP): Declare
	(ARC_SYNTAX_NOP): Likewsie.
	(ARC_OP1_MUST_BE_IMM): Update defined value.
	(ARC_OP1_IMM_IMPLIED): Likewise.
	(arg_32bit_rc, arg_32bit_u6, arg_32bit_limm): Declare.
2016-05-04 16:18:32 +02:00
Maciej W. Rozycki
22522f880a MIPS/GAS: Fix an ISA override not lifting ABI restrictions
Correct a regression introduced with commit 919731affb ("Add MIPS
.module directive") causing code like:

	.set	mips3
	dli	$2, 0x9000000080000000

to fail assembly with the following error message produced:

Error: number (0x9000000080000000) larger than 32 bits

if built with `mips3' selected as the global ISA (e.g. `-march=mips3').
This is because a `.set' directive doing an ISA override does not lift
the ABI restriction on register sizes if the ISA remains unchanged.
Previously the directive always set register sizes from the ISA chosen,
which is what some code expects.  Restore the old semantics then.

	gas/
	* config/tc-mips.c (code_option_type): New enum.
	(parse_code_option): Return status indicating option type.
	(s_mipsset): Update `parse_code_option' call site accordingly.
	Always set register sizes from the ISA with ISA overrides.
	(s_module): Update `parse_code_option' call site.
	* testsuite/gas/mips/isa-override-1.d: New test.
	* testsuite/gas/mips/micromips@isa-override-1.d: New test.
	* testsuite/gas/mips/mips1@isa-override-1.d: New test.
	* testsuite/gas/mips/mips2@isa-override-1.d: New test.
	* testsuite/gas/mips/mips32@isa-override-1.d: New test.
	* testsuite/gas/mips/mips32r2@isa-override-1.d: New test.
	* testsuite/gas/mips/mips32r3@isa-override-1.d: New test.
	* testsuite/gas/mips/mips32r5@isa-override-1.d: New test.
	* testsuite/gas/mips/mips32r6@isa-override-1.d: New test.
	* testsuite/gas/mips/mips64r2@isa-override-1.d: New test.
	* testsuite/gas/mips/mips64r3@isa-override-1.d: New test.
	* testsuite/gas/mips/mips64r5@isa-override-1.d: New test.
	* testsuite/gas/mips/mips64r6@isa-override-1.d: New test.
	* testsuite/gas/mips/r3000@isa-override-1.d: New test.
	* testsuite/gas/mips/r3900@isa-override-1.d: New test.
	* testsuite/gas/mips/r5900@isa-override-1.d: New test.
	* testsuite/gas/mips/octeon@isa-override-1.d: New test.
	* testsuite/gas/mips/octeon3@isa-override-1.d: New test.
	* testsuite/gas/mips/isa-override-2.l: New list test.
	* testsuite/gas/mips/mips1@isa-override-2.l: New list test.
	* testsuite/gas/mips/mips2@isa-override-2.l: New list test.
	* testsuite/gas/mips/mips32@isa-override-2.l: New list test.
	* testsuite/gas/mips/mips32r2@isa-override-2.l: New list test.
	* testsuite/gas/mips/mips32r3@isa-override-2.l: New list test.
	* testsuite/gas/mips/mips32r5@isa-override-2.l: New list test.
	* testsuite/gas/mips/mips32r6@isa-override-2.l: New list test.
	* testsuite/gas/mips/r3000@isa-override-2.l: New list test.
	* testsuite/gas/mips/r3900@isa-override-2.l: New list test.
	* testsuite/gas/mips/octeon3@isa-override-2.l: New list test.
	* testsuite/gas/mips/octeon3@isa-override-1.l: New stderr
	output.
	* testsuite/gas/mips/isa-override-1.s: New test source.
	* testsuite/gas/mips/r5900@isa-override-1.s: New test source.
	* testsuite/gas/mips/isa-override-2.s: New test source.
	* testsuite/gas/mips/mips1@isa-override-2.s: New test source.
	* testsuite/gas/mips/mips2@isa-override-2.s: New test source.
	* testsuite/gas/mips/mips32@isa-override-2.s: New test source.
	* testsuite/gas/mips/mips32r2@isa-override-2.s: New test source.
	* testsuite/gas/mips/mips32r3@isa-override-2.s: New test source.
	* testsuite/gas/mips/mips32r5@isa-override-2.s: New test source.
	* testsuite/gas/mips/mips32r6@isa-override-2.s: New test source.
	* testsuite/gas/mips/r3000@isa-override-2.s: New test source.
	* testsuite/gas/mips/r3900@isa-override-2.s: New test source.
	* testsuite/gas/mips/octeon3@isa-override-2.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
2016-04-22 01:22:29 +01:00
Trevor Saunders
e6c7cdec06 update many old style function definitions
This includes regenerating a bunch of files in opcodes/ with trunk cgen.

gprof/ChangeLog:

2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* basic_blocks.c: Update old style function definitions.
	* cg_arcs.c: Likewise.
	* cg_print.c: Likewise.
	* gen-c-prog.awk: Likewise.
	* gmon_io.c: Likewise.
	* hertz.c: Likewise.
	* hist.c: Likewise.
	* sym_ids.c: Likewise.

bfd/ChangeLog:

2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* cache.c: Update old style function definitions.
	* elf32-m68k.c: Likewise.
	* elf64-mmix.c: Likewise.
	* stab-syms.c: Likewise.

opcodes/ChangeLog:

2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* alpha-dis.c: Regenerate.
	* crx-dis.c: Likewise.
	* disassemble.c: Likewise.
	* epiphany-opc.c: Likewise.
	* fr30-opc.c: Likewise.
	* frv-opc.c: Likewise.
	* ip2k-opc.c: Likewise.
	* iq2000-opc.c: Likewise.
	* lm32-opc.c: Likewise.
	* lm32-opinst.c: Likewise.
	* m32c-opc.c: Likewise.
	* m32r-opc.c: Likewise.
	* m32r-opinst.c: Likewise.
	* mep-opc.c: Likewise.
	* mt-opc.c: Likewise.
	* or1k-opc.c: Likewise.
	* or1k-opinst.c: Likewise.
	* tic80-opc.c: Likewise.
	* xc16x-opc.c: Likewise.
	* xstormy16-opc.c: Likewise.

ld/ChangeLog:

2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* emultempl/scoreelf.em: Likewise.

binutils/ChangeLog:

2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* resres.c: Likewise.

gas/ChangeLog:

2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* cgen.c: Likewise.
	* config/tc-bfin.c: Likewise.
	* config/tc-ia64.c: Likewise.
	* config/tc-mep.c: Likewise.
	* config/tc-metag.c: Likewise.
	* config/tc-nios2.c: Likewise.
	* config/tc-rl78.c: Likewise.
2016-04-20 07:04:49 -04:00
Matthew Wahab
50cc854c48 [AArch64] Support RAS extension for ARMv8 onwards.
The RAS extension was introduced as part of the ARMv8.2 architecture
where it is a required feature. It is also available as an optional
feature for ARMv8 and ARMv8.1. In binutils, the RAS extension is
currently enabled by default for -march=armv8.2-a but is not available
for -march=armv8 or -march=armv8.1-a.

This patch adds the feature extension '+ras' to enable the RAS extension
for ARMv8 and ARMv8.1, it is disabled by default.

gas/
2016-04-20  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (aarch64_features): Add "ras".
	* doc/c-aarch64.texi (AArch64 Extensions): Add "ras".
	* testsuite/gas/aarch64/armv8-ras-1.d: New.
	* testsuite/gas/aarch64/armv8-ras-1.s: New.
	* testsuite/gas/aarch64/illegal-ras-1.d: New.
	* testsuite/gas/aarch64/illegal-ras-1.s: New.

Change-Id: I824fb9bc8cf846bcc03aa17a726efb1350d78b9d
2016-04-20 09:31:49 +01:00
Andrew Burgess
644aca26b5 Revert "gas/arc: Make .cpu directive case-insensitive"
This reverts commit 9a452709fe.

This change was committed as obvious, but it has been rightly been
pointed out to me that this change is not obvious, and as such I am
reverting it.

gas/ChangeLog:

	Revert prevous change.
	* config/tc-arc.c (arc_option): Make .cpu directive
	case-sensitive again.
2016-04-17 23:22:15 +01:00
Andrew Burgess
9a452709fe gas/arc: Make .cpu directive case-insensitive
gas/ChangeLog:

	* config/tc-arc.c (arc_option): Make .cpu directive
	case-insensitive.
2016-04-16 16:21:32 +01:00
Andrew Burgess
5e001f26ad gas/arc: Support NPS400 in .cpu directive
gas/ChangeLog:

	* config/tc-arc.c (arc_option): Allow NPS400 in .cpu directive.
2016-04-16 16:19:40 +01:00