* i386-dis.c: Don't print opcode suffix when we can figure out the
size (and gas can!) by register operands, or from the default
size.
(putop): Handle 'A', 'B', 'L', 'P', 'Q', 'R' macros. Rename 'C'
macro to 'E'.
(dis386, dis386_twobyte, grps): Use new suffix macros.
(dis386): Correct imul Ib to imul sIb. Change jnl to jge to be
consistent. Add suffix for call, jmp, lcall, ljmp, iret. Reverse
order of cmps operands to agree with Intel docs. Correct operand
of aad and aam (Ib -> sIb). Change ud2b from 0fb8 to 0fb9 to
agree with Intel docs.
(print_insn_x86): Print orphan fwait before other prefixes.
Return correct byte count for orphan fwait with prefixes. Don't
print `bound' operands in reverse order.
(ckprefix): Stop accumulating prefixes if we get fwait.
(OP_DIR): Print `$' before Ap operands of ljmp, lcall.
Fix problems when bfd_vma is wider than long.
* i386-dis.c: Make op_address and start_pc unsigned.
(set_op): Make parameter unsigned.
(print_insn_x86): Cast to bfd_vma when passing a value to
print_address_func.
* ns32k-dis.c (CORE_ADDR): Don't define.
(print_insn_ns32k): Change type of addr to bfd_vma. Use
bfd_scan_vma to read back address.
(print_insn_arg): Change type of addr to bfd_vma. Use sprintf_vma
to format it.
* m68k-dis.c (COERCE32): Cast to bfd_signed_vma to avoid overflow.
(NEXTULONG): New definition.
(print_insn_m68k): Avoid overflow when computing third argument of
print_insn_arg.
(print_insn_arg): Use NEXTULONG to fetch 32 bit address values.
Use disp instead of val to store offset values.
(print_indexed): Use base_disp instead of word to store base
displacement, to avoid overflow.
* m10300-dis.c (disassemble): Cast value to long when computing
pc-relative address, to get correct sign extension.
* i386-dis.c: Combine aflag and dflag into sizeflag. Change OP_*
functions to void.
(OP_DSreg): Rename from OP_DSSI.
(OP_ESreg): Rename from OP_ESDI.
(Xb, Xv, Yb, Yv): Use index reg code, not b_mode or v_mode.
(DSBX): Define.
(append_seg): Rename from append_prefix.
(ptr_reg): New function.
(dis386): Add S suffix to pushf, popf, ret, lret, enter, leave.
Add DSBX for xlat.
(PREFIX_ADDR): Rename from PREFIX_ADR.
(float_reg): Add non-broken opcodes for people who don't want
UNIXWARE_COMPAT.
* ppc-opc.c (powerpc_macros): Support shifts and rotates of size
0; produce error message for shifts of size 32 (or 64 for 64-bit
shifts), because the hardware doesn't support them.
Thu May 7 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
* mips-opc.c (teq,tge,tgeu,tlt,tltu,tne): Added three-operand
variety of ISA2 instructions to set bottom ten bits of trap code.
(asm_hash_table_entries): New variable.
(cgen_asm_init): Free asm_hash_table_entries.
(hash_insn_array,hash_insn_list): New functions.
(build_asm_hash_table): Use them. Hash macro insns as well.
(cgen_asm_lookup_insn): Update.
* cgen_dis.c (cgen_current_opcode_table): Renamed from ..._data.
(dis_hash_table_entries): New variable.
(cgen_dis_init): Free dis_hash_table_entries.
(hash_insn_array,hash_insn_list): New functions.
(build_dis_hash_table): Use them. Hash macro insns as well.
(cgen_dis_lookup_insn): Update.
* cgen-opc.c (cgen_current_opcode_table): Renamed from ..._data.
(cgen_set_cpu,cgen_hw_lookup,cgen_insn_count): Update.
(cgen_macro_insn_count): New function.
* cgen-opc.in (@arch@_cgen_lookup_insn): New arg alias_p.
All callers updated. Sanity check result of extract fn.
(@arch@_cgen_get_insn_operands): Change result type to void.
Delete args insn_value, length. New arg fields. All callers updated.
(@arch@_cgen_lookup_get_insn_operands): New function.
