A lot of cpu state is stored in global variables, as is memory handling.
The sim_size support needs unwinding at some point. But at least this
is an improvement on the status quo.
Looks like historical restructuring in this dir lost the d10v-elf subdir
and no one noticed in the meantime. Re-add it to the testsuite.
There are some failures, but better some tests get run than none at all.
Since the sim doesn't have any debug support in it, we can only exit
cleanly. But this is still better than nothing.
Change the default microblaze sim to not dump the debug load output
when running. No other does this, and it breaks the testsuite.
If a test doesn't write anything at all to stdout, the current test
framework can't support that. Even if you put a blank output line:
# output:
the setup happily clobbers that with a default pass/fail string.
Tweak the parsing logic so we only set the output to pass/fail when
the test has no output marker.
Since the testsuite subdir has to handle dynamic arch values already,
there's no real value in requiring arches to opt in to it. Most have
a testsuite now anyways, and we're requiring it in the future.
I meant for this script to be +x, but missed when doing the initial CVS
commit. It wasn't possible to fix w/CVS, but it is w/git, so do it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-12-03 Mike Frysinger <vapier@gentoo.org>
* run-tests.sh: Add +x file mode.
Since the sim has a few fake debug insns that the hardware does not, we
need to check for those before attempting to run them. Otherwise we'll
randomly trigger the sim debug asserts/aborts/halts insns. On the
hardware, these are proper invalid insns, and the table catches that.
The main body of the "all insn" test is executed once per tested insn, and
we test millions of insns here. Any shrinkage we can do in this loop will
speed things up nicely (since it's multiplied per tested insn).
To that end, simplify the end-of-table test into one less insn, and omit
the SSYNC when we build for the sim. When we build to run on the hardware,
this insn matters, but the sim doesn't have write store buffers in the chip
that might get in the way (memory writes are atomic).
Since these insns run in usermode, there should be no need to setup
RET[ENI] to safe values. They won't be dereferenced, and any insn
that returns via them are valid only in supervisor mode. Since this
is in the main exception code path, saving any insn at all is good
as it gets multiplied quickly (as in O(n^2) times).
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
From: Jayant R. Sonar <Jayant.Sonar@kpitcummins.com>
This patch adds simulator support for handling the armv7 instructions
'movw (immediate)' and 'movt'.
Compiler frequently use these instructions to load the 32bit addresses of
global variables, string pointers etc. into the general registers.
In absence of support of these instructions:
1. GDB run simulator fails to print even simple "hello world" string
on console.
2. Loading of global variable addresses into the registers fail causing
arithmetic operation failures.
Patch has been regression tested for arm-none-eabi (-march=armv7-a).
Two modifications:
1. The addition of 2013 to the copyright year range for every file;
2. The use of a single year range, instead of potentially multiple
year ranges, as approved by the FSF.
These are randomly generated tests to track down issues in ASTAT
handling with shift insns.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Now that we check for valid sub-insns in parallel insns, we can
enable the tests that explicitly validate those code paths.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Now that we have the se_all helpers together and working, we can see
what pieces are duplicated in each test and unify them in the common
header file.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Similar to logic in the cris exp, attempt a simple compile and if it fails
(presumably due to the compiler being broken), skip all the related tests.
Fortunately, most tests (~600 out of ~800) are pure assembly, so people should
still get pretty good coverage.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The current se_all*opcodes tests are very similar in how they work.
In preparation for adding more tests along these lines, unify the
common bits into a framework that others can include and build off
of easily.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The 32bit allopcodes test had quite a bit of optimization added to it
so that it ran in a reasonable amount of time out of uncached memory.
Port those changes over to the 16bit test so the two share common code.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
