Alan Modra
1f42f8b31d
gas/
...
* config/tc-crx.c: Include bfd_stdint.h.
(getconstant): Remove irrelevant comment. Don't fail due to
sign-extension of int mask.
(check_range): Rewrite using unsigned arithmetic throughout.
opcodes/
* crx-dis.c (print_arg): Mask constant to 32 bits.
* crx-opc.c (cst4_map): Use int array.
include/opcode/
* crx.h (cst4_map): Update declaration.
2012-02-27 06:37:40 +00:00
Nick Clifton
e4e42b45d5
Upgrade header files to use GPLv3
2010-04-15 10:26:09 +00:00
Nick Clifton
e172dbf8aa
Update the address and phone number of the FSF organization
2005-05-10 10:21:13 +00:00
Tomer Levi
9019af69c4
2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
...
* opcode/crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
Remove redundant instruction types.
(struct argument): X_op - new field.
(struct cst4_entry): Remove.
(no_op_insn): Declare.
2004-11-29 16:36:50 +00:00
Tomer Levi
c953b56c16
2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
...
* opcode/crx.h (enum argtype): Rename types, remove unused types.
2004-11-05 10:58:22 +00:00
Tomer Levi
5531e44c20
(enum reg): Rearrange registers, remove 'ccfg' and 'pc'.
...
(enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
(enum operand_type): Rearrange operands, edit comments.
replace us<N> with ui<N> for unsigned immediate.
replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped displacements (respectively).
replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
(instruction type): Add NO_TYPE_INS.
(instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
(operand_entry): New field - 'flags'.
(operand flags): New.
2004-10-27 10:17:39 +00:00
Tomer Levi
645ea12c46
2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
...
* opcode/crx.h (operand_type): Remove redundant types i3, i4, i5, i8, i12.
Add new unsigned immediate types us3, us4, us5, us16.
2004-10-25 09:44:27 +00:00
Nick Clifton
48c9f030c9
Add support for CRX co-processor opcodes
2004-10-07 14:18:17 +00:00
Nick Clifton
1fe1f39c06
Add new port: crx-elf
2004-07-07 17:28:53 +00:00
