Commit graph

2068 commits

Author SHA1 Message Date
Andrew Cagney
e0709f5044 New simulator. 2000-07-27 11:23:39 +00:00
Andrew Cagney
3c765a5497 From 2000-06-25 Stephane Carrez <Stephane.Carrez@worldnet.fr>:
* sim-bits.h (_MSB_16, _LSB_16): Define for 16-bit targets.
(MASK, LSBIT, MSBIT): Likewise and use _MSB_16 and _LSB_16.
(EXTENDED): Define for 16-bit word size.
* sim-bits.c (LSEXTRACTED, MSEXTRACTED, LSINSERTED,
MSINSERTED, LSSEXT, MSSEXT): Implement for 16-bit word size.
* sim-types.h: Added support for 16-bit targets.
2000-07-27 11:07:01 +00:00
Andrew Cagney
0a17cd5944 * compile.c (decode): Distinguish inc/dec.[wl] and adds/subs
correctly.
2000-07-27 09:39:50 +00:00
Andrew Cagney
a28c02cd2b * m16.igen (break): Call SignalException not sim_engine_halt. 2000-07-20 00:02:22 +00:00
Fernando Nasser
0a4321b903 2000-07-14 Fernando Nasser <fnasser@cygnus.com>
* wrapper.c (sim_create_inferior): Fix typo in the previous patch.
2000-07-14 21:27:15 +00:00
Fernando Nasser
64a1067567 2000-07-14 Fernando Nasser <fnasser@cygnus.com>
* wrapper.c (sim_create_inferior): Reset mode to ARM when creating a
        new inferior.
2000-07-14 16:49:46 +00:00
Nick Clifton
0dbdd75378 Change minimum loop size limit to 0x10 (103792) 2000-07-05 21:40:11 +00:00
Alexandre Oliva
ae3c7619e1 * armvirt.c (ABORTS): Do not define. 2000-07-04 08:00:19 +00:00
Alexandre Oliva
1e6b544a97 * armdefs.h (struct ARMul_State): Add is_StrongARM.
(ARM_Strong_Prop, STRONGARM): Define.
* arminit.c (ARMul_NewState): Reset is_StrongARM.
(ARMul_SelectProcessor): Set is_StrongARM.
* wrapper.c (sim_create_inferior): Use bfd machine type to
determine processor type to emulate.
* armemu.h (BUSUSEDINCPCS, BUSUSEDINCPCN): Don't increment PC
when emulating StrongARM.
2000-07-04 07:18:18 +00:00
Alexandre Oliva
66210567f0 * armemu.c (ARMul_Emulate, t_undefined): Proceed to next insn. 2000-07-04 06:54:48 +00:00
Alexandre Oliva
e063aa3bd8 * armemu.h (INSN_SIZE): New macro.
(SET_ABORT): Save CPSR in SPSR and set LR.
* armemu.c (ARMul_Emulate, isize): Set to INSN_SIZE.
(WriteR15, WriteSR15): Do not discard bit 1 in Thumb mode.
* arminit.c (ARMul_Abort): Use new SETABORT and INSN_SIZE.
2000-07-04 06:52:30 +00:00
Alexandre Oliva
13b6dd6f68 * armemu.c (LoadSMult): Use WriteR15() to discard the least
significant bits of PC.
2000-07-04 06:39:39 +00:00
Alexandre Oliva
892c6b9d8f * armemu.h (WRITEDESTB): New macro.
* armemu.c (ARMul_Emulate26, bl): Use WriteR15Branch() to
modify PC.  Moved the existing logic...
(WriteR15Branch): ... here.  New function.
(WriteR15, WriteSR15): Drop the two least significant bits.
(LoadSMult): Use WriteR15Branch() to modify PC.
(LoadMult): Use WRITEDESTB() instead of WRITEDEST().
2000-07-04 06:35:36 +00:00
Alexandre Oliva
cf52c765b0 * armemu.h (GETSPSR): Call ARMul_GetSPSR().
* armsupp.c (ARMul_CPSRAltered): Zero out bits as they're
extracted from state->Cpsr, but preserve the unused bits.
(ARMul_GetCPSR): Get bits preserved in state->Cpsr.
(ARMul_GetSPSR, ARMul_FixCPSR): Use ARMul_GetCPSR() to
get the full CPSR word.
2000-07-04 06:19:29 +00:00
Alexandre Oliva
4ef2594f4e * armemu.h (PSR_FBITS, PSR_SBITS, PSR_XBITS, PSR_CBITS): New.
(SETPSR_F, SETPSR_S, SETPSR_X, SETPSR_C): New macros.
(SETPSR, SET_INTMODE, SETCC): Removed.
* armsupp.c (ARMul_FixCPSR, ARMul_FixSPSR): Do not test bit
mask.  Use SETPSR_* to modify PSR.
(ARMul_SetCPSR): Load all bits from value.
* armemu.c (ARMul_Emulate, msr): Do not test bit mask.
2000-07-04 06:06:30 +00:00
Alexandre Oliva
e62263b8ec * armemu.c (ARMul_Emulate): Compute writeback value before
loading, since the offset register may be the destination
register.
2000-07-04 05:30:43 +00:00
Alexandre Oliva
b0eae074ca * armdefs.h (SYSTEMBANK): Define as USERBANK.
* armsupp.c (ARMul_SwitchMode): Remove SYSTEMBANK cases.
2000-07-04 05:16:20 +00:00
Andrew Cagney
6c29acca43 TIc80 simulator. 2000-07-04 05:00:54 +00:00
Andrew Cagney
80ee11fa0e Fix MOVN.fmt and MOVZ.fmt, need to test GPR[RT]. 2000-07-04 02:32:58 +00:00
Frank Ch. Eigler
7fb283bce2 * verbosity reduction
2000-06-23  Frank Ch. Eigler  <fche@redhat.com>

	* cgen-trace.h (TRACE_USEFUL_MASK): Remove TRACE_EVENTS_IDX.
2000-06-24 14:47:54 +00:00
Frank Ch. Eigler
ab42ee127d * build cleanliness fix
2000-06-24  Frank Ch. Eigler  <fche@redhat.com>

	From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
	* Makefile.in (distclean): Clean cconfig.h also.
2000-06-24 14:37:57 +00:00
Andrew Cagney
673388c077 Fix printf arguments. 2000-06-23 12:39:41 +00:00
Alexandre Oliva
f9c22bc3a4 * armemu.c (Multiply64): Fix computation of flag N. 2000-06-22 20:42:34 +00:00
Alexandre Oliva
ee9a777240 * armemu.c (MultiplyAdd64): Fix computation of flag N. 2000-06-22 20:03:32 +00:00
Frank Ch. Eigler
97ee9e5aa9 * build fix
2000-06-20  Frank Ch. Eigler  <fche@redhat.com>

	* compile.c: Don't include "wait.h".
	(sim_resume): Use local SIM_WIFEXITED and SIM_WIFSIGNALED macros
	instead of WIF* from host.
2000-06-20 21:12:33 +00:00
Alexandre Oliva
fe47e8dfd3 * armemu.h (NEGBRANCH): Do not overwrite the two most significant
bits of the offset.
2000-06-20 09:36:12 +00:00
Nick Clifton
bcd6576654 Add strongarm tests 2000-06-19 00:56:04 +00:00
Frank Ch. Eigler
98ecb0a78b * "Dont" -> "Don't"
2000-06-13  Frank Ch. Eigler  <fche@redhat.com>

	* compile.c, writecode.c: Correct typo.
2000-06-13 20:32:01 +00:00
Jeff Law
0ef9643e5e 2000-06-13 Kazu Hirata <kazu@hxi.com>
* compile.c: Fix formatting.
2000-06-13 19:54:56 +00:00
Joern Rennecke
2532761bdf sh-dsp support, simulator speedup by using host byte order:
* Makefile.in (interp.o): Depends on ppi.c .
	(ppi.c): New rule.
	* gencode.c (printonmatch, think, genopc): Deleted.
	(MAX_NR_STUFF): Now 42.
	(tab): Add SH-DSP CPU instructions.
	Amalgamate ldc / stc / lds / sts instructions with similar
	bit patterns.  Fix opcodes of stc Rm_BANK,@-<REG_N>.
	Fix semantics of lds.l @<REG_N>+,MACH (no sign extend).
	(movsxy_tab): New array.
	For movs, change MMMM field to GGGG, and mmmm field to MMMM.
	Added entries for movx, movy and parallel processing insns.
	(ppi_tab): New array.
	(qfunc): Stabilize sort.
	(expand_opcode): Handle [01][01]NN, [01][01]xx and [01][01]yy.
	Handle 'M', 'G' 's' 'X', 'a', 'Y' and 'A'.
	(dumptable): Now takes three arguments.  Changed all callers.
	Emit just one contigous jump table.
	(filltable): Now takes an argument.  Changed all callers.
	Make index static.
	(ppi_moves, expand_ppi_code, ppi_filltable, ppi_gensim): New functions.
	(gensim_caselist): New function, broken out of gensim.
	Handle opcode fields 'x', 'y', 's', 'M', 'G', 'X', 'a', and 'Y'.
	Handle ref '9'.
	(gensim): Handle 'N' in code field and '8' in refs field.
	Call gensim_caselist - twice.
	(ppi_index): New static variable.
	(main): Unsupport default action.
	Add dsp support for -x / -s option.  Add -p option.
	* interp.c (sh_jump_table, sh_dsp_table, ppi_table): Declare.
	(saved_state_type): Rearrange to allow amalgamated ldc / stc /
	lds / sts to work efficiently.
	(target_dsp): New static variable.
	(GBR, VBR, SSR, SPC, MACH, MACL): Reflect saved_state_type change.
	(FPUL, Rn_BANK, SET_Rn_BANK, M, Q, S, T, SR_BL, SR_RB): Likewise.
	(SR_MD, SR_RC, SET_SR_BIT, GET_SR, SET_RC, GET_FPSCR): Likewise.
	(RS, RE, MOD, MOD_ME, DSP_R): Likewise.
	(set_fpscr1): Likewise.  Use target_dsp to check for dsp.
	(MOD_MSi, SIG_BUS_FETCH): Deleted.
	(CREG, SREG, PR, SR_MASK_DMY, SR_MASK_DMX, SR_DMY): New macros.
	(SR_DMX, DSR, MOD_DELTA, GET_DSP_GRD): Likewise.
	(SET_MOD): Reflect saved_state_type change.  Set MOD_DELTA instead
	of MOD_MS, and encode SR_DMY / SR_DMX into high word of MOD_ME.
	(set_sr): Reflect saved_state_type change.  Fix SR_RB handling.
	Use SET_MOD.
	(MA, L, TL, TB): Now controlled by ACE_FAST.
	(SEXT32): Just cast to int.
	(SIGN32): Fixed to only shift by 31.
	(CHECK_INSN_PTR): SIGBUS at insn fetch now represented by insn_end 0.
	(ppi_insn): Declare.
	(ppi.c): Include.
	(init_dsp): Set target_dsp.  When it changes, switch end of
	sh_jump_table with sh_dsp_table.
	(sim_resume) Don't declare sh_jump_table0.  Use sh_jump_table instead.
	Don't Declare PR if it's #defined.
	Fix single-stepping (Was broken in Mar  6 16:59:10 patch).
	(sim_store_register, sim_read_register): Translate accesses to
	reflect saved_state_type change.

	* interp.c (set_sr): Set sr.
	(SET_RC, MOD, MOD_MS, MOD_ME, SET_MOD, MOD_MS, MOD_ME): New macros.
	(set_fpscr1): Don't bank-switch fpu registers when simulating sh-dsp.
	(DSP_R): Fix definition.
	(sim_resume): Remove outdated SET_SR use.

	* interp.c (saved_state): New members for struct member asregs:
	rs, re, insn_end, xram_start, yram_start.
	(struct loop_bounds): New struct.
	(SKIP_INSN): New macro.
	(get_loop_bounds): New function.
	(endianw): Renamed to global_endianw.
	(maskw): negated bits.
	(PC): Now insn_ptr.
	(SR_MASK_RC, SR_RC_INCREMENT, SR_RC, RAISE_EXCEPTION): New macros.
	(RS, RE, DSP_R, DSP_GRD, A1, A0, X0, X1, Y0, Y1, M0, A1G): Likewise.
	(M1, A0G, RIAT, PT2H, PH2T, SET_NIP, CHECK_INSN_PTR): Likewise.
	(SIG_BUS_FETCH): Likewise
	(raise_exception, riat_fast): New functions.
	(raise_buserror, sim_stop): Use raise_exception.
	(PROCESS_SPECIAL_ADDRESS): Use xram_start / yram_start.
	(BUSERROR, WRITE_BUSERROR, READ_BUSERROR):
	Reverse sense of mask argument.
	(FP_OP, set_dr): Use RAISE_EXCEPTION.
	(wlat_fast, wwat_fast, wbat_fast, rlat_fast, rwat_fast, rbat_fast):
	Declare.  Remove redundant masking.
	(wwat_fast, rwat_fast): Add argument endianw.  Changed callers.
	(MA): Updated for change pc -> PC.
	(Delay_Slot): Use RIAT.
	(empty): Deleted.
	(trap): Remove argument little_endian.  Add argument endianw.
	Changed all callers.  Use raise_exception.
	(macw): Add argument endainw.  Changed all callers.
	(init_dsp): New function, extended after broken out of init_pointers.
	(sim_resume): Replace pc with insn_ptr.  Replace little_endian with
	endianw.  Replace nia with nip.  Reverse sense of maskb / maskw /
	maskl.  Implement logic for zero-overhead loops.  Don't try to
	interpret garbage when getting a SIGBUS at insn fetch.
	(sim_open): Call init_dsp.
	* gencode.c (tab): Use SET_NIP instead of nia = .  Use PH2T / PT2H /
	RAISE_EXCEPTION where appropriate.
	Add extra cycles for brai, braf , bsr, bsrf, jmp, jsr.

	* interp.c (sim_store_register, sim_fetch_register):
	Do proper endianness switch.

	* interp.c (saved_state_type): New members for struct member asregs:
	xymem_select, xmem, ymem, xmem_offset, ymem_offset.
	(special_address): Delete.
	(BUSERROR): Now a two-argument predicate.
	(PROCESS_SPECIAL_ADDRESS, WRITE_BUSERROR, READ_BUSERROR): New macros.
	(wlat_little, wwat_little, wbat_any, wlat_big, wwat_big): Delete.
	(process_wlat_addr, process_wwat_addr): New functions.
	(process_wbat_addr, process_rlat_addr, process_rwat_addr): Likewise.
	(process_rbat_addr): Likewise.
	(wlat_fast, wwat_fast, wbat_fast): Use WRITE_BUSERROR.
	(rlat_little, rwat_little, rbat_any, rlat_big, rwat_big): Delete.
	(rlat_fast, rwat_fast, rbat_fast): Use READ_BUSERROR.
	(RWAT, RLAT, RBAT, WWAT, WLAT, WBAT): Delete SLOW versions.
	(do_rdat, trap): Delete SLOW code.
	(SEXT32, SIGN32): New macros.
	(swap, swap16): Now integer in - integer out.  Changed all callers.
	(strswaplen, strnswap): Delete SLOW versions.
	(init_pointers): Initialize dsp memory selection (preliminary).
	(sim_store_register, sim_fetch_register): Use swap instead of
	big / little endian read / write functions.

	* interp.c (maskl): Deleted.
	(endianw, endianb): New variables.
	(special_address): Now inline.
	(bp_holder): Put raising of buserror there, rename to:
	(raise_buserror).
	(BUSERROR): Now yields a value.  Changed all users.
	(wbat_big): Delete.
	(wlat_fast, wwat_fast, wbat_fast): New functions.
	(rlat_fast, rwat_fast, rbat_fast): Likewise.
	(RWAT, RLAT, RBAT, WWAT, WLAT, WBAT): Use new functions.
	(do_rdat, do_wdat): Likewise.  Take maskl argument instead of
	little_endian one.  Changed caller macros.
	(swap, swap16): Use w[rw]lat_big / w[rw]lat_little directly.
	(strswaplen, strnswap): New functions.
	(trap): Use them to fix up endian mismatches;
	disable SYS_execve and SYS_execv; fix double address translation for
	SYS_pipe and SYS_stat.
	(sym_write, sym_read): Add endianness translation.
	(sym_store_register, sym_fetch_register): Add maskl local variable.
	(sim_open): Set endianw and endianb.
2000-06-07 14:59:16 +00:00
Nick Clifton
896ad91016 Remove illegal instruciton pattern, since it is the same as the breakpoint
pattern.
2000-05-30 18:36:57 +00:00
Nick Clifton
c1a72ffdd6 Add support for v4 SystemMode. 2000-05-30 17:13:37 +00:00
Nick Clifton
4c0deff44c Define GPR_CLEAR 2000-05-29 19:38:39 +00:00
Nick Clifton
67f5c7ef0f fix spelling mistake in comment 2000-05-29 19:35:50 +00:00
Nick Clifton
33ae44dea2 Remove RCS tags to make synchronisation easier. 2000-05-29 19:34:13 +00:00
Nick Clifton
86e0da7a81 Use GPR_CLEAR instead of GPR_SET 2000-05-29 19:28:53 +00:00
Nick Clifton
f23b768a5c replace GPR_SET with GPR_CLEAR 2000-05-29 19:26:48 +00:00
Nick Clifton
ceec355905 minor formatting tweaks to aid syncronisation 2000-05-29 19:05:41 +00:00
Andrew Cagney
eb2d80b469 Change profiling so that it is enabled by default. Re-generate everything. 2000-05-24 04:39:50 +00:00
Nick Clifton
3463c3fbbb Add special case handling when GDB set CPSR register 2000-05-23 23:52:46 +00:00
Andrew Cagney
781c552e2d sigrc wasn't initialized before being passed to sim_resume(). 2000-05-23 11:34:27 +00:00
Alexandre Oliva
e33c036475 * am33.igen: Fix leading comments of SP-relative offset insns that
referred to other registers.  Make their offsets unsigned.
2000-05-22 20:34:09 +00:00
Alexandre Oliva
24a39d88a2 * mn10300_sim.h (genericAdd, genericSub, genericCmp, genericOr,
genericXor, genericBtst): Use `unsigned32'.
* op_utils.c: Likewise.
* mn10300.igen, am33.igen: Use `unsigned32', `signed32',
`unsigned64' or `signed64' where type width is relevant.
2000-05-18 22:56:28 +00:00
Joern Rennecke
63978407cb sh-dsp support, simulator speedup by using host byte order:
sim:
	* Makefile.in (interp.o): Depends on ppi.c .
	(ppi.c): New rule.
	* gencode.c (printonmatch, think, genopc): Deleted.
	(MAX_NR_STUFF): Now 42.
	(tab): Add SH-DSP CPU instructions.
	Amalgamate ldc / stc / lds / sts instructions with similar
	bit patterns.  Fix opcodes of stc Rm_BANK,@-<REG_N>.
	Fix semantics of lds.l @<REG_N>+,MACH (no sign extend).
	(movsxy_tab): New array.
	For movs, change MMMM field to GGGG, and mmmm field to MMMM.
	Added entries for movx, movy and parallel processing insns.
	(ppi_tab): New array.
	(qfunc): Stabilize sort.
	(expand_opcode): Handle [01][01]NN, [01][01]xx and [01][01]yy.
	Handle 'M', 'G' 's' 'X', 'a', 'Y' and 'A'.
	(dumptable): Now takes three arguments.  Changed all callers.
	Emit just one contigous jump table.
	(filltable): Now takes an argument.  Changed all callers.
	Make index static.
	(ppi_moves, expand_ppi_code, ppi_filltable, ppi_gensim): New functions.
	(gensim_caselist): New function, broken out of gensim.
	Handle opcode fields 'x', 'y', 's', 'M', 'G', 'X', 'a', and 'Y'.
	Handle ref '9'.
	(gensim): Handle 'N' in code field and '8' in refs field.
	Call gensim_caselist - twice.
	(ppi_index): New static variable.
	(main): Unsupport default action.
	Add dsp support for -x / -s option.  Add -p option.
	* interp.c (sh_jump_table, sh_dsp_table, ppi_table): Declare.
	(saved_state_type): Rearrange to allow amalgamated ldc / stc /
	lds / sts to work efficiently.
	(target_dsp): New static variable.
	(GBR, VBR, SSR, SPC, MACH, MACL): Reflect saved_state_type change.
	(FPUL, Rn_BANK, SET_Rn_BANK, M, Q, S, T, SR_BL, SR_RB): Likewise.
	(SR_MD, SR_RC, SET_SR_BIT, GET_SR, SET_RC, GET_FPSCR): Likewise.
	(RS, RE, MOD, MOD_ME, DSP_R): Likewise.
	(set_fpscr1): Likewise.  Use target_dsp to check for dsp.
	(MOD_MSi, SIG_BUS_FETCH): Deleted.
	(CREG, SREG, PR, SR_MASK_DMY, SR_MASK_DMX, SR_DMY): New macros.
	(SR_DMX, DSR, MOD_DELTA, GET_DSP_GRD): Likewise.
	(SET_MOD): Reflect saved_state_type change.  Set MOD_DELTA instead
	of MOD_MS, and encode SR_DMY / SR_DMX into high word of MOD_ME.
	(set_sr): Reflect saved_state_type change.  Fix SR_RB handling.
	Use SET_MOD.
	(MA, L, TL, TB): Now controlled by ACE_FAST.
	(SEXT32): Just cast to int.
	(SIGN32): Fixed to only shift by 31.
	(CHECK_INSN_PTR): SIGBUS at insn fetch now represented by insn_end 0.
	(ppi_insn): Declare.
	(ppi.c): Include.
	(init_dsp): Set target_dsp.  When it changes, switch end of
	sh_jump_table with sh_dsp_table.
	(sim_resume) Don't declare sh_jump_table0.  Use sh_jump_table instead.
	Don't Declare PR if it's #defined.
	Fix single-stepping (Was broken in Mar  6 16:59:10 patch).
	(sim_store_register, sim_read_register): Translate accesses to
	reflect saved_state_type change.

	* interp.c (set_sr): Set sr.
	(SET_RC, MOD, MOD_MS, MOD_ME, SET_MOD, MOD_MS, MOD_ME): New macros.
	(set_fpscr1): Don't bank-switch fpu registers when simulating sh-dsp.
	(DSP_R): Fix definition.
	(sim_resume): Remove outdated SET_SR use.

	* interp.c (saved_state): New members for struct member asregs:
	rs, re, insn_end, xram_start, yram_start.
	(struct loop_bounds): New struct.
	(SKIP_INSN): New macro.
	(get_loop_bounds): New function.
	(endianw): Renamed to global_endianw.
	(maskw): negated bits.
	(PC): Now insn_ptr.
	(SR_MASK_RC, SR_RC_INCREMENT, SR_RC, RAISE_EXCEPTION): New macros.
	(RS, RE, DSP_R, DSP_GRD, A1, A0, X0, X1, Y0, Y1, M0, A1G): Likewise.
	(M1, A0G, RIAT, PT2H, PH2T, SET_NIP, CHECK_INSN_PTR): Likewise.
	(SIG_BUS_FETCH): Likewise
	(raise_exception, riat_fast): New functions.
	(raise_buserror, sim_stop): Use raise_exception.
	(PROCESS_SPECIAL_ADDRESS): Use xram_start / yram_start.
	(BUSERROR, WRITE_BUSERROR, READ_BUSERROR):
	Reverse sense of mask argument.
	(FP_OP, set_dr): Use RAISE_EXCEPTION.
	(wlat_fast, wwat_fast, wbat_fast, rlat_fast, rwat_fast, rbat_fast):
	Declare.  Remove redundant masking.
	(wwat_fast, rwat_fast): Add argument endianw.  Changed callers.
	(MA): Updated for change pc -> PC.
	(Delay_Slot): Use RIAT.
	(empty): Deleted.
	(trap): Remove argument little_endian.  Add argument endianw.
	Changed all callers.  Use raise_exception.
	(macw): Add argument endainw.  Changed all callers.
	(init_dsp): New function, extended after broken out of init_pointers.
	(sim_resume): Replace pc with insn_ptr.  Replace little_endian with
	endianw.  Replace nia with nip.  Reverse sense of maskb / maskw /
	maskl.  Implement logic for zero-overhead loops.  Don't try to
	interpret garbage when getting a SIGBUS at insn fetch.
	(sim_open): Call init_dsp.
	* gencode.c (tab): Use SET_NIP instead of nia = .  Use PH2T / PT2H /
	RAISE_EXCEPTION where appropriate.
	Add extra cycles for brai, braf , bsr, bsrf, jmp, jsr.

	* interp.c (sim_store_register, sim_fetch_register):
	Do proper endianness switch.

	* interp.c (saved_state_type): New members for struct member asregs:
	xymem_select, xmem, ymem, xmem_offset, ymem_offset.
	(special_address): Delete.
	(BUSERROR): Now a two-argument predicate.
	(PROCESS_SPECIAL_ADDRESS, WRITE_BUSERROR, READ_BUSERROR): New macros.
	(wlat_little, wwat_little, wbat_any, wlat_big, wwat_big): Delete.
	(process_wlat_addr, process_wwat_addr): New functions.
	(process_wbat_addr, process_rlat_addr, process_rwat_addr): Likewise.
	(process_rbat_addr): Likewise.
	(wlat_fast, wwat_fast, wbat_fast): Use WRITE_BUSERROR.
	(rlat_little, rwat_little, rbat_any, rlat_big, rwat_big): Delete.
	(rlat_fast, rwat_fast, rbat_fast): Use READ_BUSERROR.
	(RWAT, RLAT, RBAT, WWAT, WLAT, WBAT): Delete SLOW versions.
	(do_rdat, trap): Delete SLOW code.
	(SEXT32, SIGN32): New macros.
	(swap, swap16): Now integer in - integer out.  Changed all callers.
	(strswaplen, strnswap): Delete SLOW versions.
	(init_pointers): Initialize dsp memory selection (preliminary).
	(sim_store_register, sim_fetch_register): Use swap instead of
	big / little endian read / write functions.

	* interp.c (maskl): Deleted.
	(endianw, endianb): New variables.
	(special_address): Now inline.
	(bp_holder): Put raising of buserror there, rename to:
	(raise_buserror).
	(BUSERROR): Now yields a value.  Changed all users.
	(wbat_big): Delete.
	(wlat_fast, wwat_fast, wbat_fast): New functions.
	(rlat_fast, rwat_fast, rbat_fast): Likewise.
	(RWAT, RLAT, RBAT, WWAT, WLAT, WBAT): Use new functions.
	(do_rdat, do_wdat): Likewise.  Take maskl argument instead of
	little_endian one.  Changed caller macros.
	(swap, swap16): Use w[rw]lat_big / w[rw]lat_little directly.
	(strswaplen, strnswap): New functions.
	(trap): Use them to fix up endian mismatches;
	disable SYS_execve and SYS_execv; fix double address translation for
	SYS_pipe and SYS_stat.
	(sym_write, sym_read): Add endianness translation.
	(sym_store_register, sym_fetch_register): Add maskl local variable.
	(sim_open): Set endianw and endianb.

gdb:

	* sh-tdep.c (sh_dsp_reg_names, sh3_dsp_reg_names): New arrays.
	(sh_processor_type_table): Add entries for bfd_mach_sh_dsp and
	 bfd_mach_sh3_dsp.
	(sh_show_regs): Floating point registers are called fr0-fr15.
	For sh4, display fpul, fpscr and fr0-fr15 / dr0-dr14 as appropriate.
	Handle sh-dsp and sh3-dsp.
	config/sh/tm-sh.h (REGISTER_VIRTUAL_TYPE): sh-dsp / sh3-dsp
	don't have floating point registers.
	(DSR_REGNUM, A0G_REGNUM, A0_REGNUM, A1G_REGNUM, A1_REGNUM): Define.
	(M0_REGNUM, M1_REGNUM, X0_REGNUM, X1_REGNUM, Y0_REGNUM): Likewise.
	(Y1_REGNUM, MOD_REGNUM, RS_REGNUM, RE_REGNUM, R0B_REGNUM): Likewise.
2000-05-15 21:12:42 +00:00
Frank Ch. Eigler
b9791fcdd6 * merge from internal tree
2000-04-14  Gary Thomas  <gthomas@redhat.com>

	* v850.igen: Define 'br *' as illegal since this is the only
	way to provide a breakpoint on some v850 family processors.
2000-05-08 23:07:39 +00:00
Andrew Cagney
ba744a4f56 Add missing ChangeLog.
Sync with mitsu's version.
2000-05-03 09:26:07 +00:00
Andrew Cagney
dd37a34b6f * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call. 2000-05-01 07:06:10 +00:00
Andrew Cagney
5eb1a8fac3 Provide more detailed traces of the event queue. 2000-04-28 06:13:46 +00:00
Andrew Cagney
0c22be818b Fix event insertion when processing more than one event for the current time. 2000-04-28 06:02:51 +00:00
Andrew Cagney
25d704f304 Cleanup tracing. 2000-04-28 05:59:25 +00:00