* doc/binutils.texi (objdump): Document x86 -M options.
include/ChangeLog
* dis-asm.h (print_insn_i386): Declare.
opcodes/ChangeLog
* disassemble.c (disassembler): Call print_insn_i386.
* i386-dis.c (SUFFIX_ALWAYS): Define.
(struct dis_private): Add orig_sizeflag.
(print_insn_i386): Make it a wrapper, calling..
(print_insn): ..The old body of print_insn_i386. Avoid longjmp
warning without using volatile by moving orig_sizeflag to priv,
and removing inbuf. Parse disassembler_options.
(print_insn_i386_att, print_insn_i386_intel): Move initialisation
code to print_insn.
(putop): Remove #ifdef SUFFIX_ALWAYS.
accept WordReg.
* i386-dis.c (grps): Change "sldt", "str", and "smsw" entries
to "sldtQ", "strQ", "smswQ" respectively; all with Ev operand
category instead of Ew.
2001-10-21 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Mark "bgezall" and
"bltzall" as writing GPR 31 (since they do).
* mips-dis.c (print_insn_arg): Calculate info->target
where appropriate.
(print_insn_mips): Fill in instruction info.
(print_mips16_insn_arg): Remove unneded variable 'val'.
Removed duplicated instruction target calculations,
calculate once and print that result. Use same idiom for
masking the jump segment bits as is used in print_insn_arg.
[gas/testsuite/ChangeLog]
2001-10-21 Chris Demetriou <cgd@broadcom.com>
* gas/mips/beq.s: Add zero words at end of instructions so
that objdump will print "..." when disassembling.
* gas/mips/beq.d: Update for disassembler changes which force
branch delay-slot nops to be printed.
* gas/mips/bge.d: Ditto.
* gas/mips/bgeu.d: Ditto.
* gas/mips/blt.d: Ditto.
* gas/mips/bltu.d: Ditto.
* gas/mips/jal-svr4pic.d: Ditto.
* gas/mips/jal-xgot.d: Ditto.
2001-10-17 Chris Demetriou <cgd@broadcom.com>
* gas/mips/mips.exp (sb1-ext-ps): New test to test
SB-1 core's paired-single extensions to the MIPS64 ISA.
* gas/mips/sb1-ext-ps.d: New file.
* gas/mips/sb1-ext-ps.s: New file.
[include/opcode/ChangeLog]
2001-10-17 Chris Demetriou <cgd@broadcom.com>
* mips.h (INSN_SB1): New cpu-specific instruction bit.
(OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1
if cpu is CPU_SB1.
[opcodes/ChangeLog]
2001-10-17 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_isa_type): Make the ISA used to disassemble
SB-1 binaries include instructions specific to the SB-1.
* mips-opc.c (SB1): New definition.
(mips_builtin_opcodes): Add SB-1 extension opcodes "div.ps",
"recip.ps", "rsqrt.ps", and "sqrt.ps".
* gas/ppc/booke.s (rfci, wrtee, wrteei, mfdcrx, mfdcr, mtdcrx,
mtdcr, msync, dcba, mbar): New BookE tests.
* gas/ppc/booke.d: Update for new BookE tests.
[opcodes/ChangeLog]
* ppc-opc.c (MO): New macro for MO field of mbar instruction.
(powerpc_opcodes): Add rfci, wrtee, wrteei, mfdcrx, mfdcr,
mtdcrx, mtdcr, msync, dcba and mbar as BookE instructions.
* config/tc-ppc.c (md_parse_option): New -m7410, -m7450 and -m7455
flags, equivalent to -m7400. New -maltivec to enable AltiVec
instructions. New -mbook64 and -mbooke/-mbooke32 flags to enable
64-bit and 32-bit BookE support, respectively. Change -m403 and
-m405 to set PPC403 option.
(md_show_usage): Adjust for new options.
* doc/all.texi: Set PPC.
* doc/as.texinfo: Add PPC support and pull in c-ppc.texi.
* doc/c-ppc.texi: New file.
* doc/Makefile.am (CPU_DOCS): Add c-ppc.texi.
* doc/Makefile.in: Regenerate.
[gas/testsuite/ChangeLog]
* gas/ppc/booke.s: New test for Motorola BookE.
* gas/ppc/booke.d: New file.
* gas/ppc/ppc.exp: Test booke.s.
[include/opcode/ChangeLog]
* ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_403): New opcode flags for
BookE and PowerPC403 instructions.
[opcodes/ChangeLog]
* ppc-opc.c (insert_de, extract_de, insert_des, extract_des): New
instruction field instruction/extraction functions for new BookE
DE form instructions.
(CT): New macro for CT field in an X form instruction.
(DE, DES, DEO, DE_MASK): New macros for DE/DES fields in DE form
instructions.
(PPC64): Don't include PPC_OPCODE_PPC.
(403): New opcode macro for PPC403 processors.
(BOOKE): New opcode macro for BookE processors.
(bce, bcel, bcea, bcela, bclre, bclrel: New BookE instructions.
(bcctre, bcctrel, be, bel, bea, bela, icbt, icbte, lwzxe): Likewise.
(dcbste, lwzuxe, luxe, dcbfe, lbzxe, lwarxe, lbzuxe): Likewise.
(stwcxe, stwxe, stxe, stwuxe, stuxe, stbxe, dcbtste, stbuxe): Likewise.
(mfapidi, dcbte, lhzxe, lhzuxe, lhaxe, lhauxe, subfe64): Likewise.
(subfeo64, adde64, addeo64, sthxe, sthuxe, subfze64): Likewise.
(subfzeo64, addze64, addzeo64, dcbie, subfme64, subfmeo64): Likewise.
(addme64, addmeo64, stdcxe., mcrxr64, lwbrxe, lfsxe, lfsuxe): Likewise.
(lfdxe, lfduxe, stwbrxe, stfsxe, stfsuxe, stfdxe, dcbae): Likewise.
(stfduxe, tlbivax, tlbivaxe, lhbrxe, ldxe, lduxe, tlbsx): Likewise.
(tlbsxe, sthbrxe, stdxe, stduxe, icbie, stfiwxe, dcbze, lbze): Likewise.
(lbzue, ldue, lhze, lhzue, lhae, lhaue, lwze, lwzue): Likewise.
(stbe, stbue, sthe, sthue, stwe, stwue, lfse, lfsue, lfde): Likewise.
(lfdue, stde, stdue, stfse, stfsue, stfde, stfdue): Likewise.
* ppc-dis.c (print_insn_big_powerpc, print_insn_little_powerpc): Look
for a disassembler option of `booke', `booke32' or `booke64' to enable
BookE support in the disassembler.
* cgen-ibld.in (insert_1): Switched bfd_get_bits and bfd_set_bits
calls to cgen_get_insn_value and cgen_put_insn_value calls.
(extract_1): Switched bfd_get_bits call to cgen_get_insn_value call.
Jason Eckhardt <jle@redhat.com>
* mips-dis.c: Add support for bfd_mach_mipsisa32 and
bfd_mach_mipsisa64. Remove bfd_mach_mips32, bfd_mach_mips32_4k,
bfd_mach_mips64.
(LS): Define.
(insert_ds): Complain if not a multiple of 4.
(XSYNC): Define.
(XSYNC_MASK): Define.
(powerpc_opcodes): Add "slbmte", "lwsync", "ptesync", "slbmfev",
"slbmfee". Modify "sync" to use XSYNC_MASK and LS.
* cgen-asm.in: Include "xregex.h" always to enable the libiberty
regex support.
(@arch@_cgen_build_insn_regex): New routine from Graydon.
(@arch@_cgen_assemble_insn): Add Graydon's code to use regex
to verify if it is worth parsing the insn as insn "x". Also update
error message when insn is not a recognized format of the insn vs
when the insn is completely unrecognized.
* i386-dis.c (set_op): Handle 64 bit and 32 bit mode.
(OP_J): Use bfd_vma for mask to work properly with 64 bits.
(op_address,op_riprel): Use bfd_vma to handle 64 bits.
2001-06-13 Geoffrey Keating <geoffk@redhat.com>
* cgen-asm.c (cgen_parse_keyword): When looking for the
boundaries of a keyword, allow any special characters
that are actually in one of the allowed keyword.
* cgen-opc.c (cgen_keyword_add): Add any special characters
to the nonalpha_chars field.
Index: cgen/ChangeLog
2001-06-13 Geoffrey Keating <geoffk@redhat.com>
* desc.scm (<keyword> 'gen-defn): Add extra zero into
CGEN_KEYWORD_ENTRY initializers.
Index: include/opcode/ChangeLog
2001-06-13 Geoffrey Keating <geoffk@redhat.com>
* cgen.h (cgen_keyword): Add nonalpha_chars field.
(cond_jump_mode, loop_jcxz_mode): Define.
(dis386_att): Add cond_jump_flag and loop_jcxz_flag as
appropriate, and 'F' suffix to loop insns.
(disx86_64_att): Likewise.
(dis386_twobyte_att): Likewise.
(print_insn_i386): Don't output addr prefix for loop, jcxz insns.
Output data size prefix for long conditional jumps. Output cs and
ds branch hints.
(putop): Handle 'F', and mark PREFIX_ADDR used for case 'E'.
(OP_J): Don't make PREFIX_DATA used.
(need_modrm): Give it file scope.
(MODRM_CHECK): Define.
(dofloat): Use MODRM_CHECK.
(OP_E): Likewise.
(OP_EM): Likewise.
(OP_EX): Likewise.
and fix testsuite yet again now that we are getting correct disassembly.
[opcodes/ChangeLog]
2001-05-07 Frank Ch. Eigler <fche@redhat.com>
* cgen-dis.in (default_print_insn): Tolerate min<base instructions
even at end of a section.
* cgen-ibld.in (extract_normal): Tolerate min!=base!=max instructions
by ignoring precariously-unpacked insn_value in favor of raw buffer.
[cgen/ChangeLog]
2001-05-07 Frank Ch. Eigler <fche@redhat.com>
* iformat.scm (compute-insn-base-mask-length): Rewrite to tolerate
various-base-length instruction sets.
2001-05-04 Frank Ch. Eigler <fche@redhat.com>
* m32r-dis.c, -asm.c, -ibld.c: Regenerated with disassembler fixes.
2001-05-04 Frank Ch. Eigler <fche@redhat.com>
* cgen-dis.in (print_insn): Remove call to read_insn. Instead,
assume incoming buffer already has the base insn loaded. Handle
case of smaller-than-base instructions for variable-length case.
* cgen-asm.in (@arch@_cgen_assemble_insn): Move tmp_errmsg
declaration inside CGEN_VERBOSE_ASSEMBLER_ERRORS conditional.
* cgen-ibld.in (put_insn_int_value): Mark cd parameter as unused
to allay a compiler warning.
* ia64-gen.c (fetch_insn_class): If xsect, then ignore comment and
notestr if larger than xsect.
(in_class): Handle format M5.
* ia64-asmtab.c: Regnerate.
* cpu-ia64-opc.c (elf64_ia64_operands}: Fix typo: error string for
C8 said "1" instead of "8". Clarify error string for IMM22:
"signed integer" instead of just "integer".
* config/tc-ia64.c (enum operand_match_result): New type.
(operand_match): Change return type to operand_match_result.
Fix all returns appropriately, adding support for returning the
out-of-range result.
(parse_operands): New locals result, error_pos, out_of_range_pos,
curr_out_of_range_pos. Rewrite operand matching loop to give better
error messages.
* ia64-opc-d.c (ia64_opcodes_d): Break the "add" pattern into two
separate variants: one for IMM22 and the other for IMM14.
* ia64-asmtab.c: Regenerate.
operands is greater than 127.
2001-02-02 Patrick Macdonald <patrickm@redhat.com>
* cgen.h (CGEN_SYNTAX_CHAR_TYPE): Typedef as unsigned short.
(CGEN_MAX_SYNTAX_ELEMENTS): Rename from CGEN_MAX_SYNTAX_BYTES.
(CGEN_SYNTAX): Define using CGEN_MAX_SYNTAX_ELEMENTS.
* fr30-desc.h: Regenerate with CGEN_MAX_SYNTAX_ELEMENTS.
* m32r-desc.h: Regenerate.
(dis386_twobyt): Add SSE2 instructions.
(twobyte_uses_SSE_prefix: Rename from ... ; add new SSE instructions.
(twobyte_uses_f3_prefix): ... this one.
(grps): Add SSE instructions.
(prefix_user_table): Add two new slots; add SSE2 instructions.
(print_insn_i386): Rename uses_f3_prefix to uses_SSE_prefix;
Handle the REPNZ and Data16 prefixes as well; do proper lookup
to prefix_user_table.
(OP_E): Accept mfence and lfence as well.
(OP_MMX): Data16 prefix turns MMX to SSE; support REX extensions.
(OP_XMM): Support REX extensions.
(OP_EM): Likewise.
(OP_EX): Likewise.
* cgen-asm.in (parse_insn_normal): Changed syn to be
CGEN_SYNTAX_CHAR_TYPE. Changed all references to *syn
as character to use CGEN_SYNTAX_CHAR macro and all comparisons
to '\0' to use 0 instead.
* cgen-dis.in (print_insn_normal): Ditto.
* cgen-ibld.in (insert_insn_normal, extract_insn_normal): Ditto.
(rex): New static variable.
(REX_MODE64, REX_EXTX, REX_EXTY, REX_EXTZ): New constants.
(USED_REX): New macro.
(Ev, Ed, Rm, Iq, Iv64, Cm, Dm, Rm*, Ob64, Ov64): New macros.
(OP_I64, OP_OFF64, OP_IMREG): New functions.
(OP_REG, OP_OFF): Declare.
(get64, get32, get32s): New functions.
(r??_reg): New constants.
(dis386_att): Change templates of instruction implicitly promoted
to 64bit; change e?? to RMe?? for unwind RM byte instructions.
(grps): Likewise.
(dis386_intel): Likewise.
(dixx86_64_att): New table based on dis386_att.
(dixx86_64_intel): New table based on dis386_intel.
(names64, names8rex): New global variable.
(names32, names16): Add extended registers.
(prefix_user_t): Recognize rex prefixes.
(prefix_name): Print REX prefixes nicely.
(op_riprel): New global variable.
(start_pc): Set type to bfd_vma.
(print_insn_i386): Detect the 64bit mode and use proper table;
move ckprefix after initializing the buffer; output unused rex prefixes;
output information about target of RIP relative addresses.
(putop): Support 'O' and 'I'. Update handling of "P', 'Q', 'R' and 'S';
(print_operand_value): New function.
(OP_E, OP_G, OP_REG, OP_I, OP_J, OP_DIR, OP_OFF, OP_D): Add support for
REX prefix and new modes.
(get64, get32s): New.
(get32): Return bfd_signed_vma type.
(set_op): Initialize the op_riprel.
* disassemble.c (disassembler): Recognize the x86-64 disassembly.
2001-01-02 Richard Sandiford <rsandifo@redhat.com>
* cgen-dis.c (hash_insn_array): Use bfd_put_bits().
(hash_insn_list): Likewise
* cgen-ibld.in (insert_1): Use bfd_put_bits() and bfd_get_bits().
(extract_1): Use bfd_get_bits().
(extract_normal): Apply sign extension to both extraction
methods.
* cgen-opc.c (cgen_get_insn_value): Use bfd_get_bits()
(cgen_put_insn_value): Use bfd_put_bits()
* elfxx-ia64.c (get_dyn_sym_info): Cast %p argument to void *.
* config/tc-ia64.h (ia64_init): Add prototype.
* gas/ia64/dv-imply.d, gas/ia64/dv-mutex.d, gas/ia64/dv-safe.d,
gas/ia64/dv-srlz.d, gas/ia64/opc-m.d: Update.
* ia64-dis.c (print_insn_ia64): Cast away const on ia64_free_opcode
argument.
* ia64_gen.c (insert_deplist): Cast sizeof result to int.
(print_dependency_table): Print NULL if semantics field not set.
(insert_opcode_dependencies): Mark cmp parameter as unused.
(print_main_table): Use fprintf_vma to print long long fields.
(main): Mark argv paramter as unused. Convert to old style definition.
* ia64-opc.c (ia64_find_dependency): Cast sizeof result to int.
* ia64-asmtab.c: Regnerate.
2000-08-30 Mark Hatle <mhatle@mvista.com>
* config/tc-ppc.c (md_parse_option): Recognize -m405.
In src/opcodes/ChangeLog:
2000-08-30 Mark Hatle <mhatle@mvista.com>
* ppc-opc.c Add XTLB macro for a few PPC 4xx extended mnemonics.
(powerpc_opcodes): Add table entries for PPC 405 instructions.
Changed rfci, icbt, mfdcr, dccci, mtdcr, iccci from PPC to PPC403
instructions.
Added extended mnemonic mftbl as defined in the 405GP manual
for all PPCs.
* cgen-ibld.in (cgen_put_insn_int_value): New function.
(insert_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P.
(insert_insn_normal): Use cgen_put_insn_int_value with CGEN_INT_INSN_P.
(extract_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P.
* cgen-dis.in (read_insn): New static function.
(print_insn): Use read_insn to read the insn into the buffer and set
up for disassembly.
(print_insn): in CGEN_INT_INSN_P, make sure that the entire insn is
in the buffer.
* fr30-asm.c: Regenerated.
* fr30-desc.c: Regenerated.
* fr30-desc.h Regenerated.
* fr30-dis.c: Regenerated.
* fr30-ibld.c: Regenerated.
* fr30-opc.c: Regenerated.
* fr30-opc.h Regenerated.
* m32r-asm.c: Regenerated.
* m32r-desc.c: Regenerated.
* m32r-desc.h Regenerated.
* m32r-dis.c: Regenerated.
* m32r-ibld.c: Regenerated.
* m32r-opc.c: Regenerated.
2000-08-08 Jason Eckhardt <jle@cygnus.com>
* config/tc-i860.h: Rework completely for BFD_ASSEMBLER.
(i860_fix_info): New enum.
(MD_APPLY_FIX3): Define.
(WORKING_DOT_WORD): Define.
(TC_HANDLES_FX_DONE): Define.
(DIFF_EXPR_OK): Define.
(LISTING_HEADER): Define.
(TARGET_FORMAT): Select target format based on endian flag.
(TARGET_BYTES_BIG_ENDIAN): Default to little endian.
(target_big_endian): Add external declaration.
* config/tc-i860.c: All existing code reworked completely. Other
new code shown below.
(SYNTAX_SVR4): Define.
(target_warn_expand): New variable.
(md_shortopts): Declare and define (-Qy, -Qn, and -V options).
(md_longopts): Declare and define with new options (-EL, -EB,
and -mwarn-expand).
(md_show_usage): New function.
(md_operand): New function.
(obtain_reloc_for_imm16): New function.
(md_apply_fix3): New function.
(tc_gen_reloc): New function.
include:
2000-08-08 Jason Eckhardt <jle@cygnus.com>
* opcode/i860.h: Small formatting adjustments.
opcode:
2000-08-08 Jason Eckhardt <jle@cygnus.com>
* i860-dis.c (print_br_address): Change third argument from int
to long.
bfd:
2000-08-08 Jason Eckhardt <jle@cygnus.com>
* elf32-i860.c (elf32_i860_howto_table): Updated some fields.
Change return type from void to int. Check the combination
of operands, return 1 if valid. Fix to avoid BUF overflow.
Report undefined combinations of operands in COMMENT.
Report internal errors to stderr. Output the adiw/sbiw
constant operand in both decimal and hex.
(print_insn_avr): Disassemble ldd/std with displacement of 0
as ld/st. Check avr_operand () return value, handle invalid
combinations of operands like unknown opcodes.
* i860-dis.c: New file.
(print_insn_i860): New function.
(print_br_address): New function.
(sign_extend): New function.
(BITWISE_OP): New macro.
(I860_REG_PREFIX): New macro.
(grnames, frnames, crnames): New structures.
* disassemble.c (ARCH_i860): Define.
(disassembler): Add check for bfd_arch_i860 to set disassemble
function to print_insn_i860.
* Makefile.in (CFILES): Added i860-dis.c.
(ALL_MACHINES): Added i860-dis.lo.
(i860-dis.lo): New dependences.
* configure.in: New bits for bfd_i860_arch.
* configure: Regenerated.
* include/opcode/i860.h (btne, bte, bla): Changed these opcodes
to use sbroff ('r') instead of split16 ('s').
(J, K, L, M): New operand types for 16-bit aligned fields.
(ld.x, {p}fld.x, fst.x, pst.d): Changed these opcodes to
use I, J, K, L, M instead of just I.
(T, U): New operand types for split 16-bit aligned fields.
(st.x): Changed these opcodes to use S, T, U instead of just S.
(andh, andnoth, orh, xorh): Deleted 3-register forms as they do not
exist on the i860.
(pfgt.sd, pfle.sd): Deleted these as they do not exist on the i860.
(pfeq.ss, pfeq.dd): New opcodes.
(st.s): Fixed incorrect mask bits.
(fmlow): Fixed incorrect mask bits.
(fzchkl, pfzchkl): Fixed incorrect mask bits.
(faddz, pfaddz): Fixed incorrect mask bits.
(form, pform): Fixed incorrect mask bits.
(pfld.l): Fixed incorrect mask bits.
(fst.q): Fixed incorrect mask bits.
(all floating point opcodes): Fixed incorrect mask bits for
handling of dual bit.
* include/elf/i860.h: New file.
(elf_i860_reloc_type): Defined ELF32 i860 relocations.
* bfd/cpu-i860.c: Added comments.
* bfd/elf32-i860.c (TARGET_LITTLE_SYM): Defined to
bfd_elf32_i860_little_vec.
(TARGET_LITTLE_NAME): Defined to "elf32-i860-little".
(ELF_MAXPAGESIZE): Changed to 4096.
* bfd/targets.c (bfd_elf32_i860_little_vec): Declaration of
new target.
(bfd_target_vector): Added bfd_elf32_i860_little_vec.
* bfd/config.bfd (i860-stardent-sysv4*, i860-stardent-elf*): Added
config for little endian elf32 i860.
(targ_defvec): Define for the new config above
as "bfd_elf32_i860_little_vec".
(targ_selvecs): Define for the new config above
as "bfd_elf32_i860_vec bfd_elf32_i860_little_vec"
* bfd/configure.in (bfd_elf32_i860_little_vec): Added recognition
of new target vec.
* bfd/configure: Regenerated.
* opcodes/i860-dis.c: New file.
(print_insn_i860): New function.
(print_br_address): New function.
(sign_extend): New function.
(BITWISE_OP): New macro.
(I860_REG_PREFIX): New macro.
(grnames, frnames, crnames): New structures.
* opcodes/disassemble.c (ARCH_i860): Define.
(disassembler): Add check for bfd_arch_i860 to set disassemble
function to print_insn_i860.
* include/dis-asm.h (print_insn_i860): Add prototype.
* opcodes/Makefile.in (CFILES): Added i860-dis.c.
(ALL_MACHINES): Added i860-dis.lo.
(i860-dis.lo): New dependences.
* opcodes/configure.in: New bits for bfd_i860_arch.
* opcodes/configure: Regenerated.
