Commit graph

2045 commits

Author SHA1 Message Date
Claudiu Zissulescu
24b368f853 Fix failures in the GAS testsuite for the ARC architecture.
gas	* config/tc-arc.c (arc_option): Sets all internal gas options when
	parsing .cpu directive.
	(declare_register_set): Declare all 64 registers.
	(md_section_align): Refactor.
	(md_pcrel_from_section): Remove assert.
	(pseudo_operand_match): Fix pseudo operand match.
	(find_reloc): Use flags filed, extend matching.
	* config/tc-arc.h (TC_VALIDATE_FIX): Don't fixup any PLT
	relocation.

testsuite	* gas/arc/bic.d: Update test.
	* gas/arc/add_s-err.s: New file.
	* gas/arc/cpu-warn1.s: Likewise.
	* gas/arc/pcl-relocs.d: Likewise.
	* gas/arc/pcl-relocs.s: Likewise.
	* gas/arc/pcrel-relocs.d: Likewise.
	* gas/arc/pcrel-relocs.s: Likewise.
	* gas/arc/pic-relocs.d: Likewise.
	* gas/arc/pic-relocs.s: Likewise.
	* gas/arc/plt-relocs.d: Likewise.
	* gas/arc/plt-relocs.s: Likewise.
	* gas/arc/pseudos.d: Likewise.
	* gas/arc/pseudos.s: Likewise.
	* gas/arc/sda-relocs.d: Likewise.
	* gas/arc/sda-relocs.s: Likewise.
	* gas/arc/sda-relocs2.d: Likewise.
	* gas/arc/sda-relocs2.s: Likewise.
	* gas/arc/tls-relocs.d: Likewise.
	* gas/arc/tls-relocs.s: Likewise.

opcode	* arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32].

opcodes	* arc-dis.c (special_flag_p): Match full mnemonic.
	* arc-opc.c (print_insn_arc): Check section size to read
	appropriate number of bytes. Fix printing.
	* arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
	arguments.
2015-12-04 10:49:57 +00:00
Tristan Gingold
b4687fcc2b Darwin: add new mach-o header flags.
binutils/
	* od-macho.c (bfd_mach_o_header_flags_name): Add name
	for flags until BFD_MACH_O_MH_APP_EXTENSION_SAFE.

include/mach-o/
	* loader.h (bfd_mach_o_header_flags): Add
	BFD_MACH_O_MH_APP_EXTENSION_SAFE.
2015-12-03 12:00:50 +01:00
Alan Modra
bbb1afc89b Invoke aout N_* macros with pointer to struct internal_exec
No functional changes here.

BTW, some of these headers don't seem to be used anywhere:
include/aout/dynix3.h, include/aout/encap.h, include/aout/hp.h,
gas/config/aout_gnu.h

bfd/
	* aout-adobe.c: Invoke aout N_* macros with pointer to
	struct internal_exec.
	* aout-arm.c: Likewise.
	* aout-cris.c: Likewise.
	* aout-target.h: Likewise.
	* aout-tic30.c: Likewise.
	* aoutf1.h: Likewise.
	* aoutx.h: Likewise.
	* bout.c: Likewise.
	* freebsd.h: Likewise.
	* gen-aout.c: Likewise.
	* hp300hpux.c: Likewise.
	* i386aout.c: Likewise.
	* i386linux.c: Likewise.
	* i386lynx.c: Likewise.
	* i386mach3.c: Likewise.
	* i386os9k.c: Likewise.
	* libaout.h: Likewise.
	* m68klinux.c: Likewise.
	* m88kmach3.c: Likewise.
	* mipsbsd.c: Likewise.
	* netbsd.h: Likewise.
	* pc532-mach.c: Likewise.
	* pdp11.c: Likewise.
	* riscix.c: Likewise.
	* sparclinux.c: Likewise.
	* sparclynx.c: Likewise.
gas/
	* config/aout_gnu.h: Invoke aout N_* macros with pointer to
	struct internal_exec.
include/
	* bout.h: Invoke aout N_* macros with pointer to
	struct internal_exec.
	* os9k.h: Likewise.
include/aout/
	* adobe.h: Invoke aout N_* macros with pointer to
	struct internal_exec.
	* aout64.h: Likewise.
	* dynix3.h: Likewise.
	* encap.h: Likewise.
	* hp.h: Likewise.
	* hp300hpux.h: Likewise.
	* sun4.h: Likewise.
2015-12-01 13:40:05 +10:30
Rainer Orth
87746c154a Port libvtv to Solaris
libstdc++-v3:
	* acinclude.m4 (GLIBCXX_ENABLE_VTABLE_VERIFY) <solaris2*>: Use
	-Wl,-R in VTV_CXXLINKFLAGS.
	* configure: Regenerate.

	* testsuite/18_support/bad_exception/23591_thread-1.c: Use
	-fvtable-verify=none on Solaris 12+.

	libgcc:
	* Makefile.in (VTV_CFLAGS): New variable.
	(vtv_start$(objext), vtv_end$(objext), vtv_end$(objext))
	(vtv_start_preinit$(objext), vtv_end_preinit$(objext)): Use it.
	* config.host (*-*-solaris2*): Add t-crtstuff-pic to tmake_file.
	Add vtv_start.o, vtv_end.o, vtv_start_preinit.o, vtv_end_preinit.o
	to extra_parts if $enable_vtable_verify = yes.

	libvtv:
	* configure.tgt (*-*-solaris2.[1-9]*): Declare supported.
	* configure.ac: Call AC_USE_SYSTEM_EXTENSIONS.
	<*-*-solaris2*>: Check for init priority support.
	Check for getexecname, __fortify_fail, _obstack_begin.
	(VTV_NO_OBSTACK): New conditional.
	* configure: Regenerate.
	* Makefile.am [VTV_NO_OBSTACK] (obstack.c): Use new condition.
	Create empty config.h
	* Makefile.in: Regenerate.

	* vtv_rts.cc [HAVE_GETEXECNAME] (program_invocation_name): New
	variable.
	(read_section_offset_and_length) [HAVE_GETEXECNAME]: Set it.
	(dl_iterate_phdr_callback) [HAVE_GETEXECNAME]: Set it.

	(__fortify_fail): Wrap in HAVE___FORTIFY_FAIL
	[!HAVE___FORTIFY_FAIL]: Provide non-Cygwin implementation.

	(read_section_offset_and_length): Assert sh_size >= VTV_PAGE_SIZE.
	(iterate_modules): Fix typo.
	Use VTV_PAGE_SIZE.
	(dl_iterate_phdr_callback): Fix typo.
	Use VTV_PAGE_SIZE.
	(__VLTChangePermission): Fix typos.

	include:
	* vtv-change-permission.h (VTV_PAGE_SIZE) [__sun__ && __svr4__ &&
	__sparc__]: Define.

	gcc:
	* config/sol2.h (SUPPORTS_INIT_PRIORITY): Move up.
	(STARTFILE_VTV_SPEC, ENDFILE_VTV_SPEC): Define.
	(STARTFILE_SPEC): Use %(startfile_vtv).
	(ENDFILE_SPEC): Use %(endfile_vtv).
	(SUBTARGET_EXTRA_SPECS): Handle STARTFILE_VTV_SPEC,
	ENDFILE_VTV_SPEC.

	* gcc.c (LINK_COMMAND_SPEC): Move VTABLE_VERIFICATION_SPEC after %{L*}.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230865 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-28 16:39:32 +00:00
Rich Felker
f4936735c5 SH FDPIC backend support
gcc/ChangeLog
	* config.gcc: Handle --enable-fdpic.
	* config/sh/constraints.md (Ccl): New constraint.
	* config/sh/linux.h (SUBTARGET_LINK_EMUL_SUFFIX): Handle -mfdpic.
	* config/sh/sh-c.c (sh_cpu_cpp_builtins): Add __FDPIC__ and
	__SH_FDPIC__.
	* config/sh/sh-mem.cc (expand_block_move): Support FDPIC for calls
	to library functions.
	* config/sh/sh-protos.h (function_symbol_result): New struct.
	(function_symbol): Return function_symbol_result.
	(sh_get_fdpic_reg_initial_val, sh_load_function_descriptor): New
	declarations.
	* config/sh/sh.c (TARGET_ASM_INTEGER, sh_assemble_integer):
	Implement target hook.
 	(TARGET_CANNOT_FORCE_CONST_MEM, sh_cannot_force_const_mem_p):
	Likewise.
	(sh_option_override): Force -fPIC if FDPIC is in effect.
 	(sh_asm_output_addr_const_extra): Add UNSPEC_GOTFUNCDESC and
	UNSPEC_GOTOFFFUNCDESC cases.
	(prepare_move_operands): Use FDPIC initial GOT register for
	TLS-related GOT access; inhibit cross-section address offset
	constants for FDPIC.
	(sh_assemble_integer): New function.
	(sh_cannot_copy_insn_p): Inhibit copying insns that are FDPIC
	PC-relative call sites.
	(expand_ashiftrt): Adapt invocation of function_symbol.
	(sh_expand_prologue): Inhibit PC-relative GOT address load for
	FDPIC.
	(nonpic_symbol_mentioned_p): Add cases for UNSPEC_GOTFUNCDESC and
	UNSPEC_GOTOFFFUNCDESC.
	(legitimize_pic_address): Resolve function symbols to function
	descriptors for FDPIC.  Do not use GOT-relative addressing for
	local data that may be read-only on FDPIC.
	(sh_emit_storesi, sh_emit_storehi): New functions.
	(sh_trampoline_init): Generate FDPIC trampolines.
	(sh_function_ok_for_sibcall): Add TARGET_FDPIC check.
	(sh_expand_sym_label2reg): Don't assume sibcalls are local.
	(sh_output_mi_thunk): Generate FDPIC call.
	(function_symbol): Return function_symbol_result.  For
	SFUNC_STATIC on FDPIC, generate call site labels to use
	PC-relative addressing rather than GOT-relative addressing.
	(sh_conditional_register_usage): Make PIC register fixed and call used
	when FDPIC is in effect.
	(sh_legitimate_constant_p): Impose FDPIC
	constant constraints.
	(sh_cannot_force_const_mem_p, sh_load_function_descriptor)
	(sh_get_fdpic_reg_initial_val): New functions.
	* config/sh/sh.h (SUBTARGET_ASM_SPEC, SUBTARGET_LINK_EMUL_SUFFIX):
	Handle -mfdpic.
	(FDPIC_SELF_SPECS, SUBTARGET_DRIVER_SELF_SPECS)
	(PIC_OFFSET_TABLE_REG_CALL_CLOBBERED)
	(SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P): New macros.
	(DRIVER_SELF_SPECS): Add SUBTARGET_DRIVER_SELF_SPECS and
	FDPIC_SELF_SPECS.
	(TRAMPOLINE_SIZE): Select trampoline size for FDPIC.
	(ASM_PREFERRED_EH_DATA_FORMAT): Add EH format constraints for
	FDPIC.
	(ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX): Handle FDPIC case.
	* config/sh/sh.md (UNSPEC_GOTFUNCDESC, UNSPEC_GOTOFFFUNCDESC): New
	constants.
	(calli_fdpic, call_valuei_fdpic, sibcalli_fdpic)
	(sibcalli_pcrel_fdpic, sibcall_pcrel_fdpic, sibcall_valuei_fdpic)
	(sibcall_valuei_pcrel_fdpic, sibcall_value_pcrel_fdpic)
	(sym2GOTFUNCDESC, symGOTFUNCDESC2reg, sym2GOTOFFFUNCDESC)
	(symGOTOFFFUNCDESC2reg): New patterns.
	(udivsi3_i1, udivsi3_i4, udivsi3_i4_single, udivsi3,
	*divsi_inv_call_combine, divsi3_i4, divsi3_i4_single, divsi3)
	(ashlsi3, ashlsi3_d_call, ashrsi3_n, lshrsi3, lshrsi3_d_call)
	(calli, call_valuei, call, call_value, sibcalli, sibcalli_pcrel)
	(sibcall_pcrel, sibcall, sibcall_valuei, sibcall_valuei_pcrel)
	(sibcall_value_pcrel, sibcall_value, GOTaddr2picreg, symGOT_load)
	(symGOTOFF2reg, block_move_real, block_lump_real)
	(block_move_real_i4, block_lump_real_i4): Add support for FDPIC
	calls.
	(mulsi3, ic_invalidate_line, initialize_trampoline, call_pop,
	call_value_pop): Adjust for new function_symbol signature.
	* config/sh/sh.opt (-mfdpic): New option.
	* doc/install.texi (Options specification): Document
	--enable-fdpic.
	* doc/invoke.texi (SH Options): Document -mfdpic.

include/ChangeLog:
	* longlong.h (udiv_qrnnd): Add FDPIC compatible version for SH.

libitm/ChangeLog:
	* config/sh/sjlj.S (_ITM_beginTransaction): Bypass PLT calling
	GTM_begin_transaction for compatibility with FDPIC.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@229438 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-28 16:39:31 +00:00
Pedro Alves
c4be264168 PR other/61321 - demangler crash on casts in template parameters
The fix for bug 59195:

 [C++ demangler handles conversion operator incorrectly]
 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=59195

unfortunately makes the demangler crash due to infinite recursion, in
case of casts in template parameters.

For example, with:

 template<int> struct A {};
 template <typename Y> void function_temp(A<sizeof ((Y)(999))>) {}
 template void function_temp<int>(A<sizeof (int)>);

The 'function_temp<int>' instantiation above mangles to:

  _Z13function_tempIiEv1AIXszcvT_Li999EEE

The demangler parses this as:

typed name
  template
    name 'function_temp'
    template argument list
      builtin type int
  function type
    builtin type void
    argument list
      template                          (*)
        name 'A'
        template argument list
          unary operator
            operator sizeof
            unary operator
              cast
                template parameter 0    (**)
              literal
                builtin type int
                name '999'

And after the fix for 59195, due to:

 static void
 d_print_cast (struct d_print_info *dpi, int options,
	       const struct demangle_component *dc)
 {
 ...
   /* For a cast operator, we need the template parameters from
      the enclosing template in scope for processing the type.  */
   if (dpi->current_template != NULL)
     {
       dpt.next = dpi->templates;
       dpi->templates = &dpt;
       dpt.template_decl = dpi->current_template;
     }

when printing the template argument list of A (what should be "<sizeof
(int)>"), the template parameter 0 (that is, "T_", the '**' above) now
refers to the first parameter of the the template argument list of the
'A' template (the '*' above), exactly what we were already trying to
print.  This leads to infinite recursion, and stack exaustion.  The
template parameter 0 should actually refer to the first parameter of
the 'function_temp' template.

Where it reads "for the cast operator" in the comment in d_print_cast
(above), it's really talking about a conversion operator, like:

  struct A { template <typename U> explicit operator U(); };

We don't want to inject the template parameters from the enclosing
template in scope when processing a cast _expression_, only when
handling a conversion operator.

The problem is that DEMANGLE_COMPONENT_CAST is currently ambiguous,
and means _both_ 'conversion operator' and 'cast expression'.

Fix this by adding a new DEMANGLE_COMPONENT_CONVERSION component type,
which does what DEMANGLE_COMPONENT_CAST does today, and making
DEMANGLE_COMPONENT_CAST just simply print its component subtree.

I think we could instead reuse DEMANGLE_COMPONENT_CAST and in
d_print_comp_inner still do:

 @@ -5001,9 +5013,9 @@ d_print_comp_inner (struct d_print_info *dpi, int options,
        d_print_comp (dpi, options, dc->u.s_extended_operator.name);
        return;

     case DEMANGLE_COMPONENT_CAST:
       d_append_string (dpi, "operator ");
 -     d_print_cast (dpi, options, dc);
 +     d_print_conversion (dpi, options, dc);
       return;

leaving the unary cast case below calling d_print_cast, but seems to
me that spliting the component types makes it easier to reason about
the code.

g++'s testsuite actually generates three symbols that crash the
demangler in the same way.  I've added those as tests in the demangler
testsuite as well.

And then this fixes PR other/61233 too, which happens to be a
demangler crash originally reported to GDB, at:
https://sourceware.org/bugzilla/show_bug.cgi?id=16957

Bootstrapped and regtested on x86_64 Fedora 20.

Also ran this through GDB's testsuite.  GDB will require a small
update to use DEMANGLE_COMPONENT_CONVERSION in one place it's using
DEMANGLE_COMPONENT_CAST in its sources.

libiberty/
2015-11-27  Pedro Alves  <palves@redhat.com>

        PR other/61321
        PR other/61233
        * demangle.h (enum demangle_component_type)
        <DEMANGLE_COMPONENT_CONVERSION>: New value.
        * cp-demangle.c (d_demangle_callback, d_make_comp): Handle
        DEMANGLE_COMPONENT_CONVERSION.
        (is_ctor_dtor_or_conversion): Handle DEMANGLE_COMPONENT_CONVERSION
        instead of DEMANGLE_COMPONENT_CAST.
        (d_operator_name): Return a DEMANGLE_COMPONENT_CONVERSION
        component if handling a conversion.
        (d_count_templates_scopes, d_print_comp_inner): Handle
        DEMANGLE_COMPONENT_CONVERSION.
        (d_print_comp_inner): Handle DEMANGLE_COMPONENT_CONVERSION instead
        of DEMANGLE_COMPONENT_CAST.
        (d_print_cast): Rename as ...
        (d_print_conversion): ... this.  Adjust comments.
        (d_print_cast): Rewrite - simply print the left subcomponent.
        * cp-demint.c (cplus_demangle_fill_component): Handle
        DEMANGLE_COMPONENT_CONVERSION.

        * testsuite/demangle-expected: Add tests.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@231020 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-28 16:39:31 +00:00
Iain Sandoe
35a88fa501 Fix PR63758 by using the _NSGetEnviron() API on Darwin
include/

	Roland McGrath  <roland@gnu.org>

	PR other/63758
	* environ.h: New file.

libiberty/

	Roland McGrath  <roland@gnu.org>
	Iain Sandoe  <iain@codesourcery.com>

	PR other/63758
	* pex-unix.c: Obtain the environment interface from settings in environ.h
	rather than in-line code.  Update copyright date.
	* setenv.c: Likewise.
	* xmalloc.c: Likewise.




git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228942 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-28 16:39:30 +00:00
Jason Merrill
e9a3881624 Implement N4514, C++ Extensions for Transactional Memory.
gcc/
	* builtins.def (BUILT_IN_ABORT): Add transaction_pure attribute.
gcc/c-family/
	* c-common.c (c_common_reswords): Add C++ TM TS keywords.
	(c_common_attribute_table): Add transaction_safe_dynamic.
	transaction_safe now affects type identity.
	(handle_tm_attribute): Handle transaction_safe_dynamic.
	* c-common.h (enum rid): Add RID_ATOMIC_NOEXCEPT,
	RID_ATOMIC_CANCEL, RID_SYNCHRONIZED.
	(OBJC_IS_CXX_KEYWORD): Add RID_SYNCHRONIZED.
	(D_TRANSMEM): New.
	* c-cppbuiltin.c (c_cpp_builtins): Define __cpp_transactional_memory.
	* c-pretty-print.c (pp_c_attributes_display): Don't print
	transaction_safe in C++.
gcc/c/
	* c-parser.c (c_lex_one_token): Handle @synchronized.
	* c-decl.c (match_builtin_function_types): A declaration of a built-in
	can change whether the function is transaction_safe.
gcc/cp/
	* cp-tree.h (struct cp_declarator): Add tx_qualifier field.
	(BCS_NORMAL, BCS_TRANSACTION): New enumerators.
	* lex.c (init_reswords): Limit TM kewords to -fgnu-tm.
	* parser.c (cp_lexer_get_preprocessor_token): Fix @synchronized.
	(make_call_declarator): Take tx_qualifier.
	(cp_parser_tx_qualifier_opt): New.
	(cp_parser_lambda_declarator_opt): Use it.
	(cp_parser_direct_declarator): Likewise.
	(cp_parser_statement): Handle atomic_noexcept, atomic_cancel.
	(cp_parser_compound_statement): Change in_try parameter to bcs_flags.
	(cp_parser_std_attribute): Map optimize_for_synchronized to
	transaction_callable.
	(cp_parser_transaction): Take the token.  Handle atomic_noexcept.
	* lambda.c (maybe_add_lambda_conv_op): Handle transaction-safety.
	* call.c (enum conversion_kind): Add ck_tsafe.
	(standard_conversion): Handle transaction-safety conversion.
	(convert_like_real, resolve_address_of_overloaded_function): Likewise.
	(check_methods): Diagnose transaction_safe_dynamic on non-virtual
	function.
	(look_for_tm_attr_overrides): Don't inherit transaction_safe_dynamic.
	* cvt.c (tx_safe_fn_type_p, tx_unsafe_fn_variant)
	(can_convert_tx_safety): New.
	* typeck.c (composite_pointer_type): Handle transaction-safety.
	* name-lookup.h (enum scope_kind): Add sk_transaction.
	* name-lookup.c (begin_scope): Handle it.
	* semantics.c (begin_compound_stmt): Pass it.
	* decl.c (check_previous_goto_1): Check it.
	(struct named_label_entry): Add in_transaction_scope.
	(poplevel_named_label_1): Set it.
	(check_goto): Check it.
	(duplicate_decls): A specialization can be transaction_safe
	independently of its template.
	(grokdeclarator): Handle tx-qualifier.
	* rtti.c (ptr_initializer): Handle transaction-safe.
	* search.c (check_final_overrider): Check transaction_safe_dynamic.
	Don't check transaction_safe.
	* mangle.c (write_function_type): Mangle transaction_safe here.
	(write_CV_qualifiers_for_type): Not here.
	(write_type): Preserve transaction_safe when stripping attributes.
	* error.c (dump_type_suffix): Print transaction_safe.
libiberty/
	* cp-demangle.c (d_cv_qualifiers): Dx means transaction_safe.
	(cplus_demangle_type): Let d_cv_qualifiers handle it.
	(d_dump, d_make_comp, has_return_type, d_encoding)
	(d_count_templates_scopes, d_print_comp_inner)
	(d_print_mod_list, d_print_mod, d_print_function_type)
	(is_ctor_or_dtor): Handle DEMANGLE_COMPONENT_TRANSACTION_SAFE.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228462 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-28 16:39:30 +00:00
Matthew Wahab
d685192a58 [AArch64] Add ARMv8.2 instructions BFC and REV64.
ARMv8.2 adds two new instructions: BFC as an alias for BFM and REV64 as
an alias for REV. This patch set adds support for these to binutils,
enabled when the -march=armv8.2-a is given. It depends on the support
for an instruction being its preferred form which was added in an
earlier patch.

This patch adds the alias BFC <Rd>, #<imm>, #<width> as the preferred
form for BFM when the source is a zero register and the conditions for
using the BFI form are met (in other words, BFC is the preferred form
for BFI <Rd>, <Rs>, #<imm>, #<width> when the <Rs> is a zero register).

gas/testsuite/
2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/alias-2.d: New.
	* gas/aarch64/alias-2.s: New.

include/opcode/
2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (aarch64_op): Add OP_BFC.

opcodes/
2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-asm.c (convert_bfc_to_bfm): New.
	(convert_to_real): Add case for OP_BFC.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-dis.c: (convert_bfm_to_bfc): New.
	(convert_to_alias): Add case for OP_BFC.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
	to allow width operand in three-operand instructions.
	* aarch64-tbl.h (QL_BF1): New.
	(aarch64_feature_v8_2): New.
	(ARMV8_2): New.
	(aarch64_opcode_table): Add "bfc".

Change-Id: I6efe318b2538ba11f0caece7c6d70957441c872b
2015-11-27 15:28:42 +00:00
Matthew Wahab
870181955b [AArch64] Add feature flags and command line for ARMv8.2 FP16 support.
ARMv8.2 adds optional support for 16-bit operations to the FP and
Adv.SIMD instructions. This patch adds a feature macro for this support
with a new command line option "+fp16" to enable/disable it.

Although the command line option is added as an architecture extension,
it only affects instructions available with when +fp or +simd is
enabled. If +fp16 is specified then it will also enable +fp.

There are currently no FP16 instructions implemented in binutils, this
patch is to enable subsequent work on supporting the extension.

gas/
2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (aarch64_features): Add "fp16".
	* doc/c-aarch64.texi (Architecture Extensions): Add "fp16".

include/opcode/
2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (AARCH64_FEATURE_F16): New.
	(AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2
	features.

Change-Id: Id2021e0513946e16d0935c2a5b9605574cdff95a
2015-11-27 13:19:50 +00:00
Nick Clifton
2e8cf49e13 Add an AArch64 simulator to GDB.
sim	* configure.tgt: Add aarch64 entry.
	* configure: Regenerate.
	* sim/aarch64/configure.ac: New configure template.
	* sim/aarch64/aclocal.m4: Generate.
	* sim/aarch64/config.in: Generate.
	* sim/aarch64/configure: Generate.
	* sim/aarch64/cpustate.c: New file - functions for accessing
	AArch64 registers.
	* sim/aarch64/cpustate.h: New header.
	* sim/aarch64/decode.h: New header.
	* sim/aarch64/interp.c: New file - interface between GDB and
	simulator.
	* sim/aarch64/Makefile.in: New makefile template.
	* sim/aarch64/memory.c: New file - functions for simulating
	aarch64 memory accesses.
	* sim/aarch64/memory.h: New header.
	* sim/aarch64/sim-main.h: New header.
	* sim/aarch64/simulator.c: New file - aarch64 simulator
	functions.
	* sim/aarch64/simulator.h: New header.

include/gdb * sim-aarch64.h: New file.

sim/test * configure: Regenerate.
	* sim/aarch64: New directory.
2015-11-24 08:47:59 +00:00
Matthew Wahab
250aafa477 [AArch64] Add support for ARMv8.1 Virtulization Host Extensions.
The ARMv8.1 architecture includes the Virtualization Host Extensions
which add a number of system registers. This patch adds support for
these system registers, making them available when -march=armv8.1-a is
selected.

include/opcode/
2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (AARCH64_FEATURE_V8_1): New.
	(AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1.

opcodes/
2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
	sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
	tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
	amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
	cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
	cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
	cnthv_ctl_el2, cnthv_cval_el2.
	(aarch64_sys_reg_supported_p): Update for the new system
	registers.

gas/testsuite/
2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/virthostext-directive.d: New.
	* gas/aarch64/virthostext.d: New.
	* gas/aarch64/virthostext.s: New.

Change-Id: Iecb370591b1b6e9e00d81c8ccd9ae3b0f71794a2
2015-11-20 16:09:34 +00:00
Matthew Wahab
56a1b672f4 [ARM] Add ARMv8.2 architecture feature and command line option.
ARMv8.2 is an architectural extension of ARMv8. This patch adds an
architecture feature macro for ARMv8.2 to the binutils ARM target
with GAS command line option -march=armv8.2-a.

gas/
2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-arm.c (arm_archs): Add "armv8.2-a".
	* doc/c-arm.texi (-march): Add "armv8.2-a".

include/opcode/
2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>

	* arm.h (ARM_EXT2_V8_2A): New.
	(ARM_ARCH_V8_2A): New.

Change-Id: I9e0f50e3c6cea24e6b87b8b862fd4e1cdcc1052e
2015-11-19 09:24:14 +00:00
Matthew Wahab
acb787b032 [AArch64] Add ARMv8.2 command line option and feature flag.
ARMv8.2 is an architectural extension of ARMv8. This patch adds an
architecture feature macro for ARMv8.2 to the binutils AArch64 target
with GAS command line option -march=armv8.2-a.

gas/
2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (aarch64_archs): Add "armv8.2-a".
	* doc/c-aarch64.texi (-march): Likewise.

include/opcode/
2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (AARCH64_FEATURE_V8_2): New.
	(AARCH64_ARCH_V8_2): New.

Change-Id: I129232ab00234a07d18ce4b619607344acb3cbaf
2015-11-19 09:12:49 +00:00
Tristan Gingold
c25b1ab690 Mach-O: add new defines and struct for darwin 14.5
include/mach-o/
	* arm64.h: New file.
	* unwind.h: Add arm64 encodings.
	* loader.h (bfd_mach_o_cpu_subtype): Add arm64 literals.
	(BFD_MACH_O_LC_ENCRYPTION_INFO_64, BFD_MACH_O_LC_LINKER_OPTIONS)
	(BFD_MACH_O_LC_LINKER_OPTIMIZATION_HINT)
	(BFD_MACH_O_LC_VERSION_MIN_WATCHOS): Define.
	* external.h (mach_o_encryption_info_64_command_external):
	(mach_o_linker_option_command_external)
	(mach_o_dyld_cache_header_external)
	(mach_o_dyld_cache_mapping_info_external)
	(mach_o_dyld_cache_image_info_external): New types.
2015-11-17 15:03:25 +01:00
Mike Frysinger
761e171ad8 sim: cr16: convert to common sim memory modules
The cr16 port has a lot of translation/offset logic baked into it, but
it all looks like copy & paste from the d10v port rather than something
the cr16 port wants.
2015-11-15 21:48:06 -05:00
Mike Frysinger
c4d4ed4083 sim: drop extern C linkage from most sim interface headers
Since these headers merely have enum's, drop the extern C linkage
markings.  Helps to reduce the copy & paste spam.
2015-11-15 00:38:26 -05:00
Peter Bergner
a680de9a98 Add assembler, disassembler and linker support for power9.
include/opcode/
	* ppc.h (PPC_OPCODE_POWER9): New define.
	(PPC_OPCODE_VSX3): Likewise.

opcodes/
	* ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
	Add PPC_OPCODE_VSX3 to the vsx entry.
	(powerpc_init_dialect): Set default dialect to power9.
        * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
        insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
        extract_l1 insert_xtq6, extract_xtq6): New static functions.
        (insert_esync): Test for illegal L operand value.
	(DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
	XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
	XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
	XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
	PPCVSX3): New defines.
	(powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
	fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
	<mcrxr>: Use XBFRARB_MASK.
	<addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
	bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
	cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
	cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
	lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
	lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
	modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
	rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
	stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
	subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
	vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
	vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
	vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
	vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
	vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
	vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
	vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
	xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
	xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
	xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
	xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
	xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
	xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
	xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
	xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
	xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
	xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
	xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
	xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
	xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
	<doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
	<tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.

include/elf/
	* ppc.h (R_PPC_REL16DX_HA): New reloction.
	* ppc64.h (R_PPC64_REL16DX_HA): Likewise.

bfd/
	* elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_REL16DX_HA.
	(ppc_elf_reloc_type_lookup): Handle R_PPC_REL16DX_HA.
	(ppc_elf_addr16_ha_reloc): Likewise.
	(ppc_elf_check_relocs): Likewise.
	(ppc_elf_relocate_section): Likewise.
	(is_insn_dq_form): Handle lxv and stxv instructions.
	* elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_REL16DX_HA.
	(ppc64_elf_reloc_type_lookup): Handle R_PPC64_REL16DX_HA.
	(ppc64_elf_ha_reloc): Likewise.
	(ppc64_elf_check_relocs): Likewise.
	(ppc64_elf_relocate_section): Likewise.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Likewise.
	* reloc.c (BFD_RELOC_PPC_REL16DX_HA): New.

elfcpp/
	* powerpc.h (R_POWERPC_REL16DX_HA): Define.

gas/
	* doc/as.texinfo (Target PowerPC): Document -mpower9 and -mpwr9.
	* doc/c-ppc.texi (PowerPC-Opts):  Likewise.
	* config/tc-ppc.c (md_show_usage): Likewise.
	(md_assemble): Handle BFD_RELOC_PPC_REL16DX_HA.
	(md_apply_fix): Likewise.
	(ppc_handle_align): Handle power9's group ending nop.

gas/testsuite/
	* gas/ppc/altivec3.s: New test.
	* gas/ppc/altivec3.d: Likewise.
	* gas/ppc/vsx3.s: Likewise.
	* gas/ppc/vsx3.d: Likewise.
	* gas/ppc/power9.s: Likewise.
	* gas/ppc/power9.d: Likewise.
	* gas/ppc/ppc.exp: Run them.
	* gas/ppc/power8.s <lxvx, lxvd2x, stxvx, stxvd2x>: Add new tests.
	* gas/ppc/power8.d: Likewise.
	* gas/ppc/vsx.s: <lxvx, stxvx>: Rename invalid mnemonics ...
	<lxvd2x, stxvd2x>: ...to this.
	* gas/ppc/vsx.d: Likewise.

gold/
	* gold/powerpc.cc (Powerpc_relocate_functions::addr16_dq): New function.
	(Powerpc_relocate_functions::addr16dx_ha): Likewise.
	(Target_powerpc::Scan::local): Handle R_POWERPC_REL16DX_HA.
	(Target_powerpc::Scan::global): Likewise.
	(Target_powerpc::Relocate::relocate): Likewise.

ld/testsuite/
	* ld-powerpc/addpcis.d: New test.
	* ld-powerpc/addpcis.s: New test.
	* ld-powerpc/powerpc.exp: Run it.
2015-11-11 19:52:52 -06:00
Mike Frysinger
6637a4265e sim: cr16/d10v: localize translation funcs
These functions are only used in the interp module, so there's no point
in exporting them and declaring them in the external sim interface.
2015-11-10 02:17:15 -05:00
Alan Modra
e9f40d7d68 Modify obstack.[hc] to avoid having to include other gnulib files
Using the standard gnulib obstack source requires importing quite a
lot of other files from gnulib, and requires build changes.

include/
	PR gdb/17133
	* obstack.h (__attribute_pure__): Expand _GL_ATTRIBUTE_PURE.
libiberty/
	PR gdb/17133
	* obstack.c (__alignof__): Expand alignof_type from alignof.h.
	(obstack_exit_failure): Don't use exitfail.h.
	(_): Include libintl.h when HAVE_LIBINTL_H and nls enabled.
	Provide default.  Don't include gettext.h.
	(_Noreturn): Define.
	* obstacks.texi: Adjust node references to external libc info files.
2015-11-09 15:18:35 +10:30
Alan Modra
314dee8ea9 Copy gnulib obstack files
This copies obstack.[ch] from gnulib, and updates the docs.  The next
patch should be applied if someone repeats the import at a later date.

include/
	PR gdb/17133
	* obstack.h: Import current gnulib file.
libiberty/
	PR gdb/17133
	* obstack.c: Import current gnulib file.
	* obstacks.texi: Updated doc, from glibc's manual/memory.texi.
2015-11-09 15:12:45 +10:30
Nick Clifton
854eb72b00 Disassemble RX NOP instructions as such.
opcode	* rx.h (enum RX_Opcode_ID): Add more NOP opcodes.

opcodes	* rx-decode.opc (rx_decode_opcode): Decode extra NOP
	instructions.
	* rx-decode.c: Regenerate.

tests	* gas/rx/max.d: Update expecetd disassembly.
	* gas/rx/nod.d: Likewise.
	* gas/rx/nop.sm: Add tests of more NOP instructions.
2015-11-02 14:37:33 +00:00
Nick Clifton
e292aa7a95 Fix disassembly of RX zero-offset register indirect instructions.
opcode	* rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.

opcodes	* rx-decode.opc (rx_disp): If the displacement is zero, set the
	type to RX_Operand_Zero_Indirect.
	* rx-decode.c: Regenerate.
	* rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.

gas	* config/rx-parse.y: Allow zero value for 5-bit displacements.

tests	* gas/rx/mov.sm: Add tests for zero offset indirect moves.
	* gas/rx/mov.d: Update expected output.
2015-11-02 14:14:22 +00:00
Yao Qi
43cdf5aeb8 Pass noaliases_p to aarch64_decode_insn
Nowadays aarch64_decode_insn is a public interface used by both
opcodes and gdb.  However, its behaviour relies on a global variable
no_aliases, which isn't a good practise.  On the other hand, In default,
no_aliases is zero, but in GDB, we do want no alias when decoding
instructions for prologue analysis (patches to be posted), so that we
can handle both instructions "add" and "mov" (an alias of "add") as
"add".  The code in GDB can be simplified.

This patch adds a new argument in aarch64_decode_insn, and pass no_aliases
to it.  In GDB side, always pass 1 to it.

include/opcode:

2015-10-28  Yao Qi  <yao.qi@linaro.org>

	* aarch64.h (aarch64_decode_insn): Update declaration.

opcodes:

2015-10-28  Yao Qi  <yao.qi@linaro.org>

	* aarch64-dis.c	(aarch64_decode_insn): Add one argument
	noaliases_p.  Update comments.  Pass noaliases_p rather than
	no_aliases to aarch64_opcode_decode.
	(print_insn_aarch64_word): Pass no_aliases to
	aarch64_decode_insn.

gdb:

2015-10-28  Yao Qi  <yao.qi@linaro.org>

	* aarch64-tdep.c (aarch64_software_single_step): Pass 1 to
	aarch64_decode_insn.
2015-10-28 14:22:57 +00:00
Cupertino Miranda
6f4b1afcdc Fix errors in the gas testsuite for the ARC target.
bfd	* reloc.c (BFD_RELOC_ARC_32_PCREL): New entry.
	(ARC_TLS_DTPOFF): Arrange it in order.
	* elf32-arc.c (arc_elf_howto_ini): Update formula.
	(get_middle_endian_relocation): New function.
	(PDATA): Define.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Likewise.

elf	* arc-reloc.def (ARC_32_PCREL): New definition.

gas	* config/tc-arc.c (tokenize_arguments): Avoid creating unused
	symbols when parsing relocation types.
	(md_apply_fix): Handle TLS relocations. Fix BFD_RELOC_ARC_32_PCREL
	relocation.
	(arc_check_reloc): Emit BFD_RELOC_ARC_32_PCREL relocation.
2015-10-28 13:48:00 +00:00
Stephen Fisher
c6056a744a Add support to readelf for reading NetBSD ELF core notes.
binutils * binutils.c (process_netbsd_elf_note): New function.
	(process_note): Call the new function for NetBSD core notes.

include	* common.h (NT_NETBSD_MARCH): Define.
2015-10-27 11:32:38 +00:00
H.J. Lu
caa65211bb Add "-z call-nop=PADDING" option to ld
The ld linker can transform indirect call to a locally defined function,
foo, via its GOT slot, to either "NOP call foo" or "call foo NOP" where
NOP is a 1-byte NOP padding.  This patch adds a "-z call-nop=PADDING"
option to x86 ld to control 1-byte NOP padding for x86 call instruction.
PADDING is one of prefix-addr, prefix-nop, suffix-nop, prefix-NUMBER or
suffix-NUMBER.

bfd/

	* elf32-i386.c (elf_i386_convert_load): Use call_nop_byte and
	check call_nop_as_suffix for 1-byte NOP padding to pad call.
	* elf64-x86-64.c (elf_x86_64_convert_load): Likewise.

include/

	* bfdlink.h (bfd_link_info): Add call_nop_as_suffix and
	call_nop_byte.

ld/

	* ld/ld.texinfo: Document "-z call-nop=PADDING" option.
	* emulparams/call_nop.sh: New file.
	* emulparams/elf_i386_be.sh: Source
	${srcdir}/emulparams/call_nop.sh.
	* emulparams/elf_i386_chaos.sh: Likewise.
	* emulparams/elf_i386_ldso.sh: Likewise.
	* emulparams/elf_i386_vxworks.sh: Likewise.
	* emulparams/elf_iamcu.sh: Likewise.
	* emulparams/elf_k1om.sh: Likewise.
	* emulparams/elf_l1om.sh: Likewise.
	* emulparams/elf_x86_64.sh: Likewise.
	* emultempl/elf32.em (gld${EMULATION_NAME}_before_parse): Set
	link_info.call_nop_byte if $CALL_NOP_BYTE isn't empty.

ld/testsuite/

	* ld-i386/call3.s: New file.
	* ld-i386/call3a.d: Likewise.
	* ld-i386/call3b.d: Likewise.
	* ld-i386/call3c.d: Likewise.
	* ld-i386/call3d.d: Likewise.
	* ld-i386/call3e.d: Likewise.
	* ld-i386/call3f.d: Likewise.
	* ld-i386/call3g.d: Likewise.
	* ld-i386/call3h.d: Likewise.
	* ld-i386/load1-nacl.d: Likewise.
	* ld-x86-64/call1.s: Likewise.
	* ld-x86-64/call1a.d: Likewise.
	* ld-x86-64/call1b.d: Likewise.
	* ld-x86-64/call1c.d: Likewise.
	* ld-x86-64/call1d.d: Likewise.
	* ld-x86-64/call1e.d: Likewise.
	* ld-x86-64/call1f.d: Likewise.
	* ld-x86-64/call1g.d: Likewise.
	* ld-x86-64/call1h.d: Likewise.
	* ld-x86-64/call1i.d: Likewise.
	* ld-x86-64/load1a-nacl.d: Likewise.
	* ld-x86-64/load1b-nacl.d: Likewise.
	* ld-x86-64/load1c-nacl.d: Likewise.
	* ld-x86-64/load1d-nacl.d: Likewise.
2015-10-22 04:56:39 -07:00
H.J. Lu
56ceb5b540 Add R_X86_64_[REX_]GOTPCRELX support to gas and ld
This patch adds support for the R_X86_64_GOTPCRELX and
R_X86_64_REX_GOTPCRELX relocations proposed in

https://groups.google.com/forum/#!topic/x86-64-abi/n9AWHogmVY0

to gas and ld.  It updates gas to generate R_X86_64_GOTPCRELX,
R_X86_64_REX_GOTPCRELX if there is a REX prefix, relocation for memory
operand, foo@GOTPCREL(%rip).  With the locally defined symbol, foo, we
convert

  mov foo@GOTPCREL(%rip), %reg

to

   lea foo(%rip), %reg

and convert

   call/jmp *foo@GOTPCREL(%rip)
to

   nop call foo/jmp foo nop

When PIC is false, convert

   test %reg, foo@GOTPCREL(%rip)
to

test $foo, %reg

and convert

   binop foo@GOTPCREL(%rip), %reg

to

   binop $foo, %reg

where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructions.

bfd/

	* elf64-x86-64.c: Include opcode/i386.h.
	(x86_64_elf_howto_table): Add R_X86_64_GOTPCRELX and
	R_X86_64_REX_GOTPCRELX.
	(R_X86_64_standard): Replace R_X86_64_PLT32_BND with
	R_X86_64_REX_GOTPCRELX.
	(x86_64_reloc_map): Add BFD_RELOC_X86_64_GOTPCRELX and
	BFD_RELOC_X86_64_REX_GOTPCRELX.
	(need_convert_mov_to_lea): Renamed to ...
	(need_convert_load): This.
	(elf_x86_64_check_relocs): Handle R_X86_64_GOTPCRELX and
	R_X86_64_REX_GOTPCRELX.  Replace need_convert_mov_to_lea with
	need_convert_load.
	(elf_x86_64_gc_sweep_hook): Handle R_X86_64_GOTPCRELX and
	R_X86_64_REX_GOTPCRELX.
	(elf_x86_64_size_dynamic_sections): Likewise.
	(elf_x86_64_relocate_section): Likewise.
	(elf_x86_64_convert_mov_to_lea): Renamed to ...
	(elf_x86_64_convert_load): This.  Replace need_convert_mov_to_lea
	with need_convert_load.  Support R_X86_64_GOTPCRELX and
	R_X86_64_REX_GOTPCRELX transformations.
	* reloc.c (BFD_RELOC_X86_64_GOTPCRELX): New.
	(BFD_RELOC_X86_64_REX_GOTPCRELX): Likewise.
	* bfd-in2.h: Regenerated.
	* libbfd.h: Likewise.

gas/

	* config/tc-i386.c (tc_i386_fix_adjustable): Handle
	BFD_RELOC_X86_64_GOTPCRELX and BFD_RELOC_X86_64_REX_GOTPCRELX.
	(tc_gen_reloc): Likewise.
	(i386_validate_fix): Generate BFD_RELOC_X86_64_GOTPCRELX or
	BFD_RELOC_X86_64_REX_GOTPCRELX if fx_tcbit2 is set.
	* config/tc-i386.h (TC_FORCE_RELOCATION_LOCAL): Also return
	true for BFD_RELOC_X86_64_GOTPCRELX and
	BFD_RELOC_X86_64_REX_GOTPCRELX.

gas/testsuite/

	* gas/i386/i386.exp: Run x86-64-gotpcrel.
	* gas/i386/x86-64-gotpcrel.d: New file.
	* gas/i386/x86-64-gotpcrel.s: Likewise.
	* gas/i386/ilp32/x86-64-gotpcrel.d: Likewise.
	* gas/i386/x86-64-localpic.d: Replace R_X86_64_GOTPCREL with
	R_X86_64_REX_GOTPCRELX.
	* gas/i386/ilp32/x86-64-localpic.d: Likewise.

include/elf/

	* x86-64.h (R_X86_64_GOTPCRELX): New.
	(R_X86_64_REX_GOTPCRELX): Likewise.

ld/testsuite/

	* ld-ifunc/ifunc-5r-local-x86-64.d: Replace R_X86_64_GOTPCREL
	with R_X86_64_REX_GOTPCRELX.
	* ld-x86-64/plt-main1.rd: Likewise.
	* ld-x86-64/plt-main3.rd: Likewise.
	* ld-x86-64/plt-main4.rd: Likewise.
	* ld-x86-64/gotpcrel1.dd: New file.
	* ld-x86-64/gotpcrel1.out: Likewise.
	* ld-x86-64/gotpcrel1a.S: Likewise.
	* ld-x86-64/gotpcrel1b.c: Likewise.
	* ld-x86-64/gotpcrel1c.c: Likewise.
	* ld-x86-64/gotpcrel1d.S: Likewise.
	* ld-x86-64/load1.s: Likewise.
	* ld-x86-64/load1a.d: Likewise.
	* ld-x86-64/load1b.d: Likewise.
	* ld-x86-64/load1c.d: Likewise.
	* ld-x86-64/load1d.d: Likewise.
	* ld-x86-64/x86-64.exp: Run load1a, load1b, load1c and load1d
	tests.  Run gotpcrel1 test.
2015-10-22 04:49:38 -07:00
H.J. Lu
02a866936d Add R_386_GOT32X support to gas and ld
This patch adds support for the R_386_GOT32X relocation proposed in

https://groups.google.com/forum/#!topic/ia32-abi/GbJJskkid4I

to gas and ld.  It updates gas to generate R_386_GOT32X relocation for
memory operand, foo@GOT[(%reg)].  We must encode "mov foo@GOT, %eax"
with the 0x8b opcode, instead of the 0xb8 opcode, so that it can be
transformed to "lea foo, %eax".  With the locally defined symbol, foo,
we convert

   mov foo@GOT[(%reg1)], %reg2
to
   lea foo[@GOTOFF(%reg1)], %reg2

and convert

   call/jmp *foo@GOT[(%reg)]
to

   nop call foo/jmp foo nop

When PIC is false, convert

   test %reg1, foo@GOT[(%reg2)]
to
   test $foo, %reg1

and convert

binop foo@GOT[(%reg1)], %reg2

to

binop $foo, %reg2

where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructions.

bfd/

	* elf32-i386.c: Include opcode/i386.h.
	(elf_howto_table): Add R_386_GOT32X.
	(R_386_ext2): Replace R_386_IRELATIVE with R_386_GOT32X.
	(elf_i386_reloc_type_lookup): Handle BFD_RELOC_386_GOT32X.
	(need_convert_mov_to_lea): Renamed to ...
	(need_convert_load): This.
	(elf_i386_check_relocs): Handle R_386_GOT32X.  Replace
	need_convert_mov_to_lea with need_convert_load.
	(elf_i386_gc_sweep_hook): Handle R_386_GOT32X.
	(elf_i386_size_dynamic_sections): Likewise.
	(elf_i386_relocate_section): Likewise.
	(elf_i386_convert_mov_to_lea): Renamed to ...
	(elf_i386_convert_load): This.  Replace need_convert_mov_to_lea
	with need_convert_load.  Support R_386_GOT32X transformations.
	* reloc.c (BFD_RELOC_386_GOT32X): New.
	* bfd-in2.h: Regenerated.
	* libbfd.h: Likewise.

gas/

	* config/tc-i386.c (tc_i386_fix_adjustable): Handle
	BFD_RELOC_386_GOT32X.
	(tc_gen_reloc): Likewise.
	(match_template): Force 0x8b encoding for "mov foo@GOT, %eax".
	(output_disp): Check for "call/jmp *mem", "mov mem, %reg",
	"test %reg, mem" and "binop mem, %reg" where binop is one of
	adc, add, and, cmp, or, sbb, sub, xor instructions.  Set
	fx_tcbit if the REX prefix is generated.  Set fx_tcbit2 if
	BFD_RELOC_386_GOT32X should be generated.
	(i386_validate_fix): Generate BFD_RELOC_386_GOT32X if fx_tcbit2
	is set.

gas/testsuite/

	* gas/i386/got.d: New file.
	* gas/i386/got.s: Likewise.
	* gas/i386/i386.exp: Run got.
	* gas/i386/localpic.d: Replace R_386_GOT32 with R_386_GOT32X.
	* gas/i386/mixed-mode-reloc32.d: Likewise.
	* gas/i386/reloc32.d: Likewise.

include/elf/

	* i386.h (R_386_GOT32X): New relocation.

ld/testsuite/

	* ld-i386/branch1.d: New file.
	* ld-i386/branch1.s: Likewise.
	* ld-i386/call1.d: Likewise.
	* ld-i386/call1.s: Likewise.
	* ld-i386/call2.d: Likewise.
	* ld-i386/call2.s: Likewise.
	* ld-i386/got1.dd: Likewise.
	* ld-i386/got1.out: Likewise.
	* ld-i386/got1a.S: Likewise.
	* ld-i386/got1b.c: Likewise.
	* ld-i386/got1c.c: Likewise.
	* ld-i386/got1d.S: Likewise.
	* ld-i386/jmp1.d: Likewise.
	* ld-i386/jmp1.s: Likewise.
	* ld-i386/jmp2.d: Likewise.
	* ld-i386/jmp2.s: Likewise.
	* ld-i386/load1.d: Likewise.
	* ld-i386/load1.s: Likewise.
	* ld-i386/load2.d: Likewise.
	* ld-i386/load2.s: Likewise.
	* ld-i386/load3.d: Likewise.
	* ld-i386/load3.s: Likewise.
	* ld-i386/load4.s: Likewise.
	* ld-i386/load4a.d: Likewise.
	* ld-i386/load4b.d: Likewise.
	* ld-i386/load5.s: Likewise.
	* ld-i386/load5a.d: Likewise.
	* ld-i386/load5b.d: Likewise.
	* ld-i386/load6.d: Likewise.
	* ld-i386/load6.s: Likewise.
	* ld-i386/i386.exp: Run branch1, call1, call2, jmp1, jmp2,
	load1, load2, load3, load4a, load4b, load5a, load5b and load6
	tests.  Run got1 test.
2015-10-22 04:47:07 -07:00
Yao Qi
875880c661 Avoid using 'template' C++ keyword
'template' is used in include/opcode/aarch64.h as below,

 typedef struct
 {
   const char *template;
   uint32_t value;
   int has_xt;
 } aarch64_sys_ins_reg;

and it triggers compilation errors when GDB is built in C++ mode.

In file included from git/gdb/aarch64-tdep.c:62:0:
git/gdb/../include/opcode/aarch64.h:651:15: error: expected unqualified-id before 'template'
   const char *template;

This patch is to rename field template to name.

gas/

	* config/tc-aarch64.c (md_begin): Access field 'name' rather
	than 'template'.

include/opcode/

	* aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
	<name>: New field.

opcodes/

	* aarch64-dis.c (aarch64_ext_sysins_op): Access field
	'name' rather than 'template'.
	* aarch64-opc.c (aarch64_print_operand): Likewise.
2015-10-07 15:22:47 +01:00
Yao Qi
d3e12b29ae Wrap include/opcode/aarch64.h in extern "C" for C++
This is sufficient to link an aarch64 GDB built in C++ mode.  Pedro
did something similar in Feb
https://sourceware.org/ml/binutils/2015-02/msg00176.html

include/opcode/

2015-10-07  Yao Qi  <yao.qi@linaro.org>

	* aarch64.h [__cplusplus]: Wrap in extern "C".
2015-10-07 15:07:14 +01:00
Nick Clifton
886a250647 New ARC implementation.
bfd	* archures.c: Remove support for older ARC. Added support for new
	ARC cpus (ARC600, ARC601, ARC700, ARCV2).
	* bfd-in2.h: Likewise.
	* config.bfd: Likewise.
	* cpu-arc.c: Likewise.
	* elf32-arc.c: Totally changed file with a refactored
	inplementation of the ARC port.
	* libbfd.h: Added ARC specific relocation types.
	* reloc.c: Likewise.

gas     * config/tc-arc.c: Revamped file for ARC support.
        * config/tc-arc.h: Likewise.
        * doc/as.texinfo: Add new ARC options.
        * doc/c-arc.texi: Likewise.

ld	* configure.tgt: Added target arc-*-elf* and arc*-*-linux-uclibc*.
	* emulparams/arcebelf_prof.sh: New file
	* emulparams/arcebelf.sh: Likewise.
	* emulparams/arceblinux_prof.sh: Likewise.
	* emulparams/arceblinux.sh: Likewise.
	* emulparams/arcelf_prof.sh: Likewise.
	* emulparams/arcelf.sh: Likewise.
	* emulparams/arclinux_prof.sh: Likewise.
	* emulparams/arclinux.sh: Likewise.
	* emulparams/arcv2elfx.sh: Likewise.
	* emulparams/arcv2elf.sh: Likewise.
	* emultempl/arclinux.em: Likewise.
	* scripttempl/arclinux.sc: Likewise.
	* scripttempl/elfarc.sc: Likewise.
	* scripttempl/elfarcv2.sc: Likewise
	* Makefile.am: Add new ARC emulations.
	* Makefile.in: Regenerate.
	* NEWS: Mention the new feature.

opcodes * arc-dis.c: Revamped file for ARC support
	* arc-dis.h: Likewise.
	* arc-ext.c: Likewise.
	* arc-ext.h: Likewise.
	* arc-opc.c: Likewise.
	* arc-fxi.h: New file.
	* arc-regs.h: Likewise.
	* arc-tbl.h: Likewise.

binutils * readelf.c (get_machine_name): Remove A5 reference. Add ARCompact
	and ARCv2.
	(get_machine_flags): Handle EM_ARCV2 and EM_ARCOMPACT.
	(guess_is_rela): Likewise.
	(dump_relocations): Likewise.
	(is_32bit_abs_reloc): Likewise.
	(is_16bit_abs_reloc): Likewise.
	(is_none_reloc): Likewise.
	* NEWS: Mention the new feature.

include	* dis-asm.h (arc_get_disassembler): Correct declaration.
	* arc-reloc.def: Macro file with definition of all relocation
	types.
	* arc.h: Changed macros for the newly supported ARC cpus.  Altered
	enum defining the supported relocations.
	* common.h: Changed EM_ARC_A5 definition to EM_ARC_COMPACT. Added
	macro for EM_ARC_COMPACT2.
        * arc-func.h: New file.
        * arc.h: Likewise.
2015-10-07 14:20:19 +01:00
Yao Qi
e141d84e89 Make aarch64_zero_register_p declaration starts from column one
include/opcode:

2015-10-02  Yao Qi  <yao.qi@linaro.org>

	* aarch64.h (aarch64_zero_register_p): Move the declaration
	to column one.
2015-10-02 15:43:46 +01:00
Yao Qi
36f4aab18c [aarch64] expose disas_aarch64_insn and rename it to aarch64_decode_insn
We want to use disas_aarch64_insn inside GDB to decode instructions, so
this patch exposes it and rename it to aarch64_decode_insn to follow
the conventions of other interfaces.

include/opcode:

2015-10-02  Yao Qi  <yao.qi@linaro.org>

	* aarch64.h (aarch64_decode_insn): Declare it.

opcodes:

2015-10-02  Yao Qi  <yao.qi@linaro.org>

	* aarch64-dis.c	(disas_aarch64_insn): Remove static.  Change
	argument insn type to aarch64_insn.  Rename to ...
	(aarch64_decode_insn): ... it.
	(print_insn_aarch64_word): Caller updated.
2015-10-02 15:23:58 +01:00
Nick Clifton
6899683948 Resync files in the binutils repository that are maintained in the gcc repository.
.	2015-08-23  Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>

	PR libfortran/54572
	* Makefile.def: Make libgfortran depend on libbacktrace.
	* Makefile.in: Regenerate.

	2015-08-12  Tom de Vries  <tom@codesourcery.com>

	PR other/67092
	PR other/67098
	* configure.ac: Remove --with_host_libstdcxx support.
	* configure: Regenerate.

	2015-08-10  Thomas Schwinge  <thomas@codesourcery.com>
	    Jakub Jelinek  <jakub@redhat.com>

	* configure.ac (noconfigdirs): Don't add "target-libgomp" for target
	nvptx*-*-*.
	* configure: Regenerate.

include	2015-08-14  Pierre-Marie de Rodat  <derodat@adacore.com>

	* dwarf2.def (DW_AT_GNU_bias): New attribute.

	2015-08-14  Pierre-Marie de Rodat  <derodat@adacore.com>

	* dwarf2.def (DW_AT_GNU_numerator, DW_AT_GNU_denominator): New
	attributes.

libiberty  2015-08-15  Ian Lance Taylor  <iant@google.com>

	* cp-demangle.c (d_abi_tags): Preserve di->last_name across any
	ABI tags.
2015-09-30 17:55:16 +01:00
Dominik Vogt
7ecc513a44 Add support for extensions in the .machine pseudoop on S/390, e.g. ".machine zEC12+nohtm+vx"
gas	* doc/c-s390.texi: Add documentation.
	Add missing code markup.
	* config/tc-s390.c (current_flags): New static variable.
	(s390_parse_cpu): Parse cpu flags a la "+nohtm" etc.
	(s390_setup_opcodes): Use cpu flags to determine the set of opcodes.
	Fix indentation.
	(md_parse_option): Call s390_parse_cpu with the new signature.
	(s390_machine): Likewise.
	Keep track of current_flags.
	Simplify code a bit.
	undefine MAX_HISTORY at end of function.
	(s390_machinemode): undefine MAX_HISTORY at end of function.
	Update an error message.

tests	* gas/s390/s390.exp: Add new tests.
	* gas/s390/machine-parsing-1.s: New test file.
	* gas/s390/machine-parsing-1.l: Likewise.
	* gas/s390/machine-parsing-2.s: Likewise.
	* gas/s390/machine-parsing-2.l: Likewise.
	* gas/s390/machine-parsing-3.s: Likewise.
	* gas/s390/machine-parsing-3.l: Likewise.
	* gas/s390/machine-parsing-4.s: Likewise.
	* gas/s390/machine-parsing-4.l: Likewise.
	* gas/s390/machine-parsing-5.s: Likewise.
	* gas/s390/machine-parsing-5.l: Likewise.
	* gas/s390/machine-parsing-6.s: Likewise.
	* gas/s390/machine-parsing-6.l: Likewise.

opcode	* s390.h (S390_INSTR_FLAG_HTM): New flag.
	(S390_INSTR_FLAG_VX): New flag.
	(S390_INSTR_FLAG_FACILITY_MASK): New flag mask.

opcodes	* s390-mkopc.c (main): Parse htm and vx flag.
	* s390-opc.txt: Mark instructions from the hardware transactional
	memory and vector facilities with the "htm"/"vx" flag.
2015-09-29 13:22:07 +01:00
jamesbowman
71f4ed30fe FT32: define macros for instruction recognition.
Other places (e.g. the gdb stack unwinder) can use these instead of
hard-coded patterns.

[include/Changelog]

2015-09-26  James Bowman  <james.bowman@ftdichip.com>

	* opcode/ft32.h: Add instruction macros FT32_*()
2015-09-28 11:23:54 -07:00
Nick Clifton
b6518b3871 Fix compile time warnings generated when compiling with clang.
bfd	* bout.c (b_out_slurp_reloc_table): Cast constant to unsigned in
	order to avoid problems with left shifting negative values.
	(abs32code): Likewise.
	* mach-o.c (FILE_ALIGN): Likewise.
	* coff-rs6000.c (xcoff_debug_sections): Delete unused static
	array.
	* elf32-visium.c (visium_reloc_map): Likewise.
	* elf32-arm.c (elf32_arm_final_link_relocate): Remove useless
	calls to abs function.
	* elf32-frv.c (_frvfdpic_relax_tls_entries): Likewise.
	* elf32-score.c (score_elf_final_link_relocate): Likewise.
	* elf32-score7.c (score_elf_final_link_relocate): Likewise.
	* elf32-i860.c (i860_howto_pc26_reloc): Use multiplication instead
	of shifting to create a negative mask.
	* elf32-msp430.c (elf_backend_special_sections): Define.
	* elfxx-mips.c (got_ofst_reloc_p): Delete unused function.
	(got_hi16_reloc_p): Delete unused function.
	* ppcboot.c (ppcboot_bfd_print_private_bfd_data): Fix test of
	partition name.

gas	* config/tc-ppc.c (insn_validate): Cast PPC_OPSHIFT_INV to an int.

opcode	* ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
	shifting.

ld	* emultempl/elf32.em (ehdr_start_empty): New static variable.
	(before_allocation): Use it to initialise ehdr_start_save.
	* emultempl/pe.em (write_build_id): Remove useless double
	parenthesis.
	* emultempl/pep.em (write_build_id): Likewise.

opcodes	* bfin-dis.c (fmtconst): Remove unnecessary call to the abs
	function.
	* tic30-dis.c (print_branch): Likewise.
	* cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
	value before left shifting.
	* fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
	* hppa-dis.c (print_insn_hppa): Likewise.
	* mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
	array.
	* msp430-dis.c (msp430_singleoperand): Likewise.
	(msp430_doubleoperand): Likewise.
	(print_insn_msp430): Likewise.
	* nds32-asm.c (parse_operand): Likewise.
	* sh-opc.h (MASK): Likewise.
	* v850-dis.c (get_operand_value): Likewise.
2015-09-23 18:05:16 +01:00
Nick Clifton
f04265eceb Enhance the RX disassembler to detect and report bad instructions.
opcode	* rx.h (enum RX_Size): Add RX_Bad_Size entry.

opcodes	* rx-decode.opc (bwl): Use RX_Bad_Size.
	(sbwl): Likewise.
	(ubwl): Likewise.  Rename to ubw.
	(uBWL): Rename to uBW.
	Replace all references to uBWL with uBW.
	* rx-decode.c: Regenerate.
	* rx-dis.c (size_names): Add entry for RX_Bad_Size.
	(opsize_names): Likewise.
	(print_insn_rx): Detect and report RX_Bad_Size.
2015-09-22 17:21:13 +01:00
Rainer Orth
5c383f0262 Solaris PIE support
include/elf:
	* common.h (DF_1_STUB, DF_1_PIE): Define.

	ld:
	* emulparams/solaris2.sh (GENERATE_PIE_SCRIPT): Set to yes.

	* emultempl/elf32.em: Include ldlex.h.
	(gld${EMULATION_NAME}_handle_option) [GENERATE_PIE_SCRIPT]
	<OPTION_PIE>: Set DF_1_PIE.

	binutils:
	* readelf.c (process_dynamic_section): Handle DF_1_STUB, DF_1_PIE.
2015-09-22 11:12:51 +02:00
H.J. Lu
7f7a1bce25 Change ch_type in Elf64_External_Chdr to 4 bytes
The ch_type field in Elf64_External_Chdr is 4 bytes, followed by a
4-byte padding.  This change doesn't introduce any functional change
since only the lower 32 bits of the ch_type field are used.

	* external.h (Elf64_External_Chdr): Change ch_type to 4 bytes
	and add ch_reserved.
2015-09-21 10:19:25 -07:00
Rich Felker
9b8b325a1f Add --no-dynamic-linker option to ld, for static PIE use
Inhibits output of .interp section in ELF executables.

include/
	* bfdlink.h (struct bfd_link_info): Add "nointerp" field.
bfd/
	* elflink.c (_bfd_elf_link_create_dynamic_sections): Don't create
	.interp when info->nointerp.
	(bfd_elf_size_dynamic_sections): Adjust assert.
	* elf32-arm.c (elf32_arm_size_dynamic_sections): Don't size .interp
	when info->nointerp.
	* elf32-bfin.c (elf32_bfinfdpic_size_dynamic_sections): Likewise.
	* elf32-cr16.c (_bfd_cr16_elf_size_dynamic_sections): Likewise.
	* elf32-cris.c (elf_cris_size_dynamic_sections): Likewise.
	* elf32-frv.c (elf32_frvfdpic_size_dynamic_sections): Likewise.
	* elf32-hppa.c (elf32_hppa_size_dynamic_sections): Likewise.
	* elf32-i370.c (i370_elf_size_dynamic_sections): Likewise.
	* elf32-i386.c (elf_i386_size_dynamic_sections): Likewise.
	* elf32-lm32.c (lm32_elf_size_dynamic_sections): Likewise.
	* elf32-m32r.c (m32r_elf_size_dynamic_sections): Likewise.
	* elf32-m68k.c (elf_m68k_size_dynamic_sections): Likewise.
	* elf32-metag.c (elf_metag_size_dynamic_sections): Likewise.
	* elf32-nds32.c (nds32_elf_size_dynamic_sections): Likewise.
	* elf32-nios2.c (nios2_elf32_size_dynamic_sections): Likewise.
	* elf32-or1k.c (or1k_elf_size_dynamic_sections): Likewise.
	* elf32-ppc.c (ppc_elf_size_dynamic_sections): Likewise.
	* elf32-s390.c (elf_s390_size_dynamic_sections): Likewise.
	* elf32-score.c (s3_bfd_score_elf_size_dynamic_sections): Likewise.
	* elf32-score7.c (s7_bfd_score_elf_size_dynamic_sections): Likewise.
	* elf32-sh.c (sh_elf_size_dynamic_sections): Likewise.
	* elf32-tic6x.c (elf32_tic6x_size_dynamic_sections): Likewise.
	* elf32-tilepro.c (tilepro_elf_size_dynamic_sections): Likewise.
	* elf32-vax.c (elf_vax_size_dynamic_sections): Likewise.
	* elf32-xtensa.c (elf_xtensa_size_dynamic_sections): Likewise.
	* elf64-alpha.c (elf64_alpha_size_dynamic_sections): Likewise.
	* elf64-hppa.c (elf64_hppa_size_dynamic_sections): Likewise.
	* elf64-ppc.c (ppc64_elf_size_dynamic_sections): Likewise.
	* elf64-s390.c (elf_s390_size_dynamic_sections): Likewise.
	* elf64-sh64.c (sh64_elf64_size_dynamic_sections): Likewise.
	* elf64-x86-64.c (elf_x86_64_size_dynamic_sections): Likewise.
	* elfnn-aarch64.c (elfNN_aarch64_size_dynamic_sections): Likewise.
	* elfnn-ia64.c (elfNN_ia64_size_dynamic_sections): Likewise.
	* elfxx-mips.c (_bfd_mips_elf_size_dynamic_sections): Likewise.
	* elfxx-sparc.c (_bfd_sparc_elf_size_dynamic_sections): Likewise.
	* elfxx-tilegx.c (tilegx_elf_size_dynamic_sections): Likewise.
ld/
	* ld.texinfo (--no-dynamic-linker): Document.
	* ldlex.h (enum option_values): Add OPTION_NO_DYNAMIC_LINKER.
	* lexsup.c (ld_options, parse_args): Handle --no-dynamic-linker.
2015-09-20 15:52:27 +09:30
Nick Clifton
7bdf96efee Make register name tables in visium.h static in order to prevent multiple definitions.
* visium.h (gen_reg_table): Make static.
	(fp_reg_table): Likewise.
	(cc_table): Likewise.
2015-09-09 14:50:08 +01:00
Alan Modra
5f329d5b14 Reorder enum output_type for better code generation
Works around a gcc bug #67328 for the most commonly used of bfd_link_pic
and bfd_link_executable.

	* bfdlink.h (enum output_type): Reorder enum.
2015-08-23 23:21:48 +09:30
Jiong Wang
49df5539f9 [AArch64][3/6] GAS support TLSLD move/add relocation types
2015-08-19  Jiong Wang  <jiong.wang@arm.com>

bfd/
  * reloc.c (BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12,
  BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0,
  BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC,
  BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1,
  BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC,
  BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2): New entries.
  * elfnn-aarch64.c (elfNN_aarch64_howto_table): Likewise.
  * bfd-in2.h: Regenerate.
  * libbfd.h: Regenerate.

gas/
  * config/tc-aarch64.c (reloc_table): New relocation modifiers,
  "dtprel_hi12", "dtprel_g0", "dtprel_g0_nc", "dtprel_g1",
  "dtprel_g1_nc", "dtprel_g2".
  (md_apply_fix): Support new relocation types.
  (aarch64_force_relocation): Likewise.
  (process_movw_reloc_info): Likewise.

gas/testsuite/
  * gas/aarch64/reloc-dtprel_g0.s: New testcase.
  * gas/aarch64/reloc-dtprel_g0-ilp32.s: Likewise.
  * gas/aarch64/reloc-dtprel_g0_nc.s: Likewise.
  * gas/aarch64/reloc-dtprel_g0_nc-ilp32.s: Likewise.
  * gas/aarch64/reloc-dtprel_g1.s: Likewise.
  * gas/aarch64/reloc-dtprel_g1-ilp32.s: Likewise.
  * gas/aarch64/reloc-dtprel_g1_nc.s: Likewise.
  * gas/aarch64/reloc-dtprel_g2.s: Likewise.
  * gas/aarch64/reloc-dtprel_hi12.s: Likewise.
  * gas/aarch64/reloc-dtprel_hi12-ilp32.s: Likewise.
  * gas/aarch64/reloc-dtprel_g0.d: New expectation file.
  * gas/aarch64/reloc-dtprel_g0-ilp32.d: Likewise.
  * gas/aarch64/reloc-dtprel_g0_nc.d: Likewise.
  * gas/aarch64/reloc-dtprel_g0_nc-ilp32.d: Likewise.
  * gas/aarch64/reloc-dtprel_g1.d: Likewise.
  * gas/aarch64/reloc-dtprel_g1-ilp32.d: Likewise.
  * gas/aarch64/reloc-dtprel_g1_nc.d: Likewise.
  * gas/aarch64/reloc-dtprel_g2.d: Likewise.
  * gas/aarch64/reloc-dtprel_hi12.d: Likewise.
  * gas/aarch64/reloc-dtprel_hi12-ilp32.d: Likewise.
2015-08-19 16:36:22 +01:00
Jiong Wang
13289c10e2 [AArch64][1/6] GAS support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
2015-08-19  Jiong Wang  <jiong.wang@arm.com>

bfd/
  * reloc.c (BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC): New entry.
  * bfd-in2.h: Regenerate.
  * libbfd.h: Regenerate.
  * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for
  BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC.

gas/
  * config/tc-aarch64.c (reloc_table): New relocation modifiers.
  (md_apply_fix): Support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC.
  (aarch64_force_relocation): Likewise.

gas/testsuite/
  * gas/aarch64/reloc-dtprel_lo12_nc.s: New testcase.
  * gas/aarch64/reloc-dtprel_lo12_nc-ilp32.s: Likewise.
  * gas/aarch64/reloc-dtprel_lo12_nc.d: New expectation file.
  * gas/aarch64/reloc-dtprel_lo12_nc-ilp32.d: Likewise.
2015-08-19 16:28:08 +01:00
Alan Modra
64d94ba01a Remove link_info.pic
Adding type_pie to output_type allows us to remove link_info.pic and
with some reordering of the enum, produces better code.

include/
	* bfdlink.h (enum output_type): Delete type_executable, add type_pde
	and type_pie.  Reorder.
	(struct bfd_link_info): Delete pic field.
	(bfd_link_executable, bfd_link_pde, bfd_link_pie, bfd_link_pic): Adjust.
ld/
	* emultempl/aix.em: Don't set link_info.pic.
	* emultempl/pe.em: Likewise.
	* emultempl/pep.em: Likewise.
	* emultempl/sunos.em: Likewise.
	* lexsup.c (parse_args): Likewise.  Set type_pie for -pie.
	* plugin.c (set_tv_header <LDPT_LINKER_OUTPUT>): Simplify.
2015-08-19 12:53:54 +09:30
Alan Modra
3cbc1e5e68 Add bfd_link_pde, and simplify some tests of link_info.type
include/
	* bfdlink.h (bfd_link_pde): Define.
bfd/
	* elf-s390-common.c: Simplify expressions using
	bfd_linke_executable, bfd_link_pie and bfd_link_pic.
	* elf32-arm.c: Likewise.
	* elf32-bfin.c: Likewise.
	* elf32-frv.c: Likewise.
	* elf32-m68k.c: Likewise.
	* elf32-nios2.c: Likewise.
	* elf32-ppc.c: Likewise.
	* elf32-s390.c: Likewise.
	* elf32-sh.c: Likewise.
	* elf64-alpha.c: Likewise.
	* elf64-ppc.c: Likewise.
	* elf64-s390.c: Likewise.
	* elflink.c: Likewise.
2015-08-19 12:51:06 +09:30
H.J. Lu
0e1862bb40 Add output_type to bfd_link_info
The "shared" field in bfd_link_info is set for both DSO and and PIE.
There are separate fields for executable and relocatable outputs.  This
patch adds an "output_type" field:

enum output_type
{
  type_unknown = 0,
  type_executable,
  type_dll,
  type_relocatable
};

and a "pic" field to bfd_link_info to replace shared, executable and
relocatable fields so that we can use the "output_type" field to check
for output type and the "pic" field check if output is PIC.  Macros,
bfd_link_executable, bfd_link_dll, bfd_link_relocatable, bfd_link_pic
and bfd_link_pie, are provided to check for output features.

bfd/

	* bfd/aoutx.h: Replace shared, executable, relocatable and pie
	fields with bfd_link_executable, bfd_link_dll,
	bfd_link_relocatable, bfd_link_pic and bfd_link_pie.
	* bfd/bout.c: Likewise.
	* bfd/coff-alpha.c: Likewise.
	* bfd/coff-arm.c: Likewise.
	* bfd/coff-i386.c: Likewise.
	* bfd/coff-i960.c: Likewise.
	* bfd/coff-m68k.c: Likewise.
	* bfd/coff-mcore.c: Likewise.
	* bfd/coff-mips.c: Likewise.
	* bfd/coff-ppc.c: Likewise.
	* bfd/coff-rs6000.c: Likewise.
	* bfd/coff-sh.c: Likewise.
	* bfd/coff-tic80.c: Likewise.
	* bfd/coff-x86_64.c: Likewise.
	* bfd/coff64-rs6000.c: Likewise.
	* bfd/coffgen.c: Likewise.
	* bfd/cofflink.c: Likewise.
	* bfd/ecoff.c: Likewise.
	* bfd/ecofflink.c: Likewise.
	* bfd/elf-bfd.h: Likewise.
	* bfd/elf-eh-frame.c: Likewise.
	* bfd/elf-ifunc.c: Likewise.
	* bfd/elf-m10200.c: Likewise.
	* bfd/elf-m10300.c: Likewise.
	* bfd/elf-s390-common.c: Likewise.
	* bfd/elf-vxworks.c: Likewise.
	* bfd/elf.c: Likewise.
	* bfd/elf32-arm.c: Likewise.
	* bfd/elf32-avr.c: Likewise.
	* bfd/elf32-bfin.c: Likewise.
	* bfd/elf32-cr16.c: Likewise.
	* bfd/elf32-cr16c.c: Likewise.
	* bfd/elf32-cris.c: Likewise.
	* bfd/elf32-crx.c: Likewise.
	* bfd/elf32-d10v.c: Likewise.
	* bfd/elf32-dlx.c: Likewise.
	* bfd/elf32-epiphany.c: Likewise.
	* bfd/elf32-fr30.c: Likewise.
	* bfd/elf32-frv.c: Likewise.
	* bfd/elf32-ft32.c: Likewise.
	* bfd/elf32-h8300.c: Likewise.
	* bfd/elf32-hppa.c: Likewise.
	* bfd/elf32-i370.c: Likewise.
	* bfd/elf32-i386.c: Likewise.
	* bfd/elf32-i860.c: Likewise.
	* bfd/elf32-ip2k.c: Likewise.
	* bfd/elf32-iq2000.c: Likewise.
	* bfd/elf32-lm32.c: Likewise.
	* bfd/elf32-m32c.c: Likewise.
	* bfd/elf32-m32r.c: Likewise.
	* bfd/elf32-m68hc11.c: Likewise.
	* bfd/elf32-m68hc1x.c: Likewise.
	* bfd/elf32-m68k.c: Likewise.
	* bfd/elf32-mcore.c: Likewise.
	* bfd/elf32-mep.c: Likewise.
	* bfd/elf32-metag.c: Likewise.
	* bfd/elf32-microblaze.c: Likewise.
	* bfd/elf32-moxie.c: Likewise.
	* bfd/elf32-msp430.c: Likewise.
	* bfd/elf32-mt.c: Likewise.
	* bfd/elf32-nds32.c: Likewise.
	* bfd/elf32-nios2.c: Likewise.
	* bfd/elf32-or1k.c: Likewise.
	* bfd/elf32-ppc.c: Likewise.
	* bfd/elf32-rl78.c: Likewise.
	* bfd/elf32-rx.c: Likewise.
	* bfd/elf32-s390.c: Likewise.
	* bfd/elf32-score.c: Likewise.
	* bfd/elf32-score7.c: Likewise.
	* bfd/elf32-sh-symbian.c: Likewise.
	* bfd/elf32-sh.c: Likewise.
	* bfd/elf32-sh64.c: Likewise.
	* bfd/elf32-spu.c: Likewise.
	* bfd/elf32-tic6x.c: Likewise.
	* bfd/elf32-tilepro.c: Likewise.
	* bfd/elf32-v850.c: Likewise.
	* bfd/elf32-vax.c: Likewise.
	* bfd/elf32-visium.c: Likewise.
	* bfd/elf32-xc16x.c: Likewise.
	* bfd/elf32-xstormy16.c: Likewise.
	* bfd/elf32-xtensa.c: Likewise.
	* bfd/elf64-alpha.c: Likewise.
	* bfd/elf64-hppa.c: Likewise.
	* bfd/elf64-ia64-vms.c: Likewise.
	* bfd/elf64-mmix.c: Likewise.
	* bfd/elf64-ppc.c: Likewise.
	* bfd/elf64-s390.c: Likewise.
	* bfd/elf64-sh64.c: Likewise.
	* bfd/elf64-x86-64.c: Likewise.
	* bfd/elflink.c: Likewise.
	* bfd/elfnn-aarch64.c: Likewise.
	* bfd/elfnn-ia64.c: Likewise.
	* bfd/elfxx-mips.c: Likewise.
	* bfd/elfxx-sparc.c: Likewise.
	* bfd/elfxx-tilegx.c: Likewise.
	* bfd/i386linux.c: Likewise.
	* bfd/linker.c: Likewise.
	* bfd/m68klinux.c: Likewise.
	* bfd/pdp11.c: Likewise.
	* bfd/pe-mips.c: Likewise.
	* bfd/peXXigen.c: Likewise.
	* bfd/reloc.c: Likewise.
	* bfd/reloc16.c: Likewise.
	* bfd/sparclinux.c: Likewise.
	* bfd/sunos.c: Likewise.
	* bfd/vms-alpha.c: Likewise.
	* bfd/xcofflink.c: Likewise.

include/

	* include/bfdlink.h (output_type): New enum.
	(bfd_link_executable): New macro.
	(bfd_link_dll): Likewise.
	(bfd_link_relocatable): Likewise.
	(bfd_link_pic): Likewise.
	(bfd_link_pie): Likewise.
	(bfd_link_info): Remove shared, executable, pie and relocatable.
	Add output_type and pic.

ld/

	* ld/ldctor.c: Replace shared, executable, relocatable and pie
	fields with bfd_link_executable, bfd_link_dll,
	bfd_link_relocatable, bfd_link_pic and bfd_link_pie.
	* ld/ldemul.c: Likewise.
	* ld/ldfile.c: Likewise.
	* ld/ldlang.c: Likewise.
	* ld/ldmain.c: Likewise.
	* ld/ldwrite.c: Likewise.
	* ld/lexsup.c: Likewise.
	* ld/pe-dll.c: Likewise.
	* ld/plugin.c: Likewise.
	* ld/emultempl/aarch64elf.em: Likewise.
	* ld/emultempl/aix.em: Likewise.
	* ld/emultempl/alphaelf.em: Likewise.
	* ld/emultempl/armcoff.em: Likewise.
	* ld/emultempl/armelf.em: Likewise.
	* ld/emultempl/avrelf.em: Likewise.
	* ld/emultempl/beos.em: Likewise.
	* ld/emultempl/cr16elf.em: Likewise.
	* ld/emultempl/elf-generic.em: Likewise.
	* ld/emultempl/elf32.em: Likewise.
	* ld/emultempl/genelf.em: Likewise.
	* ld/emultempl/generic.em: Likewise.
	* ld/emultempl/gld960.em: Likewise.
	* ld/emultempl/gld960c.em: Likewise.
	* ld/emultempl/hppaelf.em: Likewise.
	* ld/emultempl/irix.em: Likewise.
	* ld/emultempl/linux.em: Likewise.
	* ld/emultempl/lnk960.em: Likewise.
	* ld/emultempl/m68hc1xelf.em: Likewise.
	* ld/emultempl/m68kcoff.em: Likewise.
	* ld/emultempl/m68kelf.em: Likewise.
	* ld/emultempl/metagelf.em: Likewise.
	* ld/emultempl/mipself.em: Likewise.
	* ld/emultempl/mmo.em: Likewise.
	* ld/emultempl/msp430.em: Likewise.
	* ld/emultempl/nds32elf.em: Likewise.
	* ld/emultempl/needrelax.em: Likewise.
	* ld/emultempl/nios2elf.em: Likewise.
	* ld/emultempl/pe.em: Likewise.
	* ld/emultempl/pep.em: Likewise.
	* ld/emultempl/ppc32elf.em: Likewise.
	* ld/emultempl/ppc64elf.em: Likewise.
	* ld/emultempl/sh64elf.em: Likewise.
	* ld/emultempl/solaris2.em: Likewise.
	* ld/emultempl/spuelf.em: Likewise.
	* ld/emultempl/sunos.em: Likewise.
	* ld/emultempl/tic6xdsbt.em: Likewise.
	* ld/emultempl/ticoff.em: Likewise.
	* ld/emultempl/v850elf.em: Likewise.
	* ld/emultempl/vms.em: Likewise.
	* ld/emultempl/vxworks.em: Likewise.
2015-08-18 05:51:19 -07:00
H.J. Lu
dd419f3aac Sync ansidecl.h with GCC
Sync with GCC
	2015-08-11  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>

	* ansidecl.h (GCC_FINAL): New macro.
2015-08-12 05:02:21 -07:00
Jiong Wang
70151fb54a [AArch64][7/8] GAS support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
2015-08-11  Jiong Wang  <jiong.wang@arm.com>

include/elf/
  * aarch64.h (R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12): Define.

bfd/
  * reloc.c (BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12): New entry.
  * bfd-in2.h: Regenerate.
  * libbfd.h: Regenerate.
  * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for
  BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.

gas/
  * config/tc-aarch64.c (reloc_table): New relocation modifiers
  "dtprel_lo12".
  (md_apply_fix): Support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
  (aarch64_force_relocation): Likewise.

gas/testsuite/
  * gas/aarch64/reloc-dtprel_lo12-1.s: New testcase.
  * gas/aarch64/reloc-dtprel_lo12-ilp32-1.s: Likewise.
  * gas/aarch64/reloc-dtprel_lo12-1.d: New expectation file.
  * gas/aarch64/reloc-dtprel_lo12-ilp32-1.d: Likewise.
2015-08-11 21:26:31 +01:00
Jiong Wang
56a2e4507a [AArch64][4/8] Add R_AARCH64_P32_TLSLD_ADD_LO12_NC in elf header
2015-08-11  Jiong Wang  <jiong.wang@arm.com>

include/elf/
  * aarch64.h (R_AARCH64_P32_TLSLD_ADD_LO12_NC): Define.
2015-08-11 21:25:32 +01:00
Jiong Wang
2c0a466a7f [AArch64][1/8] Add R_AARCH64_P32_TLSLD_ADR_PAGE21 in elf header
2015-08-11  Jiong Wang  <jiong.wang@arm.com>

include/elf/
  * aarch64.h (R_AARCH64_P32_TLSLD_ADR_PAGE21): Define.
2015-08-11 21:15:52 +01:00
H.J. Lu
72f4393d8c Remove leading/trailing white spaces in ChangeLog 2015-07-24 04:16:47 -07:00
Matthew Wahab
f33026a965 [ARM] Support correctly spelled ARMv6KZ architecture names
2015-07-20  Matthew Wahab  <matthew.wahab@arm.com>

gas/
    * NEWS: Mention corrected spelling of armv6kz.
    * config/tc-arm.c (arm_cpus): Replace ARM_ARCH_V6ZK with
    ARM_ARCH_V6KZ.
    (arm_archs): Likewise. Also add "armv6kz" and "armv6kzt2".
    * doc/c-arm.texi: Replace "armv6zk" with "armv6kz".

gas/testsuite

    * gas/arm/attr-march-armv6kz.d: New.
    * gas/arm/attr-march-armv6kzt2.d: New.

include/opcode

    * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
    (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
    (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
    (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
2015-07-21 09:43:35 +01:00
Jiong Wang
53e8fd0f07 [AArch64][1/3] Add R_AARCH64_P32_TLSLD_ADR_PREL21 in elf header 2015-07-16 15:38:32 +01:00
H.J. Lu
dc2edb520a Sync longlong.h with GCC
Sync with GCC
	2014-10-28  Richard Henderson  <rth@redhat.com>

	* longlong.h [__alpha] (umul_ppmm): Disable for c++.
2015-07-14 09:18:16 -07:00
H.J. Lu
d0270d8cb9 Sync hashtab.h, splay-tree.h with GCC
Sync with GCC
	2014-12-09  Trevor Saunders  <tsaunders@mozilla.com>

	* hashtab.h, splay-tree.h: Remove GTY markers.
2015-07-14 09:18:16 -07:00
H.J. Lu
1d83d382de Remove trailing spaces in demangle.h 2015-07-14 09:18:16 -07:00
H.J. Lu
4d6404f01d Sync ansidecl.h with GCC
Sync with GCC
	2015-03-02  Markus Trippelsdorf  <markus@trippelsdorf.de>

	PR target/65261
	* ansidecl.h (ATTRIBUTE_NO_SANITIZE_UNDEFINED): New macro.
2015-07-14 09:18:16 -07:00
Catherine Moore
3350cc01de 2015-07-09 Catherine Moore <clm@codesourcery.com>
include/
        * elf/mips/mips.h (Val_GNU_MIPS_ABI_FP_NAN2008): New.

        gas/
        * config/tc-mips.c (check_fpabi):  Handle
        VAL_GNU_MIPS_ABI_FP_NAN2008.

        binutils/
        * readelf.c (print_mips_fp_abi_value): Handle
        Val_GNU_MIPS_ABI_FP_NAN2008.

        ld/testsuite/
        * ld-mips-elf/attr-gnu-4-08.d: Update expected output.
        * ld-mips-elf/attr-gnu-4-09.d: New.
        * ld-mips-elf/attr-gnu-4-19.d: New.
        * ld-mips-elf/attr-gnu-4-29.d: New.
        * ld-mips-elf/attr-gnu-4-39.d: New.
        * ld-mips-elf/attr-gnu-4-49.d: New.
        * ld-mips-elf/attr-gnu-4-59.d: New.
        * ld-mips-elf/attr-gnu-4-69.d: New.
        * ld-mips-elf/attr-gnu-4-79.d: New.
        * ld-mips-elf/attr-gnu-4-89.d: New.
        * ld-mips-elf/attr-gnu-4-9.s: New.
        * ld-mips-elf/mips-elf.exp: Run new tests.
2015-07-09 08:26:10 -07:00
Denis Chertykov
328e7bfdde Define DIFF_EXPR_OK for avr target to allow PC relative difference relocation.
When generating relocation (tc_gen_reloc) 32 bit relocation fixup
is changed to new 32 bit PC relative relocation if the fixup has pc-relative
flag set.

bfd/ChangeLog

2015-07-06  Pitchumani Sivanupandi <pitchumani.s@atmel.com>

    * elf32-avr.c: Add 32 bit PC relative relocation for AVR target.

gas/ChangeLog

2015-07-06  Pitchumani Sivanupandi <pitchumani.s@atmel.com>

    * config/tc-avr.c (tc_gen_reloc): Change 32 bit relocation to
    32 bit PC relative and update offset if the fixup is pc-relative.
    * config/tc-avr.h (DIFF_EXPR_OK): Define to enable PC relative diff
    relocs.

gas/testsuite/ChangeLog

2015-07-06  Pitchumani Sivanupandi <pitchumani.s@atmel.com>

    * gas/avr/pc-relative-reloc.d: New test for 32 bit pc relative reloc.
    * gas/avr/per-function-debugline.s: New test source.

include/ChangeLog

2015-07-06  Pitchumani Sivanupandi <pitchumani.s@atmel.com>

    * elf/avr.h: Add new 32 bit PC relative relocation.

ld/testsuite/ChangeLog

2015-07-06  Pitchumani Sivanupandi <pitchumani.s@atmel.com>

    * ld-avr/gc-section-debugline.d: New test.
    * ld-avr/per-function-debugline.s: Source for new test.
2015-07-08 21:41:52 +03:00
Alan Modra
ef5a96d564 Remove ppc860, ppc750cl, ppc7450 insns from common ppc.
Back in the day support for these processors was added, we probably
didn't want to waste PPC_OPCODE bits on minor variations.  I've had a
complaint that disassembly of mfspr/mtspr was wrong for power8.  This
patch fixes that problem.

Note that since -m860/-m850/-m821 are new gas options enabling the
mpc8xx specific mfspr/mtspr variants it is possible that this change
will break some mpc8xx assembly code.  ie. you might need to modify
makefiles to pass -m860 to gas.

include/opcode/
	* ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
opcodes/
	* ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
	* ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
	PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
gas/
	* config/tc-ppc.c (md_show_usage): Add -m821, -m850, -m860.
	* doc/c-ppc.texi (PowerPC-Opts): Likewise.
gas/testsuite/
	* gas/ppc/titan.d: Correct mfmcsrr0 disassembly.
2015-07-03 10:57:14 +09:30
Sandra Loosemore
c8c8175b62 Opcodes and assembler support for Nios II R2
2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
	    Cesar Philippidis  <cesar@codesourcery.com>

	gas/
	* config/tc-nios2.c (nios2_min_align): New.
	(nop): Replace with....
	(nop_r1, nop_r2, nop_r2_cdx, nop32, nop16): New.
	(nios2_align): Handle alignment on 2-byte boundaries when CDX
	instructions may be present.
	(s_nios2_align): Adjust reference to nop.
	(CDXBRANCH, IS_CDXBRANCH): New.
	(CDX_UBRANCH_SUBTYPE, CDX_CBRANCH_SUBTYPE): New.
	(nios2_relax_subtype_size): Handle 2-byte CDX branches.
	(nios2_relax_frag): Likewise.
	(md_convert_frag): Handle R2 encodings.
	(nios2_check_overflow): Check that low-order bits are zero
	before applying rightshift from howto.
	(nios2_check_overflow): Correct negative overflow calculation.
	(nios2_diagnose_overflow): Handle signed_immed12_overflow.  Issue
	generic overflow messages for miscellaneous instruction formats.
	(md_apply_fix): Recognize new R2 relocations.  For pc_relative
	relocations, store fixup in *valP.
	(nios2_reglist_mask, nios2_reglist_dir): New.
	(nios2_parse_reglist): New.
	(nios2_parse_base_register): New.
	(nios2_assemble_expression): Handle constant expressions designated
	by BFD_RELOC_NONE.
	(nios2_assemble_reg3): New.
	(nios2_assemble_arg_c): Handle R2 instruction formats.
	(nios2_assemble_arg_d): Likewise.
	(nios2_assemble_arg_s): Likewise.
	(nios2_assemble_arg_t): Likewise.
	(nios2_assemble_arg_D): New.
	(nios2_assemble_arg_S): New.
	(nios2_assemble_arg_T): New.
	(nios2_assemble_arg_i): Handle R2 instruction formats.
	(nios2_assemble_arg_I): New.
	(nios2_assemble_arg_u): Handle R2 instruction formats.
	(nios2_assemble_arg_U): New.
	(nios2_assemble_arg_V): New.
	(nios2_assemble_arg_W): New.
	(nios2_assemble_arg_X): New.
	(nios2_assemble_arg_Y): New.
	(nios2_assemble_arg_o): Handle R2 instruction formats.
	(nios2_assemble_arg_O): New.
	(nios2_assemble_arg_P): New.
	(nios2_assemble_arg_j): Handle R2 instruction formats.
	(nios2_assemble_arg_k): New.
	(nios2_assemble_arg_l): Handle R2 instruction formats.
	(nios2_assemble_arg_m): Likewise.
	(nios2_assemble_arg_M): New.
	(nios2_assemble_arg_N): New.
	(nios2_assemble_arg_e): New.
	(nios2_assemble_arg_f): New.
	(nios2_assemble_arg_g): New.
	(nios2_assemble_arg_h): New.
	(nios2_assemble_arg_R): New.
	(nios2_assemble_arg_B): New.
	(nios2_assemble_args): Handle new argument letters.
	(nios2_consume_arg): Likewise.
	(nios2_translate_pseudo_insn): Avoid dereferencing null pointer
	in error message.
	(nios2_ps_insn_info_structs): Add nop.n.
	(output_ubranch): Handle CDX branches.
	(output_cbranch): Likewise.
	(output_call): Handle R2 encodings.
	(output_movia): Likewise.
	(md_begin): Initialize nios2_min_align.
	(md_assemble): Align to nios2_min_align.  Adjust nios2_min_align
	if a 16-bit instruction is seen.
	(nios2_cons_align): Use appropriate nop pattern.

	include/opcode/
	* nios2.h (enum iw_format_type): Add R2 formats.
	(enum overflow_type): Add signed_immed12_overflow and
	enumeration_overflow for R2.
	(struct nios2_opcode): Document new argument letters for R2.
	(REG_3BIT, REG_LDWM, REG_POP): Define.
	(includes): Include nios2r2.h.
	(nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
	(nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
	(nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
	(nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
	(nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
	(nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
	Declare.
	* nios2r2.h: New file.

	opcodes/
	* nios2-dis.c (nios2_extract_opcode): New.
	(nios2_disassembler_state): New.
	(nios2_find_opcode_hash): Use mach parameter to select correct
	disassembler state.
	(nios2_print_insn_arg): Extend to support new R2 argument letters
	and formats.
	(print_insn_nios2): Check for 16-bit instruction at end of memory.
	* nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
	(NIOS2_NUM_OPCODES): Rename to...
	(NIOS2_NUM_R1_OPCODES): This.
	(nios2_r2_opcodes): New.
	(NIOS2_NUM_R2_OPCODES): New.
	(nios2_num_r2_opcodes): New.
	(nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
	(nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
	(nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
	(nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
	(nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):	New.
2015-07-01 16:08:03 -07:00
Sandra Loosemore
8c163c5a87 Relocations for Nios II R2
2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
	    Cesar Philippidis  <cesar@codesourcery.com>

	bfd/
	* bfd-in2.h: Regenerated.
	* elf32-nios2.c (elf_nios2_howto_table_rel): Rename to...
	(elf_nios2_r1_howto_table_rel): This.
	(elf_nios2_r2_howto_table_rel): New.
	(BFD_IS_R2): New.
	(lookup_howto): Add ABFD parameter.  Adjust to look up in either
	the R1 or R2 relocation table, as determined by ABFD.
	(nios2_reloc_map): Add R2 relocations.
	(nios2_elf32_bfd_reloc_type_lookup): Do lookup using lookup_howto.
	Pass it the ABFD parameter.
	(nios2_elf32_bfd_reloc_name_lookup): Use ABFD to decide whether to
	return an R1 or R2 relocation.
	(nios2_elf32_info_to_howto): Do lookup using lookup_howto.
	Pass it the ABFD parameter.
	(nios2_elf32_do_call26_relocate): Check for alignment on a 4-byte
	boundary.
	(nios2_elf32_relocate_section): Adjust call to lookup_howto.
	* libbfd.h: Regenerated.
	* reloc.c (BFD_RELOC_NIOS2_R2_S12): New.
	(BFD_RELOC_NIOS2_R2_I10_1_PCREL): New.
	(BFD_RELOC_NIOS2_R2_T1I7_1_PCREL): New.
	(BFD_RELOC_NIOS2_R2_T1I7_2): New.
	(BFD_RELOC_NIOS2_R2_T2I4): New.
	(BFD_RELOC_NIOS2_R2_T2I4_1): New.
	(BFD_RELOC_NIOS2_R2_T2I4_2): New.
	(BFD_RELOC_NIOS2_R2_X1I7_2): New.
	(BFD_RELOC_NIOS2_R2_X2L5): New.
	(BFD_RELOC_NIOS2_R2_F1I5_2): New.
	(BFD_RELOC_NIOS2_R2_L5I4X1): New.
	(BFD_RELOC_NIOS2_R2_T1X1I6): New.
	(BFD_RELOC_NIOS2_R2_T1X1I6_2): New.

	include/elf/
	* nios2.h (R_NIOS2_R2_S12): New.
	(R_NIOS2_R2_I10_1_PCREL): New.
	(R_NIOS2_R2_T1I7_1_PCREL): New.
	(R_NIOS2_R2_T1I7_2): New.
	(R_NIOS2_R2_T2I4): New.
	(R_NIOS2_R2_T2I4_1): New.
	(R_NIOS2_R2_T2I4_2): New.
	(R_NIOS2_R2_X1I7_2): New.
	(R_NIOS2_R2_X2L5): New.
	(R_NIOS2_R2_F1I5_2): New.
	(R_NIOS2_R2_L5I4X1): New.
	(R_NIOS2_R2_T1X1I6): New.
	(R_NIOS2_R2_T1X1I6_2): New.
	(R_NIOS2_ILLEGAL): Renumber.
2015-07-01 16:02:09 -07:00
Sandra Loosemore
965b1d8083 Add Nios II arch flags and compatibility tests
2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
	    Cesar Philippidis  <cesar@codesourcery.com>

	bfd/
	* archures.c (bfd_mach_nios2r1, bfd_mach_nios2r2): New.
	* bfd-in2.h: Regenerated.
	* cpu-nios2.c (nios2_compatible): New.
	(N): Use nios2_compatible instead of bfd_default_compatible.
	(NIOS2R1_NEXT, NIOS2R2_NEXT): Define.
	(arch_info_struct): New.
	(bfd_nios2_arch): Chain to NIOS2R1_NEXT.
	* elf32-nios2.c (is_nios2_elf): New.
	(nios2_elf32_merge_private_bfd_data): New.
	(nios2_elf32_object_p): New.
	(bfd_elf32_bfd_merge_private_bfd_data): Define.
	(elf_backend_object_p): Define.

	gas/
	* config/tc-nios2.c: Adjust includes.
	(OPTION_MARCH): Define.
	(md_longopts): Add -march option.
	(nios2_architecture): New.
	(nios2_use_arch): New.
	(md_parse_option): Handle OPTION_MARCH.
	(md_show_usage): Document -march.
	(md_begin): Set arch in BFD.
	(nios2_elf_final_processing): New.
	* config/tc-nios2.h (elf_tc_final_processing): Define.
	(nios2_elf_final_processing): New.
	* doc/c-nios2.texi (-march): Add documentation.

	include/elf/
	* nios2.h (EF_NIOS2_ARCH_R1, EF_NIOS2_ARCH_R2): Define.

	ld/testsuite/
	* ld-nios2/mixed1a.d: New.
	* ld-nios2/mixed1a.s: New.
	* ld-nios2/mixed1b.d: New.
	* ld-nios2/mixed1b.s: New.
	* ld-nios2/nios2.exp: Build the new compatibility tests.
2015-07-01 15:55:28 -07:00
Matthew Fortune
a5499fa464 Add support for DT_MIPS_RLD_MAP_REL.
This tag makes it possible to access the debug map when debugging position
independent executables.

bfd/

	* elfxx-mips.c (_bfd_mips_elf_create_dynamic_sections): Use executable
	instead of !shared to indicate an application vs shared library.
	(_bfd_mips_elf_size_dynamic_sections): Likewise.
	(_bfd_mips_elf_finish_dynamic_sections): Handle DT_MIPS_RLD_MAP_REL.
	(_bfd_mips_elf_get_target_dtag): Likewise.

binutils/

	* readelf.c (get_mips_dynamic_type): Handle DT_MIPS_RLD_MAP_REL.

include/

	* elf/mips.h (DT_MIPS_RLD_MAP_REL): New macro.

ld/testsuite/

	* ld-mips-elf/pic-and-nonpic-3b.ad: Adjust for extra dynamic tag.
	* ld-mips-elf/pic-and-nonpic-4b.ad: Likewise.
	* ld-mips-elf/pic-and-nonpic-5b.ad: Likewise.
	* ld-mips-elf/pic-and-nonpic-6-n32.ad: Likewise.
	* ld-mips-elf/pic-and-nonpic-6-n64.ad: Likewise.
	* ld-mips-elf/pic-and-nonpic-6-o32.ad: Likewise.
	* ld-mips-elf/tlsdyn-o32-1.d: Likewise.
	* ld-mips-elf/tlsdyn-o32-1.got: Likewise.
	* ld-mips-elf/tlsdyn-o32-2.d: Likewise.
	* ld-mips-elf/tlsdyn-o32-2.got: Likewise.
	* ld-mips-elf/tlsdyn-o32-3.d: Likewise.
	* ld-mips-elf/tlsdyn-o32-3.got: Likewise.
	* ld-mips-elf/tlsdyn-o32.d: Likewise.
	* ld-mips-elf/tlsdyn-o32.got: Likewise.
	* ld-mips-elf/pie-n32.d: New file.
	* ld-mips-elf/pie-n64.d: Likewise.
	* ld-mips-elf/pie-o32.d: Likewise.
	* ld-mips-elf/pie.s: Likewise.
	* ld-mips-elf/mips-elf.exp: Add new tests.
2015-06-26 11:53:33 +01:00
Iain Buclaw
f91ca6bc00 Sync libiberty from GCC, replaying updates to configure scripts 2015-06-24 21:43:02 +02:00
Nick Clifton
bdc4de1b24 Stop "objdump -d" from disassembling past a symbolic address.
include	* dis-asm.h (struct disassemble_info): Add stop_vma field.

binuti  * objdump.c (disassemble_bytes): Set the stop_vma field in the
	disassemble_info structure when disassembling code sections with
	-d.
	* doc/binutils.texi (objdump): Document the discrepancy between -d
	and -D.

opcodes	* dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
	requested region lies beyond it.
	* bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
	looking for 32-bit insns.
	* mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
	data.
	* sh-dis.c (print_insn_sh): Likewise.
	* tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
	blocks of instructions.
	* vax-dis.c (print_insn_vax): Check that the requested address
	does not clash with the stop_vma.

tests	* gas/arm/backslash-at.s: Add extra .byte directives so that the
	foo symbol does not appear to point half way through an
	instruction.
	* gas/arm/backslash-at.d: Update expected disassembly.
	* gas/i386/ilp32/x86-64-opcode-inval-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-opcode-inval.d: Likewise.
	* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
	* gas/i386/x86-64-opcode-inval.d: Likewise.
2015-06-22 16:53:27 +01:00
Peter Bergner
11a0cf2ec0 Allow for optional operands with non-zero default values.
ISA 2.07 (ie, POWER8) added the rfebb instruction which takes one operand
with the value of either a 0 or 1.  It also defines an extended mnemonic
with no operands (ie, "rfebb") that is supposed to be equivalent to "rfebb 1".
I implemented rfebb's lone operand with PPC_OPERAND_OPTIONAL, but the
problem is, optional operands that are ommitted always default to the
value 0, which is wrong in this case.  I have added support for allowing
non-zero default values by adding an additional flag PPC_OPERAND_OPTIONAL_VALUE
that specifies that the default operand value to be used is stored in the
SHIFT field of the operand field immediately following this one.

This fixes the rfebb issue.  I also fixed the mftb and mfcr instructions
so they use the same mechanism.  This allows us to flag invalid uses of
mfcr where we explicitly pass in a zero FXM value, like the use in a2.[sd].

include/opcode/

	* ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
	(ppc_optional_operand_value): New inline function.

opcodes/
	* ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
	* ppc-opc.c (FXM4): Add non-zero optional value.
	(TBR): Likewise.
	(SXL): Likewise.
	(insert_fxm): Handle new default operand value.
	(extract_fxm): Likewise.
	(insert_tbr): Likewise.
	(extract_tbr): Likewise.

gas/
	* config/tc-ppc.c (md_assemble): Use ppc_optional_operand_value.
	Allow for optional operands without insert functions.

gas/testsuite/
	* gas/ppc/power8.d: Fixup rfebb test results.
	* gas/ppc/a2.s: Fix invalid mfcr test.
	* gas/ppc/a2.d: Likewise.
2015-06-19 17:17:07 -05:00
Mike Frysinger
6362a3f875 sim: callback: add human readable strings for debugging to maps
When tracing, we often want to display the human readable name for the
various syscall/errno values.  Rather than make each target duplicate
the lookup, extend the existing maps to include the string directly,
and add helper functions to look up the constants.

While most targets are autogenerated (from libgloss), the bfin/cris
targets have custom maps for the Linux ABI which need to be updated
by hand.
2015-06-17 13:19:51 -04:00
Matthew Wahab
88f0ea342d [AArch64] Add support for ARMv8.1 command line option 2015-06-04 11:14:07 +01:00
Matthew Wahab
a5932920ef [ARM] Support for ARMv8.1 command line option
2015-06-03  Matthew Wahab  <matthew.wahab@arm.com>

gas/
	* config/tc-arm.c (arm_archs): Add "armv8.1-a".
	* doc/c-arm.texi (ARM Options, -march): Add "armv8.1-a".
	* NEWS: Mention ARMv8.1 support.

include/opcode/
	* arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
	(ARM_ARCH_V8_1A): New.
	(ARM_ARCH_V8_1A_FP): New.
	(ARM_ARCH_V8_1A_SIMD): New.
	(ARM_ARCH_V8_1A_CRYPTOV1): New.
	(ARM_FEATURE_CORE): New.
2015-06-03 10:03:50 +01:00
Matthew Wahab
d6b4b13ed2 [ARM] Support for ARMv8.1 Adv.SIMD extension 2015-06-02 12:37:33 +01:00
Matthew Wahab
ddfded2f7b [ARM] Add support for ARMv8.1 PAN extension 2015-06-02 12:30:38 +01:00
Matthew Wahab
1af1dd51db [ARM] Rework CPU feature selection in the disassembler
include/opcode/
	* arm.h (ARM_FEATURE_ALL): New.

opcodes/
	* arm-dis.c (select_arm_features): Rework to avoid used of
	redefined macros.
2015-06-02 12:24:24 +01:00
Matthew Wahab
9e1f0fa7f3 [AArch64] Support for ARMv8.1a Adv.SIMD instructions
2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>

gas/
  * config/tc-aarch64.c (aarch64_features): Add "rdma".
  * doc/c-aarch64.texi (AArch64 Extensions): Add "rdma".

gas/testsuite/
  * rdma-directive.d: New.
  * rdma.d: New.
  * rdma.s: New.

include/opcode/
  * aarch64.h (AARCH64_FEATURE_RDMA): New.

opcode/
  * aarch64-tbl.h (aarch64_feature_rdma): New.
  (RDMA): New.
  (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
  * aarch64-asm-2.c: Regenerate.
  * aarch64-dis-2.c: Regenerate.
  * aarch64-opc-2.c: Regenerate.
2015-06-02 12:20:00 +01:00
Matthew Wahab
290806fd94 [AArch64] Support for ARMv8.1a Limited Ordering Regions extension
2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
include/
  * aarch64.h (AARCH64_FEATURE_LOR): New.

opcodes/
  * aarch64-tbl.h (aarch64_feature_lor): New.
  (LOR): New.
  (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
  "stllrb", "stllrh".
  * aarch64-asm-2.c: Regenerate.
  * aarch64-dis-2.c: Regenerate.
  * aarch64-opc-2.c: Regenerate.

gas/
  * config/tc-aarch64.c (aarch64_features): Add "lor".
  * doc/c-aarch64.c (Aarch64 Extensions): Add "lor" to list of
  architecture extensions.

gas/testsuite/
  * lor-directive.d: New.
  * lor.d: New.
  * lor.s: New.
2015-06-02 11:30:12 +01:00
Matthew Wahab
f21cce2cac [AArch64][libopcode] Add support for PAN architecture extension
The ARMv8.1 architecture introduced the Privileged Access Never extension. This
adds a processor state field PSTATE.PAN which can be accessed using the MRS/MSR
instructions.

This patch adds support for the PAN architecture feature and processor state
field to libopcode.

include/opcode
2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (AARCH64_FEATURE_PAN): New.
	(aarch64_sys_reg_supported_p): Declare.
	(aarch64_pstatefield_supported_p): Declare.

opcodes/
2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
	* aarch64-opc.c (F_ARCHEXT): New.
	(aarch64_sys_regs): Add "pan".
	(aarch64_sys_reg_supported_p): New.
	(aarch64_pstatefields): Add "pan".
	(aarch64_pstatefield_supported_p): New.
2015-06-01 16:00:28 +01:00
Roland McGrath
14ae95f220 Recognize GNU_ABI_TAG_SYLLABLE and GNU_ABI_TAG_NACL.
binutils/
	* readelf.c (print_gnu_note: NT_GNU_ABI_TAG): Recognize
	GNU_ABI_TAG_SYLLABLE and GNU_ABI_TAG_NACL.

include/elf/
	* common.h (GNU_ABI_TAG_SYLLABLE): New macro.
	(GNU_ABI_TAG_NACL): New macro.
2015-05-29 09:13:53 -07:00
Catherine Moore
2f0c68f23b Compact EH Support
The specification for the Compact EH format is available at:
https://github.com/MentorEmbedded/cxx-abi/blob/master/MIPSCompactEH.pdf

2015-05-28  Catherine Moore  <clm@codesourcery.com>
	    Bernd Schmidt <bernds@codesourcery.com>
	    Paul Brook <paul@codesourcery.com>

	bfd/
	* bfd-in2.h: Regenerated.
	* elf-bfd.h (DWARF2_EH_HDR, COMPACT_EH_HDR): Define.
	(COMPACT_EH_CANT_UNWIND_OPCODE): Define.
	(dwarf_eh_frame_hdr_info): Move dwarf-specific fields from
	eh_frame_hdr_info.
	(compact_eh_frame_hdr_info): Declare.
	(eh_frame_hdr_info):  Redeclare with union for dwarf-specific
	fields and compact-eh fields.
	(elf_backend_data): Add cant_unwind_opcode and compact_eh_encoding.
	(bfd_elf_section_data): Add eh_frame_entry_field.
	(elf_section_eh_frame_entry): Define.
	(bfd_elf_parse_eh_frame_entries): Declare.
	(_bfd_elf_parse_eh_frame_entry): Declare.
	(_bfd_elf_end_eh_frame_parsing): Declare.
	(_bfd_elf_write_section_eh_frame_entry): Declare.
	(_bfd_elf_eh_frame_entry_present): Declare.
	(_bfd_elf_section_for_symbol): Declare.
	* elf-eh-frame.c (bfd_elf_discard_eh_frame_entry): New function.
	(bfd_elf_record_eh_frame_entry): New function.
	(_bfd_elf_parse_eh_frame_entry): New function.
	(_bfd_elf_parse_eh_frame): Update hdr_info field references.
	(cmp_eh_frame_hdr): New function.
	(add_eh_frame_hdr_terminator): New function.
	(_bfd_elf_end_eh_frame_parsing): New function.
	(find_merged_cie): Update hdr_info field references.
	(_bfd_elf_discard_section_eh_frame): Likewise.
	(_bfd_elf_discard_section_eh_frame_hdr): Add Compact EH support.
	(_bfd_elf_eh_frame_entry_present): New function.
	(_bfd_elf_maybe_strip_eh_frame_hdr): Add Compact EH support.
	(_bfd_elf_write_section_eh_frame_entry): New function.
	(_bfd_elf_write_section_eh_frame): Update hdr_info field references.
	(_bfd_elf_fixup_eh_frame_hdr): New function.
	(write_compact_eh_frame_hdr): New function.
	(write_dwarf_eh_frame_hdr): New function.
	(_bfd_elf_write_section_eh_frame_hdr): Add Compact EH support.
	* elflink.c (_bfd_elf_section_for_symbol): New function.
	(elf_section_ignore_discarded_relocs): Add Compact EH support.
	(elf_link_input_bfd): Likewise.
	(bfd_elf_final_link): Likewise.
	(_bfd_elf_gc_mark): Likewise.
	(bfd_elf_parse_eh_frame_entries): New function.
	(bfd_elf_gc_sections): Add Compact EH support.
	(bfd_elf_discard_info): Likewise.
	* elfxx-mips.c: Include dwarf2.h.
	(_bfd_mips_elf_compact_eh_encoding): New function.
	(_bfd_mips_elf_cant_unwind_opcode): New function.
	* elfxx-mips.h (_bfd_mips_elf_compact_eh_encoding): Declare.
	(_bfd_mips_elf_cant_unwind_opcode): Declare.
	(elf_backend_compact_eh_encoding): Define.
	(elf_backend_cant_unwind_opcode): Define.
	* elfxx-target.h (elf_backend_compact_eh_encoding): Provide default.
	(elf_backend_cant_unwind_opcode): Provide default.
	(elf_backend_data elfNN_bed): Add elf_backend_compact_eh_encoding and
	elf_backend_cant_unwind_opcode.
	* section.c (SEC_INFO_TYPE_EH_FRAME_ENTRY): Add definition.

	gas/
	* config/tc-alpha.c (all_cfi_sections): Declare.
	(s_alpha_ent): Initialize all_cfi_sections.
	(alpha_elf_md_end): Invoke cfi_set_sections.
	* config/tc-mips.c (md_apply_fix):  Handle BFD_RELOC_NONE.
	(s_ehword): Use BFD_RELOC_32_PCREL.
	(mips_fix_adjustable): Handle BFD_RELOC_32_PCREL.
	(mips_cfi_reloc_for_encoding): New function.
	* tc-mips.h (DWARF2_FDE_RELOC_SIZE): Redefine.
	(DWARF2_FDE_RELOC_ENCODING): Define.
	(tc_cfi_reloc_for_encoding): Define.
	(mips_cfi_reloc_for_encoding): Define.
	(tc_compact_eh_opcode_stop): Define.
	(tc_compact_eh_opcode_pad): Define.
	* doc/as.texinfo: Document Compact EH extensions.
	* doc/internals.texi: Likewise.
	* dw2gencfi.c (EH_FRAME_LINKONCE): Redefine.
	(tc_cfi_reloc_for_encoding): Provide default.
	(compact_eh): Declare.
	(emit_expr_encoded): New function.
	(get_debugseg_name): Add Compact EH support.
	(alloc_debugseg_item): Likewise.
	(cfi_set_sections): New function.
	(dot_cfi_fde_data): New function.
	(dot_cfi_personality_id): New function.
	(dot_cfi_inline_lsda): New function.
	(cfi_pseudo_table): Add cfi_fde_data, cfi_personality_id,
	and cfi_inline_lsda.
	(dot_cfi_personality): Add Compact EH support.
	(dot_cfi_lsda): Likewise.
	(dot_cfi_sections): Likewise.
	(dot_cfi_startproc): Likewise.
	(get_cfi_seg): Likewise.
	(output_compact_unwind_data): New function.
	(output_cfi_insn): Add Compact EH support.
	(output_cie): Likewise.
	(output_fde): Likewise.
	(cfi_finish): Likewise.
	(cfi_emit_eh_header): New function.
	(output_eh_header): New function.
	* dw2gencfi.h (cfi_set_sections): Declare.
	(SUPPORT_COMPACT_EH): Define.
	(MULTIPLE_FRAME_SECTIONS): Define.
	New enumeration to describe the Compact EH header format.
	(fde_entry): Add new fields personality_id, eh_header_type, eh_data_size,
	eh_data, eh_loc and sections.
	(CFI_EMIT_eh_frame, CFI_EMIT_debug_frame, CFI_EMIT_target,
	CFI_EMIT_eh_frame_compact): Define.

2015-05-22  Catherine Moore  <clm@codesourcery.com>
	    Bernd Schmidt <bernds@codesourcery.com>

	gas/testsuite/
	* gas/mips/mips.exp: Run new tests.

	* gas/mips/compact-eh-1.s: New file.
	* gas/mips/compact-eh-2.s: New file.
	* gas/mips/compact-eh-3.s: New file.
	* gas/mips/compact-eh-4.s: New file.
	* gas/mips/compact-eh-5.s: New file.
	* gas/mips/compact-eh-6.s: New file.
	* gas/mips/compact-eh-7.s: New file.
	* gas/mips/compact-eh-eb-1.d: New file.
	* gas/mips/compact-eh-eb-2.d: New file.
	* gas/mips/compact-eh-eb-3.d: New file.
	* gas/mips/compact-eh-eb-4.d: New file.
	* gas/mips/compact-eh-eb-5.d: New file.
	* gas/mips/compact-eh-eb-6.d: New file.
	* gas/mips/compact-eh-eb-7.d: New file.
	* gas/mips/compact-eh-el-1.d: New file.
	* gas/mips/compact-eh-el-2.d: New file.
	* gas/mips/compact-eh-el-3.d: New file.
	* gas/mips/compact-eh-el-4.d: New file.
	* gas/mips/compact-eh-el-5.d: New file.
	* gas/mips/compact-eh-el-6.d: New file.
	* gas/mips/compact-eh-el-7.d: New file.
	* gas/mips/compact-eh-err1.l: New file.
	* gas/mips/compact-eh-err1.s: New file.
	* gas/mips/compact-eh-err2.l: New file.
	* gas/mips/compact-eh-err2.s: New file.

2015-05-22  Catherine Moore  <clm@codesourcery.com>

	include/
	* bfdlink.h: Rename eh_frame_hdr to eh_frame_hdr_type.

2015-05-22  Catherine Moore  <clm@codesourcery.com>
	    Paul Brook <paul@codesourcery.com>

	ld/
	* emultempl/elf32.em (gld${EMULATION_NAME}_after_open):
	Add Compact EH support.
	* scripttempl/elf.sc: Handle .eh_frame_entry and .gnu_extab
	sections.

2015-05-22  Catherine Moore  <clm@codesourcery.com>

	ld/testsuite/
	* ld-mips-elf/compact-eh.ld: New linker script.
	* ld-mips-elf/compact-eh1.d: New.
	* ld-mips-elf/compact-eh1.s: New.
	* ld-mips-elf/compact-eh1a.s: New.
	* ld-mips-elf/compact-eh1b.s: New.
	* ld-mips-elf/compact-eh2.d: New.
	* ld-mips-elf/compact-eh2.s: New.
	* ld-mips-elf/compact-eh3.d: New.
	* ld-mips-elf/compact-eh3.s: New.
	* ld-mips-elf/compact-eh3a.s: New.
	* ld-mips-elf/compact-eh4.d: New.
	* ld-mips-elf/compact-eh5.d: New.
	* ld-mips-elf/compact-eh6.d: New.
	* ld-mips-elf/mips-elf.exp: Run new tests.
2015-05-28 15:21:17 -07:00
Jiong Wang
15eddee17f [AArch64] Add R_AARCH64_P32_LD32_GOTPAGE_LO14 to elf header
2015-05-12  Jiong. Wang  <jiong.wang@arm.com>

include/
  * elf/aarch64.h (R_AARCH64_P32_LD32_GOTPAGE_LO14): New enumeration.
2015-05-12 13:47:15 +01:00
H.J. Lu
22abe5566a Rename EM_486 to EM_IAMCU
bfd/

	* elfcode.h (elf_object_p): Replace EM_486 with EM_IAMCU.

binutils/

	* dwarf.c (init_dwarf_regnames): Replace EM_486 with EM_IAMCU.
	* readelf.c (guess_is_rela): Likewise.
	(dump_relocations): Likewise.
	(get_machine_name): Likewise.
	(get_elf_section_flags): Likewise.
	(process_section_headers): Likewise.
	(is_32bit_abs_reloc): Likewise.
	(is_32bit_pcrel_reloc): Likewise.

include/elf/

	* common.h (EM_486): Renamed to ...
	(EM_IAMCU): This.
2015-05-11 08:53:05 -07:00
H.J. Lu
f7d1355102 Sync filenames.h with gcc
Merge with gcc:
	2014-11-11  Anthony Brandon  <anthony.brandon@gmail.com>
		    Manuel López-Ibáñez  <manu@gcc.gnu.org>

	PR driver/36312
	* filenames.h: Add prototype for canonical_filename_eq.
2015-05-01 09:11:15 -07:00
DJ Delorie
0952813b0b Make RL78 disassembler and simulator respect ISA for mul/div
[gas]
	* config/rl78-defs.h (rl78_isa_g10): New.
	(rl78_isa_g13): New.
	(rl78_isa_g14): New.
	* config/rl78-parse.y (ISA_G10): New.
	(ISA_G13): New.
	(ISA_G14): New.
	(MULHU, MULH, MULU, DIVHU, DIVWU, MACHU, MACH): Use them.
	* config/tc-rl78.c (rl78_isa_g10): New.
	(rl78_isa_g13): New.
	(rl78_isa_g14): New.

[gdb]
	* rl78-tdep.c (rl78_analyze_prologue): Pass RL78_ISA_DEFAULT to
	rl78_decode_opcode

[include]
	* dis-asm.h (print_insn_rl78_g10): New.
	(print_insn_rl78_g13): New.
	(print_insn_rl78_g14): New.
	(rl78_get_disassembler): New.
	* opcode/rl78.h (RL78_Dis_Isa): New.
	(rl78_decode_opcode): Add ISA parameter.

[opcodes]
	* disassemble.c (disassembler): Choose suitable disassembler based
	on E_ABI.
	* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
	it to decode mul/div insns.
	* rl78-decode.c: Regenerate.
	* rl78-dis.c (print_insn_rl78): Rename to...
	(print_insn_rl78_common): ...this, take ISA parameter.
	(print_insn_rl78): New.
	(print_insn_rl78_g10): New.
	(print_insn_rl78_g13): New.
	(print_insn_rl78_g14): New.
	(rl78_get_disassembler): New.

[sim]
	* rl78/cpu.c (g14_multiply): New.
	* rl78/cpu.h (g14_multiply): New.
	* rl78/load.c (rl78_load): Decode ISA completely.
	* rl78/main.c (main): Expand -M to include other ISAs.
	* rl78/rl78.c (decode_opcode): Decode based on ISA.
	* rl78/trace.c (rl78_disasm_fn): New.
	(sim_disasm_init): Reset it.
	(sim_disasm_one): Get correct disassembler for ISA.
2015-04-30 15:25:49 -04:00
Andreas Krebbel
643f7afb0d S/390: z13 use GNU attribute to indicate vector ABI
bfd/
	* elf-s390-common.c (elf_s390_merge_obj_attributes): New function.
	* elf32-s390.c (elf32_s390_merge_private_bfd_data): Call
	elf_s390_merge_obj_attributes.
	* elf64-s390.c (elf64_s390_merge_private_bfd_data): New function.

binutils/
	* readelf.c (display_s390_gnu_attribute): New function.
	(process_s390_specific): New function.
	(process_arch_specific): Call process_s390_specific.

gas/
	* doc/as.texinfo: Document Tag_GNU_S390_ABI_Vector.

include/elf/
	* s390.h: Define Tag_GNU_S390_ABI_Vector.
2015-04-27 10:32:23 +02:00
Alan Modra
44bd1acd55 Non-alloc sections don't belong in PT_LOAD segments
Taking them out showed a bug in the powerpc64 backend with .branch_lt
being removed from output_bfd but not from previously set up segment
section maps.  Removing the bfd sections meant their sh_flags (and
practically everything else) remaining zero, ie. not SHF_ALLOC,
triggering complaints about "`.branch_lt' can't be allocated in
segment".

include/elf/
	* internal.h (ELF_SECTION_IN_SEGMENT_1): Ensure PT_LOAD and
	similar segments only contain alloc sections.
ld/
	* emultempl/ppc64elf.em (gld${EMULATION_NAME}_after_allocation):
	Call gld${EMULATION_NAME}_map_segments regardless of need_laying_out.
ld/testsuite/
	* ld-powerpc/tocnovar.d: Revert last change.
2015-04-25 09:15:49 +09:30
H.J. Lu
9361e6307b Define SEC_MEP_VLIW in bfd/section.c
Bits in section flags should only be defined in bfd/section.c.  This
patch moves SEC_MEP_VLIW to bfd/section.c.

bfd/

	PR binutils/18316
	* section.c (SEC_MEP_VLIW): New.
	* bfd-in2.h: Regenerated.

include/elf/

	PR binutils/18316
	* mep.h (SEC_MEP_VLIW): Removed.
2015-04-24 05:40:23 -07:00
Richard Earnshaw
a4ea36c6cb Merge include/partition.h from GCC.
2015-03-19  Richard Biener  <rguenther@suse.de>

		* partition.h (struct partition_elem): Re-order elements to
		avoid padding.
2015-04-17 16:13:43 +01:00
H.J. Lu
0ce398f106 Add --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]
This patch adds --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi]
to ld for ELF targets to support generating compressed DWARF debug
sections.  We always generate .zdebug_* section since section names have
been finalized and they can't be changed easily when compression is
being performed.

bfd/

	* bfd-in.h (compressed_debug_section_type): New.
	* compress.c (bfd_compress_section_contents): Add an argument
	for linker write compression and always generate .zdebug_*
	section when linking.
	(bfd_init_section_compress_status): Pass FALSE to
	bfd_compress_section_contents.
	(bfd_compress_section): New function.
	* elf.c (elf_fake_sections): For linking, set SEC_ELF_COMPRESS
	on DWARF debug sections if COMPRESS_DEBUG is set and rename
	section if COMPRESS_DEBUG_GABI_ZLIB isn't set.
	(assign_file_positions_for_non_load_sections): Set sh_offset
	to -1 if SEC_ELF_COMPRESS is set.
	(assign_file_positions_except_relocs): Likwise.
	(_bfd_elf_assign_file_positions_for_relocs): Renamed to ...
	(_bfd_elf_assign_file_positions_for_non_load): This.  Change
	return time to bfd_boolean.  Compress the section if
	SEC_ELF_COMPRESS is set.
	(_bfd_elf_write_object_contents): Updated.
	(_bfd_elf_set_section_contents): Write section contents to
	the buffer if SEC_ELF_COMPRESS is set.
	* merge.c: Include "elf-bfd.h".
	(sec_merge_emit): Add arguments for contents and offset.  Write
	to contents with offset if contents isn't NULL.
	(_bfd_write_merged_section): Write section contents to the
	buffer if SEC_ELF_COMPRESS is set.  Pass contents and
	output_offset to sec_merge_emit.
	* elflink.c (bfd_elf_final_link): Allocate the buffer for
	output section contents if SEC_ELF_COMPRESS is set.
	* section.c (SEC_ELF_COMPRESS): New.
	* bfd-in2.h: Regenerated.

gas/

	* as.h (compressed_debug_section_type): Removed.

include/

	* bfdlink.h (bfd_link_info): Add compress_debug.

ld/

	* ld.texinfo: Document --compress-debug-sections=.
	* ldmain.c (main): Set BFD_COMPRESS on output_bfd if
	COMPRESS_DEBUG is set.  Set BFD_COMPRESS_GABI on output_bfd
	for COMPRESS_DEBUG_GABI_ZLIB.
	* lexsup.c (elf_static_list_options): Add
	--compress-debug-sections=.
	* emultempl/elf32.em (OPTION_COMPRESS_DEBUG): New.
	(xtra_long): Add "compress-debug-sections".
	(gld${EMULATION_NAME}_handle_option): Handle
	OPTION_COMPRESS_DEBUG.

ld/testsuite/

	* ld-elf/compress.exp (build_tests): Add tests for
	--compress-debug-sections=.
	(run_tests): Likewise.
	Add additonal tests for --compress-debug-sections=.
	* ld-elf/gabiend.rt: New file.
	* ld-elf/gabinormal.rt: Likewise.
	* ld-elf/gnubegin.rS: Likewise.
	* ld-elf/gnunormal.rS: Likewise.
	* ld-elf/zlibbegin.rS: Likewise.
	* ld-elf/zlibnormal.rS: Likewise.
2015-04-14 22:01:38 -07:00
H.J. Lu
889c2a6796 Add -z noextern-protected-data to ld for ELF/x86
Address of protected data defined in the shared library may be external,
i.e., due to copy relocation.  By default, linker backend checks if
relocations against protected data symbols are valid for building shared
library and issues an error if relocation isn't allowed.  The new option
override linker backend default.  When -z noextern-protected-data is used,
updates on protected data symbols by another module won't be visibile
to the resulting shared library.  This option is specific to ELF/i386
and ELF/x86-64.

bfd/

	PR ld/pr17709
	* elflink.c (_bfd_elf_adjust_dynamic_copy): Check
	info->extern_protected_data when warning copy relocs against
	protected symbols.
	(_bfd_elf_symbol_refs_local_p): Check info->extern_protected_data
	when checking protected non-function symbols.

include/

	PR ld/pr17709
	* bfdlink.h (bfd_link_info): Add extern_protected_data.

ld/

	PR ld/pr17709
	* ld.texinfo: Document "-z noextern-protected-data".
	* ldmain.c (main): Initialize link_info.extern_protected_data
	to -1.
	* lexsup.c (elf_shlib_list_options): Add
	"-z [no]extern-protected-data".
	* emulparams/elf32_x86_64.sh: Source extern_protected_data.sh.
	* emulparams/elf_i386.sh: Likewise.
	* emulparams/elf_i386_be.sh: Likewise.
	* emulparams/elf_i386_chaos.sh: Likewise.
	* emulparams/elf_i386_ldso.sh: Likewise.
	* emulparams/elf_i386_vxworks.sh: Likewise.
	* emulparams/elf_k1om.sh: Likewise.
	* emulparams/elf_l1om.sh: Likewise.
	* emulparams/elf_x86_64.sh: Source extern_protected_data.sh.
	(PARSE_AND_LIST_OPTIONS): Renamed to ...
	(PARSE_AND_LIST_OPTIONS_BNDPLT): This.
	(PARSE_AND_LIST_ARGS_CASE_Z): Renamed to ...
	(PARSE_AND_LIST_ARGS_CASE_Z_BNDPLT): This.
	(PARSE_AND_LIST_OPTIONS): Append $PARSE_AND_LIST_OPTIONS_BNDPLT.
	(PARSE_AND_LIST_ARGS_CASE_Z): Append
	$PARSE_AND_LIST_ARGS_CASE_Z_BNDPLT.
	* emulparams/extern_protected_data.sh: New file.

ld/testsuite/

	PR ld/pr17709
	* ld-i386/i386.exp: Run protected6b.
	* ld-i386/protected6b.d: New file.
	* ld-x86-64/protected6b.d: Likewise.
	* ld-x86-64/x86-64.exp:  Run protected6b.
2015-04-14 04:13:11 -07:00
Nick Clifton
3525236c57 Add support to the RX toolchain to restrict the use of string instructions.
bfd	* elf32-rx.c (describe_flags): Report the settings of the string
	insn using bits.
	(rx_elf_merge_private_bfd_data): Handle merging of the string insn
	using bits.

bin	* readelf.c (get_machine_flags): Report the setting of the string
	insn using bits.

gas	* config/tc-rx.c (enum options): Add OPTION_DISALLOW_STRING_INSNS.
	(md_longopts): Add -mno-allow-string-insns.
	(md_parse_option): Handle -mno-allow-string-insns.
	(md_show_usage): Mention -mno-allow-string-insns.
	(rx_note_string_insn_use): New function.  Produces an error
	message if a string insn is used when it is not allowed.
	* config/rx-parse.y (SCMPU): Call rx_note_string_insn_use.
	(SMOVU, SMOVB, SMOVF, SUNTIL, SWHILE, RMPA): Likewise.
	* config/rx-defs.h (rx_note_string_insn_use): Prototype.
	* doc/c-rx.texi: Document -mno-allow-string-insns.

elf	* rx.h (E_FLAG_RX_SINSNS_SET): New bit in e_flags field.
	(E_FLAG_RX_SINSNS_YES): Likewise.
	(E_FLAG_RX_SINSNS_MASK): New define.
2015-04-09 12:48:37 +01:00
H.J. Lu
6aa7612029 Add Elf_Internal_Chdr and ElfXX_External_Chdr
* external.h (Elf32_External_Chdr): New.
	(Elf64_External_Chdr): Likewise.
	* internal.h (Elf_Internal_Chdr): Likewise.
2015-04-03 12:50:10 -07:00
James Bowman
f46e4eb78b sim: ft32: new port
FT32 is a new high performance 32-bit RISC core developed by FTDI for
embedded applications.
2015-03-28 02:12:33 -04:00
H.J. Lu
332f5759ac Add ELFOSABI_CLOUDABI and SHF_COMPRESSED
Update from gABI DRAFT - 10 June 2013.

	* common.h (ELFOSABI_CLOUDABI): New.
	(SHF_COMPRESSED): Likewise.
	(ELFCOMPRESS_ZLIB): Likewise.
	(ELFCOMPRESS_LOOS): Likewise.
	(ELFCOMPRESS_HIOS): Likewise.
	(ELFCOMPRESS_LOPROC): Likewise.
	(ELFCOMPRESS_HIPROC): Likewise.
2015-03-26 08:42:58 -07:00
Terry Guo
823d25713d Extend arm_feature_set struct to provide more bits
gas/ChangeLog:
2015-03-24  Terry Guo  <terry.guo@arm.com>

	* config/tc-arm.c (no_cpu_selected): Use new macro to compare
	features.
	(parse_psr): Likewise.
	(do_t_mrs): Likewise.
	(do_t_msr): Likewise.
	(static const arm_feature_set arm_ext_*): Defined with new
	macros.
	(static const arm_feature_set arm_cext_*): Likewise.
	(static const arm_feature_set fpu_fpa_ext_*): Likewise.
	(static const arm_feature_set fpu_vfp_ext_*): Likewise.
	(deprecated_coproc_regs): Likewise.
	(UL_BARRIER): Likewise.
	(barrier_opt_names): Likewise.
	(arm_cpus): Likewise.
	(arm_extensions): Likewise.

include/opcode/ChangeLog:
2015-03-24  Terry Guo  <terry.guo@arm.com>

	* arm.h (arm_feature_set): Extended to provide more available
	* bits.
	(ARM_ANY): Updated to follow above new definition.
	(ARM_CPU_HAS_FEATURE): Likewise.
	(ARM_CPU_IS_ANY): Likewise.
	(ARM_MERGE_FEATURE_SETS): Likewise.
	(ARM_CLEAR_FEATURE): Likewise.
	(ARM_FEATURE): Likewise.
	(ARM_FEATURE_COPY): New macro.
	(ARM_FEATURE_EQUAL): Likewise.
	(ARM_FEATURE_ZERO): Likewise.
	(ARM_FEATURE_CORE_EQUAL): Likewise.
	(ARM_FEATURE_LOW): Likewise.
	(ARM_FEATURE_CORE_LOW): Likewise.
	(ARM_FEATURE_CORE_COPROC): Likewise.

opcodes/ChangeLog:
2015-03-24  Terry Guo  <terry.guo@arm.com>

	* arm-dis.c (opcode32): Updated to use new arm feature struct.
	(opcode16): Likewise.
	(coprocessor_opcodes): Replace bit with feature struct.
	(neon_opcodes): Likewise.
	(arm_opcodes): Likewise.
	(thumb_opcodes): Likewise.
	(thumb32_opcodes): Likewise.
	(print_insn_coprocessor): Likewise.
	(print_insn_arm): Likewise.
	(select_arm_features): Follow new feature struct.
2015-03-24 14:08:08 +08:00
Nick Clifton
1740ba0cec Add support for G13 and G14 flag bits in RL78 ELF binaries.
inc	* rl78.h (E_FLAG_RL78_G10): Redefine.
	(E_FLAG_RL78_CPU_MASK, E_FLAG_RL78_ANY_CPU, E_FLAG_RL78_G13
	E_FLAG_RL78_G14): New flags.

bin	* readelf.c (get_machine_flags): Decode RL78's G13 and G14 flags.

gas	* config/tc-rl78.c (enum options): Add G13 and G14.
	(md_longopts): Add -mg13 and -mg14.
	(md_parse_option): Handle -mg13 and -mg14.
	(md_show_usage): List -mg13 and -mg14.
	* doc/c-rl78.texi: Add description of -mg13 and -mg14 options.

bfd	* elf32-rl78.c (rl78_cpu_name): New function.  Prints the name of
	the RL78 core based upon the flags.
	(rl78_elf_merge_private_bfd_data): Handle merging of G13 and G14
	flags.
	(rl78_elf_print_private_bfd_data): Use rl78_cpu_name.
	(elf32_rl78_machine): Always return bfd_mach_rl78.
2015-03-19 15:37:43 +00:00
Mike Frysinger
8406bb5944 sim: dv-sockser: push module init prototype down
Pull out the duplicated dv_sockser_install prototype from the tconfig.in
files and put it in the one place it gets used -- sim-module.c.  This is
still arguably incorrect, but it's better than the status quo where the
tconfig.in has to include header files and duplicate the dv-sockser func.
The tconfig header is meant to be simple and contain a target defines.
2015-03-15 03:05:05 -04:00
Jiong Wang
a5721eddd1 [ARM] PR ld/16572: Remove EF_ARM_HASENTRY flag
bfd/
2015-03-10  Yuri Gribov  <y.gribov@samsung.arm>

	PR ld/16572
	* elf32-arm.c (elf32_arm_final_link_relocate): Remove
	support for ELF_ARM_HASENTRY.
	(elf32_arm_print_private_bfd_data): Likewise.

binutils/
2015-03-10  Yuri Gribov  <y.gribov@samsung.arm>

	PR ld/16572
	* readelf.c: Remove support for ELF_ARM_HASENTRY.

include/
2015-03-10  Matthew Wahab  <matthew.wahab@arm.com>

	PR ld/16572
	* elf/arm.h (EF_ARM_HASENTRY): Remove.
2015-03-10 11:15:13 +00:00
Marcus Shawcroft
3c12b05436 Add ADR :tlsgd: directive and TLSGD_ADR_PREL21 support. 2015-02-26 22:23:09 +00:00
Nick Clifton
685080f210 Adds support for generating notes in V850 binaries.
bfd	* elf32-v850.c (v850_set_note): New function.  Creates a Renesas
	style note entry.
	(v850_elf_make_note_section): New function.  Creates a note
	section.
	(v850_elf_create_sections): New function.  Create a note section
	if one is not already present.
	(v850_elf_set_note): New function.  Adds a note to a bfd.
	(v850_elf_copy_private_bfd_data): New function.  Copies V850
	notes.
	(v850_elf_merge_notes): New function.  Merges V850 notes.
	(print_v850_note): New function.  Displays a V850 note.
	(v850_elf_print_notes): New function. Displays all notes attached
	to a bfd.
	(v850_elf_merge_private_bfd_data): Call v850_elf_merge_notes.
	(v850_elf_print_private_bfd_data): Call v850_elf_print_notes.
	(v850_elf_fake_sections): Set the type of the V850 note section.
	* bfd-in.h (v850_elf_create_sections): Add prototype.
	(v850_elf_set_note): Add prototype.
	* bfd-in2.h: Regenerate.

binutils* readelf.c (get_machine_flags): Remove deprecated V850 machine
	flags.
	(get_v850_section_type_name): New function.  Handles V850 special
	sections.
	(get_section_type_name): Add support for V850.
	(get_v850_elf_note_type): New function.  Returns the name of a
	V850 note.
	(print_v850_note): New function.  Prints a V850 note.
	(process_v850_notes): New function.  Prints V850 notes.
	(process_note_sections): Add support for V850.

binutils/testsute
	* binutils-all/objcopy.exp: Skip the strip-10 test for the V850.

gas	* config/tc-v850.c (soft_float): New variable.
	(v850_data_8): New variable.
	(md_show_usage): Add -msoft-float/-mhard-float.
	(md_parse_option): Likewise.
	(md_begin): Set the default value of soft_float.
	(v850_md_end): New function.  Creates a note section.
	* config/tc-v850.h (md_end): Define.
	* doc/c-v850.texi: Document -msoft-float/-mhard-float.

gas/testsuite
	* gas/elf/elf.exp: Add special version of the section2 test for
	the V850.
	* gas/elf/section2.e-v850: New file.

include/elf
	* v850.h (EF_RH850_SIMD): Delete deprecated flag.
	(EF_RH850_CACHE): Likewise.
	(EF_RH850_MMU): Likewise.
	(EF_RH850_DATA_ALIGN8): Likewise.
	(SHT_RENESAS_IOP): Fix typo in name.
	(SHT_RENESAS_INFO): Define.
	(V850_NOTE_SECNAME): Define.
	(SIZEOF_V850_NOTE): Define.
	(V850_NOTE_NAME): Define.
	(enum v850_notes): New enum.
	(NUM_V850_NOTES): Define.

ld/ChangeLog
2015-02-24  Nick Clifton  <nickc@redhat.com>

	* Makefile.am (ev850.c): Add dependency upon
	$(srcdir)/emultempl/v850elf.em.
	(ev850_rh850.c): Likewise.
	* Makefile.in: Regenerate.
	* emultempl/v850elf.em: New file.
	* emulparams/v850.sh (EXTRA_EM_FILE): Define.
	* emulparams/v850_rh850.sh (EXTRA_EM_FILE): Define.
	* scripttempl/v850.sc: Add .note.renesas section.
	* scripttempl/v850_rh850.sc: Likewise.

ld/testsuite
	* ld-elf/extract-symbol-1sec.d: Expect to fail on the V850.
2015-02-24 17:54:09 +00:00
Nick Clifton
8f3102ea1a Fixes a typo in the license notice in include/elf/score.h
PR 17915
	* score.h: Fix typo in license header.
2015-02-23 14:52:12 +00:00
Andreas Arnez
4ef9f41a95 S390: Support new vector register sections
The IBM z13 has new 128-bit wide vector registers v0-v31, where v0-v15
include the existing 64-bit wide floating point registers.  The Linux
kernel presents the vector registers as two additional register sets,
one for the right halves of v0-v15 and another one for the full
registers v16-v31.  Thus a new core file may contain two new register
note sections, and this patch adds support to binutils for them.

bfd/
	* elf-bfd.h (elfcore_write_s390_vxrs_low): Add prototype.
	(elfcore_write_s390_vxrs_high): Likewise.
	* elf.c (elfcore_grok_s390_vxrs_low): New function.
	(elfcore_grok_s390_vxrs_high): New function.
	(elfcore_grok_note): Call them.
	(elfcore_write_s390_vxrs_low): New function.
	(elfcore_write_s390_vxrs_high): New function.
	(elfcore_write_register_note): Call them.

binutils/
	* readelf.c (get_note_type): Add NT_S390_VXRS_LOW and
	NT_S390_VXRS_HIGH.

include/elf/
	* common.h (NT_S390_VXRS_LOW): New macro.
	(NT_S390_VXRS_HIGH): Likewise.
2015-02-20 10:39:53 +01:00
Pedro Alves
f63c17760f Wrap a few opcodes headers in extern "C" for C++
These are sufficient to link an --enable-targets=all GDB build in C++
mode, on x86_64 Fedora 20.

include/opcode/
2015-02-19  Pedro Alves  <palves@redhat.com>

	* cgen.h [__cplusplus]: Wrap in extern "C".
	* msp430-decode.h [__cplusplus]: Likewise.
	* nios2.h [__cplusplus]: Likewise.
	* rl78.h [__cplusplus]: Likewise.
	* rx.h [__cplusplus]: Likewise.
	* tilegx.h [__cplusplus]: Likewise.

opcodes/
2015-02-19  Pedro Alves  <palves@redhat.com>

	* microblaze-dis.h [__cplusplus]: Wrap in extern "C".
2015-02-19 22:45:47 +00:00
Pedro Alves
07df97c857 floatformat.h: Wrap in extern "C"
Just like libiberty.h.  So that C++ programs, such as GDB when built
as a C++ program, can use it.

include/ChangeLog:
2015-02-19  Pedro Alves  <palves@redhat.com>

	* floatformat.h [__cplusplus]: Wrap in extern "C".
2015-02-19 22:44:44 +00:00
Alan Modra
ce875075f9 PR ld/17973 LTO file syms
LTO output objects have an STT_FILE symbol using the name of the file,
a temporary file.  This results in executables that can't be exactly
reproduced, so the file name needs to be dropped.  We don't want to
lose all file symbols when linking a mix of lto and non-lto objects as
a file symbol can be used to figure which source file generated a
given local symbol.  So lto output objects need to be marked.

I chose to mark lto output objects with a new bfd flag.  This flag is
also used to fix a bug in the link-once handling;  An object being
loaded after "loading_lto_outputs" is set might be one extracted from
an archive to satisfy new references from lto objects, not an lto
object itself.

The new flag is copied from archive to elements, and the same done
for no_export.  This fixes a bug in that --exclude-libs doesn't work
with thin archives.  I'm not completely happy with this part of the
patch and may revist this to avoid the hack in
_bfd_look_for_bfd_in_cache.

	PR ld/17973
include/
	* bfdlink.h (struct bfd_link_info): Delete loading_lto_outputs.
bfd/
	* bfd.c (struct bfd): Add lto_output.
	* linker.c (_bfd_handle_already_linked): Explicitly test for
	objects added by the lto plugin.
	* opncls.c (_bfd_new_bfd_contained_in): Copy lto_output and
	no_export flags from archive.
	* archive.c (open_nested_file): New function, setting lto_output
	and no_export, extracted from..
	(find_nested_archive): ..here.  Flip params.  Rename from
	_bfd_find_nested_archive.
	(_bfd_get_elt_at_filepos): Correct var typo.  Use open_nested_file.
	(_bfd_look_for_bfd_in_cache): Copy no_export.
	* elflink.c (elf_link_add_object_symbols): Remove now unnecessary
	my_archive->no_export test.
	(elf_link_input_bfd): Drop existing lto_output STT_FILE syms.
	Don't use the file name when adding lto_output STT_FILE sym.
	* bfd-in2.h: Regenerate.
ld/
	* ldlang.h (struct lang_input_statement_flags): Add lto_output.
	* ldlang.c (lang_process): Don't set loading_lto_outputs.
	* ldfile.c (ldfile_try_open_bfd): Transfer entry flags.lto_output
	to bfd.
	* plugin.c (add_input_file, add_input_library): Set flags.lto_output.
2015-02-14 23:41:54 +10:30
Mark Wielaard
5a19504458 Recognize new DWARF5/GCC5 DW_LANG constants for Fortran 03 and Fortran 08.
DWARFv5 defines and GCC5 may output two new DW_LANG constants for the
Fortran 2003 and Fortran 2008 standards. Handle and display both in
binutils.

binutils/ChangeLog:

	* dwarf.c (read_and_display_attr_value): Handle DW_LANG_Fortran03
	and DW_LANG_Fortran08.

include/ChangeLog:

	* dwarf2.h: Add DW_LANG_Fortran03 and DW_LANG_Fortran08.

http://dwarfstd.org/ShowIssue.php?issue=141121.1
2015-02-10 09:07:25 +01:00
Mark Wielaard
a2c2acaf15 GCC5/DWARFv5 Handle DW_TAG_atomic_type for C11 _Atomic type qualifier.
gdb/ChangeLog

	* c-typeprint.c (cp_type_print_method_args): Handle '_Atomic'.
	(c_type_print_modifier): Likewise.
	* dwarf2read.c (read_tag_atomic_type): New function.
	(read_type_die_1): Handle DW_TAG_atomic_type.
	* gdbtypes.c (make_atomic_type): New function.
	(recursive_dump_type): Handle TYPE_ATOMIC.
	* gdbtypes.h (enum type_flag_values): Renumber.
	(enum type_instance_flag_value): Add TYPE_INSTANCE_FLAG_ATOMIC.
	(TYPE_ATOMIC): New macro.
	(make_atomic_type): Declare.

gdb/testsuite/ChangeLog

	* gdb.dwarf2/atomic.c: New file.
	* gdb.dwarf2/atomic-type.exp: Likewise.

include/ChangeLog

	* dwarf2.def: Add DW_TAG_atomic_type.
2015-02-09 15:09:22 +01:00
Doug Evans
9f0500621b Add support for inlining scripts into .debug_gdb_scripts.
include/gdb/ChangeLog:

	* section-scripts.h: Remove "future extension" comment.
	(SECTION_SCRIPT_ID_PYTHON_TEXT): New macro.
	(SECTION_SCRIPT_ID_SCHEME_TEXT): New macro.

gdb/ChangeLog:

	* NEWS: Mention inlined scripts in .debug_gdb_scripts section.
	* auto-load.c: #include ctype.h.
	(struct auto_load_pspace_info): Replace member loaded_scripts with
	new members loaded_script_files, loaded_script_texts.
	(auto_load_pspace_data_cleanup): Update.
	(init_loaded_scripts_info): Update.
	(get_auto_load_pspace_data_for_loading): Update.
	(maybe_add_script_file): Renamed from maybe_add_script.  All callers
	updated.
	(maybe_add_script_text): New function.
	(clear_section_scripts): Update.
	(source_script_file, execute_script_contents): New functions.
	(source_section_scripts): Add support for
	SECTION_SCRIPT_ID_PYTHON_TEXT, SECTION_SCRIPT_ID_GUILE_TEXT.
	(print_scripts): New function.
	(auto_load_info_scripts): Also print inlined scripts.
	(maybe_print_unsupported_script_warning): Renamed from
	unsupported_script_warning_print.  All callers updated.
	(maybe_print_script_not_found_warning): Renamed from
	script_not_found_warning_print.  All callers updated.
	* extension-priv.h (struct extension_language_script_ops): New member
	objfile_script_executor.
	* extension.c (ext_lang_objfile_script_executor): New function.
	* extension.h (objfile_script_executor_func): New typedef.
	(ext_lang_objfile_script_executor): Declare.
	* guile/guile-internal.h (gdbscm_execute_objfile_script): Declare.
	* guile/guile.c (guile_extension_script_ops): Update.
	* guile/scm-objfile.c (gdbscm_execute_objfile_script): New function.
	* python/python.c (python_extension_script_ops): Update.
	(gdbpy_execute_objfile_script): New function.

gdb/doc/ChangeLog:

	* gdb.texinfo (dotdebug_gdb_scripts section): Update docs to
	distinguish script files vs inlined scripts.
	* python.texi (Python Auto-loading): Ditto.

gdb/testsuite/ChangeLog:

	* gdb.guile/scm-section-script.c: Add duplicate inlined section script
	entries.  Duplicate file section script entries.
	* gdb.guile/scm-section-script.exp: Add tests for duplicate entries,
	inlined entries.  Add test for safe-path rejection.
	* gdb.python/py-section-script.c: Add duplicate inlined section script
	entries.  Duplicate file section script entries.
	* gdb.python/py-section-script.exp: Add tests for duplicate entries,
	inlined entries.  Add test for safe-path rejection.
2015-01-31 12:01:13 -08:00
Alan Modra
3f8107ab38 FT32 initial support
FT32 is a new 32-bit RISC core developed by FTDI for embedded applications.

	* configure.ac: Add FT32 support.
	* configure: Regenerate.
bfd/
	* Makefile.am: Add FT32 files.
	* archures.c (enum bfd_architecture): Add bfd_arch_ft32.
	(bfd_mach_ft32): Define.
	(bfd_ft32_arch): Declare.
	(bfd_archures_list): Add bfd_ft32_arch.
	* config.bfd: Handle FT32.
	* configure.ac: Likewise.
	* cpu-ft32.c: New file.
	* elf32-ft32.c: New file.
	* reloc.c (BFD_RELOC_FT32_10, BFD_RELOC_FT32_20, BFD_RELOC_FT32_17,
	BFD_RELOC_FT32_18): Define.
	* targets.c (_bfd_target_vector): Add ft32_elf32_vec.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/SRC-POTFILES.in: Regenerate.
binutils/
	* readelf.c: Add FT32 support.
gas/
	* Makefile.am: Add FT32 files.
	* config/tc-ft32.c: New file.
	* config/tc-ft32.h: New file.
	* configure.tgt: Add FT32 support.
	* Makefile.in: Regenerate.
	* po/POTFILES.in: Regenerate.
gas/testsuite/
	* gas/ft32/ft32.exp: New file.
	* gas/ft32/insn.d: New file.
	* gas/ft32/insn.s: New file.
include/
	* dis-asm.h (print_insn_ft32): Declare.
include/elf/
	* common.h (EM_FT32): Define.
	* ft32.h: New file.
include/opcode/
	* ft32.h: New file.
ld/
	* Makefile.am: Add FT32 files.
	* configure.tgt: Handle FT32 target.
	* emulparams/elf32ft32.sh: New file.
	* scripttempl/ft32.sc: New file.
	* Makefile.in: Regenerate.
opcodes/
	* Makefile.am: Add FT32 files.
	* configure.ac: Handle FT32.
	* disassemble.c (disassembler): Call print_insn_ft32.
	* ft32-dis.c: New file.
	* ft32-opc.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.
2015-01-28 16:25:18 +10:30
Mark Wielaard
743649fd80 Use GCC5/DWARF5 DW_AT_noreturn to mark functions that don't return normally.
Add a flag field is_noreturn to struct func_type. Make calling_convention
a small bit field to not increase the size of the struct. Set is_noreturn
if the new GCC5/DWARF5 DW_AT_noreturn is set on a DW_TAG_subprogram.
Use this information to warn the user before doing a finish or return from
a function that does not return normally to its caller.

(gdb) finish
warning: Function endless does not return normally.
Try to finish anyway? (y or n)

(gdb) return
warning: Function does not return normally to caller.
Make endless return now? (y or n)

gdb/ChangeLog

	* dwarf2read.c (read_subroutine_type): Set TYPE_NO_RETURN from
	DW_AT_noreturn.
	* gdbtypes.h (struct func_type): Add is_noreturn field flag. Make
	calling_convention an 8 bit bit field.
	(TYPE_NO_RETURN): New macro.
	* infcmd.c (finish_command): Query if function does not return
	normally.
	* stack.c (return_command): Likewise.

gdb/testsuite/ChangeLog

	* gdb.base/noreturn-return.c: New file.
	* gdb.base/noreturn-return.exp: New file.
	* gdb.base/noreturn-finish.c: New file.
	* gdb.base/noreturn-finish.exp: New file.

include/ChangeLog

	* dwarf2.def (DW_AT_noreturn): New DWARF5 attribute.

The dwarf2.h addition and the code to emit the new attribute is already in
the gcc tree.
2015-01-23 17:29:19 +01:00
Andreas Krebbel
1e2e8c529c S/390: Add support for IBM z13.
- 32 128 bit vector registers (overlapping with the existing 16 64 bit
  floating point registers)
- vector double instructions
- vector integer instructions
- scalar vector instructions (allowing to have more floating point
  registers for scalar operations)
- vector string instructions

gas/ChangeLog:

	* config/tc-s390.c (struct pd_reg): Remove.
	(pre_defined_registers): Remove.
	(REG_NAME_CNT): Remove.
	(reg_name_search): Calculate the register number instead of doing
	a lookup.
	(register_name, tc_s390_regname_to_dw2regnum): Adopt to the new
	reg_name_search signature.
	(s390_parse_cpu): Support the new arch string z13.
	(s390_insert_operand): Support for vector registers with the extra
	field for the fifth bit of each vector register operand.
	(md_gather_operand): Adjust to the new handling of optional
	parameters.

	* doc/as.texinfo: Document the z13 cpu string.

gas/testsuite/ChangeLog:

	* gas/s390/esa-g5.d: Add a variant without the optional operand.
	* gas/s390/esa-g5.s: Likewise.
	* gas/s390/esa-z9-109.d: Likewise.
	* gas/s390/esa-z9-109.s: Likewise.
	* gas/s390/zarch-z9-109.d: Likewise.
	* gas/s390/zarch-z9-109.s: Likewise.
	* gas/s390/zarch-z10.d: For variants with a zero optional argument
	it is not dumped by objdump anymore.
	* gas/s390/zarch-zEC12.d: Likewise.

	* gas/s390/zarch-z13.d: New file.
	* gas/s390/zarch-z13.s: New file.
	* gas/s390/s390.exp: Run the test for the z13 files.

include/opcode/ChangeLog:

	* s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.

ld/testsuite/ChangeLog:

	* ld-s390/tlsbin.dd: The nopr register operand is optional and not
	printed if 0 anymore.

opcodes/ChangeLog:

	* s390-dis.c (s390_extract_operand): Support vector register
	operands.
	(s390_print_insn_with_opcode): Support new operands types and add
	new handling of optional operands.
	* s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
	and include opcode/s390.h instead.
	(struct op_struct): New field `flags'.
	(insertOpcode, insertExpandedMnemonic): New parameter `flags'.
	(dumpTable): Dump flags.
	(main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
	string.
	* s390-opc.c: Add new operands types, instruction formats, and
	instruction masks.
	(s390_opformats): Add new formats for .insn.
	* s390-opc.txt: Add new instructions.
2015-01-16 12:28:58 +01:00
Jan-Benedict Glaw
edabaaee81 Merge include/libiberty.h from GCC
This pulls in some missing prototypes and also adds corresponding entries
to the ChangeLog file. Please note that for one function, strverscmp(),
the ChangeLog entry was already there, but the actual prototype wasn't.

  These ChangeLog entries are added:

	2014-10-28  Yury Gribov  <y.gribov@samsung.com>

	       * libiberty.h (strtol, strtoul, strtoll, strtoull): New prototypes.

	2014-10-15  David Malcolm  <dmalcolm@redhat.com>

	       * libiberty.h (choose_tmpdir): New prototype.
2015-01-14 22:15:02 +01:00
Anthony Green
400cf8cbe9 Use official ELF machine number for moxie 2015-01-09 07:13:07 -05:00
Richard Earnshaw
7c89917ffa Sync with gcc/libiberty. 2015-01-07 17:34:29 +00:00
Alan Modra
60ebc25751 Fixes a buffer overflow when compiling assembler for the MinGW targets.
PR binutils/17754
	* internal.h (internal_auxent): Increase size of x_fname field to
	20 to allow for PE format's longer file names.
2015-01-06 16:46:40 +00:00
Alan Modra
b90efa5b79 ChangeLog rotatation and copyright year update 2015-01-02 00:53:45 +10:30
Joel Brobecker
32d0add0a6 Update year range in copyright notice of all files owned by the GDB project.
gdb/ChangeLog:

        Update year range in copyright notice of all files.
2015-01-01 13:32:14 +04:00
Anthony Green
bffb60047d Limit moxie sto/ldo offsets to 16 bits 2014-12-27 10:57:51 -05:00
Terry Guo
5c294fee9a ARM: Add support for value 3 of Tag_ABI_VFP_args attribute
*** bfd/ChangeLog ***

2014-12-25  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* elf32-arm.c (elf32_arm_merge_eabi_attributes): Handle new
	Tag_ABI_VFP_args value and replace hardcoded values by enum
	values.
	(elf32_arm_post_process_headers): Set e_flags in ELF header
	as hard float only when Tag_ABI_VFP_args is 1, using new enum
	value AEABI_VFP_args_vfp to check that.

*** binutils/ChangeLog ***

2014-12-25  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* readelf.c (arm_attr_tag_ABI_VFP_args): Add "compatible".

*** gdb/ChangeLog ***

2014-12-25  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* arm-tdep.c (arm_gdbarch_init): Explicitely handle value 3 of
	Tag_ABI_VFP_args. Also replace hardcoded values by enum values
	in the switch handling the different values of Tag_ABI_VFP_args.

*** gold/ChangeLog ***

2014-12-25  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* arm.cc (Target_arm::do_adjust_elf_header): Set e_flags in ELF
	header as hard float only when Tag_ABI_VFP_args is 1, using new
	enum value AEABI_VFP_args_vfp to check that.
	(Target_arm::merge_object_attributes): Handle new Tag_ABI_VFP_args
	value and replace hardcoded values by enum values.

*** include/elf/ChangeLog ***

2014-12-25  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* arm.h: New AEABI_FP_number_model_* and AEABI_VFP_args_* enum
	values.

*** ld/testsuite/ChangeLog ***

2014-12-25  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* ld-arm/attr-merge-2a.s: Add Tag_ABI_VFP_args.
	* ld-arm/attr-merge-2b.s: Likewise.
	* ld-arm/attr-merge-2.attr: Likewise.
	* ld-arm/attr-merge-4a.s: Add Tag_ABI_FP_number_model and
	Tag_ABI_VFP_args.
	* ld-arm/attr-merge-4b.s: Likewise.
	* ld-arm/attr-merge-4.attr: Likewise.
	* ld-arm/attr-merge-6a.s: Likewise.
	* ld-arm/attr-merge-6b.s: Likewise.
	* ld-arm/attr-merge-6.attr: Add Tag_ABI_FP_number_model.
2014-12-25 09:55:03 +08:00
Alan Modra
12b2843a6b Use a symbol flag bit to mark linker defined symbols
Trying to use the SEC_LINKER_CREATED section flag to determine whether
a symbol is linker defined fails to work on targets like alpha that
define special SEC_COMMON sections.  These might contain symbols that
originated in an object file.

include/
	* bfdlink.h (struct bfd_link_hash_entry): Comment non_ir_ref.  Add
	linker_def.
bfd/
	* elflink.c (_bfd_elf_define_linkage_sym): Set linker_def.
	* linker.c (_bfd_generic_link_add_one_symbol): Clear linker_def
	for CDEF, DEF, DEFW, COM.
ld/
	* ldexp.c (exp_fold_tree_1 <etree_provide>): Test linker_def.
ld/testsuite/
	* ld-powerpc/sdabase.s,
	* ld-powerpc/sdabase.t,
	* ld-powerpc/sdabase.d: New test.
	* ld-powerpc/sdabase2.t,
	* ld-powerpc/sdabase2.d: New test.
	* ld-powerpc/powerpc.exp: Run them.
2014-12-23 23:36:50 +10:30
Tom Tromey
a92a2e3435 add gcc/gdb interface files
The gcc plugin is split into two parts.  One part is an ordinary gcc
plugin.  The other part is a shared library that is loaded by gdb.

This patch adds some files that define the interface exported by this
shared library to gdb.  These files also define the internal API by
which the gdb- and gcc-sides communicate.

These files will be kept in sync between gcc and gdb like much of
include/.

The exported API has been intentionally kept very simple.  In
particular only a single function is exported from the gdb-side
library; symbol visibility is used to hide everything else.  This
exported symbol is a function which is called to return a structure
holding function pointers that gdb then uses.  This structure is
versioned so that changes can be made without necessarily requiring a
simultaneous gdb upgrade.

Note that the C compiler API is broken out separately.  This lets us
extend it to other GCC front ends as desired.  We plan to investigate
C++ in the future.

include/ChangeLog
2014-12-12  Phil Muldoon  <pmuldoon@redhat.com>
	    Jan Kratochvil  <jan.kratochvil@redhat.com>
	    Tom Tromey  <tromey@redhat.com>

	* gcc-c-fe.def: New file.
	* gcc-c-interface.h: New file.
	* gcc-interface.h: New file.
2014-12-12 22:23:53 +01:00
Eric Botcazou
d924db559b Add Visium support to bfd
bfd/
	* config.bfd: Add Visium support.
	* configure.ac: Likewise.
	* configure: Regenerate.
	* Makefile.am (ALL_MACHINES): Add cpu-visium.lo.
	(ALL_MACHINES_CFILES): Add cpu-visium.c.
	(BFD32_BACKENDS): Add elf32-visium.lo.
	(BFD32_BACKENDS_CFILES): Add elf32-visium.c.
	* Makefile.in: Regenerate.
	* archures.c (DESCRIPTION): Add Visium support.
	(bfd_visium_arch): Declare.
	(bfd_archures_list): Add bfd_visium_arch.
	* reloc.c: Add Visium relocations.
	* targets.c (visium_elf32_vec): Declare.
	(_bfd_target_vector): Add visium_elf32_vec.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Likewise.
	* cpu-visium.c: New file.
	* elf32-visium.c: Likewise.
	* po/SRC-POTFILES.in: Regenerate.
include/elf/
	* common.h (EM_VISIUM): Define.
	* visium.h: New file.
2014-12-06 16:35:18 +01:00
Eric Botcazou
1945cfa59d Add Visium support to opcodes
include/
	* dis-asm.h (print_insn_visium): Declare.
include/opcode/
	* visium.h: New file.
opcodes/
	* configure.ac: Add Visium support.
	* configure: Regenerate.
	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add visium-dis.c and
	visium-opc.c.
	* Makefile.in: Regenerate.
	* disassemble.c (ARCH_visium): Define if ARCH_all.
	(disassembler): Deal with bfd_arch_visium if ARCH_visium.
	* visium-dis.c: New file.
	* visium-opc.c: Likewise.
	* po/POTFILES.in: Regenerate.
2014-12-06 16:25:55 +01:00
Joel Brobecker
2d7bb7580a callback.h:struct host_callback_struct compilation error on Windows hosts.
On Windows, a recent gnulib update imported the lstat module, and
this caused a remote-sim.c build failure in struct host_callback_struct:

    In file included from /[...]/gdb/remote-sim.c:34:0:
    /[...]/gdb/../include/gdb/callback.h:93:9: error: duplicate member '_stati64'
       int (*lstat) (host_callback *, const char *, struct stat *);
             ^
What happens it that gnulib's stat.h makes the following defines:

     /* Large File Support on native Windows.  */
     #if 1
     # define stat _stati64
     #endif

and then:

    #if 1
    # if ! 0
    /* mingw does not support symlinks, therefore it does not have lstat.  But
       without links, stat does just fine.  */
    #  if !(defined __cplusplus && defined GNULIB_NAMESPACE)
    #   define lstat stat
    #  endif

So, the following fields in struct host_callback_struct...

      int (*stat) (host_callback *, const char *, struct stat *);
      int (*fstat) (host_callback *, int, struct stat *);
      int (*lstat) (host_callback *, const char *, struct stat *);

... get translated to...

      int (*_stati64) (host_callback *, const char *, struct _stati64 *);
      int (*_fstati64) (host_callback *, int, struct _stati64 *);
      int (*_stati64) (host_callback *, const char *, struct _stati64 *);

... which causes two fields to have the same name.

This patch fixes the issue by renaming the stat-related fields
by adding a "to_" prefix, similar to what is done in GDB's
target_ops vector.

include/gdb/ChangeLog:

	* callback.h (struct host_callback_struct) <to_stat>: Renamed
	from "stat".
	<to_fstat>: Renamed from "fstat".
	<to_lstat>: Renamed from "lstat".

sim/common/ChangeLog:

	* sim-io.c (sim_io_stat, sim_io_fstat): Adjust calls to "stat"
	and "fstat" callbacks by calls to "to_stat" and "to_fstat" (resp)
	callbacks following renaming in callback.h.
	* syscall.c (cb_syscall): Likewise.  Adjust calls to "lstat"
	callback by call to "to_lstat" callback

sim/cris/ChangeLog:

	* traps.c (cris_break_13_handler): Adjust call to "fstat" callback
	by call to "to_fstat" following renaming in callback.h.

sim/h8300/ChangeLog:

	* compile.c (sim_resume):  Adjust calls to "stat" and "fstat"
	callbacks by calls to "to_stat" and "to_fstat" (resp) callbacks
	following renaming in callback.h.
2014-12-03 13:43:08 +04:00
Sandra Loosemore
d306ce58b4 Remove broken nios2 assembler dwim support.
2014-11-28  Sandra Loosemore  <sandra@codesourcery.com>

	include/opcode/
	* nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
	(NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
	(NIOS2_INSN_OPTARG): Renumber.

	opcodes/
	* nios2-opc.c (nios2_r1_opcodes): Remove deleted attributes
	from descriptors.

	gas/
	* config/tc-nios2.c (can_evaluate_expr, get_expr_value): Delete.
	(output_addi, output_andi, output_ori, output_xori): Delete.
	(md_assemble): Remove calls to deleted functions.

	gas/testsuite/
	* gas/nios2/nios2.exp: Make "movi" a list test.
	* gas/nios2/movi.s: Adjust comments, add another case.
	* gas/nios2/movi.l: New.
	* gas/nios2/movi.d: Delete.
2014-11-28 14:41:32 -08:00
Mark Wielaard
0cfd832fc7 Recognize new DWARFv5 C11, C++11 and C++14 DW_LANG constants.
gdb/ChangeLog

	* dwarf2read.c (set_cu_language): Recognize DW_LANG_C11,
	DW_LANG_C_plus_plus_11, DW_LANG_C_plus_plus_14.

include/ChangeLog

	* dwarf2.h: Add DW_LANG_C_plus_plus_11, DW_LANG_C11 and
	DW_LANG_C_plus_plus_14.
2014-11-26 12:47:29 +01:00
Andrew Burgess
b8b64fa5e4 Merge include/* files from GCC commit 69a2f316d3.
include/ChangeLog:

	* dwarf2.def (DW_AT_APPLE_optimized, DW_AT_APPLE_flags)
	(DW_AT_APPLE_isa, DW_AT_APPLE_block)
	(DW_AT_APPLE_major_runtime_vers, DW_AT_APPLE_runtime_class)
	(DW_AT_APPLE_omit_frame_ptr, DW_AT_APPLE_property_name)
	(DW_AT_APPLE_property_getter, DW_AT_APPLE_property_setter)
	(DW_AT_APPLE_property_attribute, DW_AT_APPLE_objc_complete_type)
	(DW_AT_APPLE_property): New macros.
2014-11-21 22:47:32 +00:00
Andrew Burgess
e235c3a213 Merge include/* files from GCC commit 77cab4753.
include/ChangeLog:

	PR debug/63239
	* dwarf2.def (DW_AT_GNU_deleted): New attribute.
2014-11-21 22:46:39 +00:00
Terry Guo
a715796ba1 Support ARM Cortex-M7
include/ChangeLog:
2014-11-21  Terry Guo  <terry.guo@arm.com>

	* opcode/arm.h (FPU_VFP_EXT_ARMV8xD): New macro.
	(FPU_VFP_V5D16): Likewise.
	(FPU_VFP_V5_SP_D16): Likewise.
	(FPU_ARCH_VFP_V5D16): Likewise.
	(FPU_ARCH_VFP_V5_SP_D16): Likewise.

bfd/ChangeLog:
2014-11-21  Terry Guo  <terry.guo@arm.com>

	* elf32-arm.c (elf32_arm_merge_eabi_attributes): Support FPv5.

binutils/ChangeLog:
2014-11-21  Terry Guo  <terry.guo@arm.com>

	* readelf.c (arm_attr_tag_FP_arch): Extended to support FPv5.

gas/ChangeLog:
2014-11-21  Terry Guo  <terry.guo@arm.com>

	* config/tc-arm.c (fpu_vfp_ext_armv8xd): New.
	(arm_cpus): Support cortex-m7.
	(arm_fpus): Support fpv5-sp-d16 and fpv5-d16.
	(do_vfp_nsyn_cvt_fpv8): Generate error when use D register for S
	register only target like FPv5-SP-D16.
	(do_neon_cvttb_1): Likewise.
	(do_vfp_nsyn_fpv8): Likewise.
	(do_vrint_1): Likewise.
	(aeabi_set_public_attributes): Set proper FP arch for FPv5.
	* doc/c-arm.texi: Document new cpu and fpu names for cortex-m7.

gas/testsuite/ChangeLog:
2014-11-21  Terry Guo  <terry.guo@arm.com>

	* gas/arm/armv7e-m+fpv5-d16.s: New.
	* gas/arm/armv7e-m+fpv5-d16.d: Likewise.
	* gas/arm/armv7e-m+fpv5-sp-d16.s: Likewise.
	* gas/arm/armv7e-m+fpv5-sp-d16.d: Likewise.

ld/testsuite/ChangeLog:
2014-11-21  Terry Guo  <terry.guo@arm.com>

	* ld-arm/attr-merge-vfp-4-sp.s: New test source file.
	* ld-arm/attr-merge-vfp-5-sp.s: Likewise.
	* ld-arm/attr-merge-vfp-5.s: Likewise.
	* ld-arm/attr-merge-vfp-8.d: New test.
	* ld-arm/attr-merge-vfp-8r.d: Likewise.
	* ld-arm/attr-merge-vfp-9.d: Likewise.
	* ld-arm/attr-merge-vfp-9r.d: Likewise.
	* ld-arm/attr-merge-vfp-10.d: Likewise.
	* ld-arm/attr-merge-vfp-10r.d: Likewise.
	* ld-arm/attr-merge-vfp-11.d: Likewise.
	* ld-arm/attr-merge-vfp-11r.d: Likewise.
	* ld-arm/attr-merge-vfp-12.d: Likewise.
	* ld-arm/attr-merge-vfp-12r.d: Likewise.
	* ld-arm/attr-merge-vfp-13.d: Likewise.
	* ld-arm/attr-merge-vfp-13r.d: Likewise.
	* ld-arm/attr-merge-vfp-14.d: Likewise.
	* ld-arm/attr-merge-vfp-14r.d: Likewise.
	* ld-arm/arm-elf.exp: Run the new tests.
2014-11-21 11:36:06 +08:00
Igor Zamyatin
d258b82828 Add -z bndplt to generate BND prefix in PLT entries
This patch adds "-z bndplt" option Linux/x86-64 linker to generate BND
prefix in PLT entries.  It also updated Linux/x86-64 assembler not to
generate R_X86_64_PLT32_BND nor R_X86_64_PC32_BND relocations.

bfd/

2014-11-18  Igor Zamyatin  <igor.zamyatin@intel.com>

	* elf64-x86-64.c (elf_x86_64_check_relocs): Enable MPX PLT only
	for -z bndplt.

gas/

2014-11-18  Igor Zamyatin  <igor.zamyatin@intel.com>

	* config/tc-i386-intel.c (i386_operator): Remove last argument
	from lex_got call.
	* config/tc-i386.c (reloc): Remove bnd_prefix from parameters'
	list.  Return always BFD_RELOC_32_PCREL.
	* (output_branch): Remove condition for BFD_RELOC_X86_64_PC32_BND.
	* (output_jump): Update call to reloc accordingly.
	* (output_interseg_jump): Likewise.
	* (output_disp): Likewise.
	* (output_imm): Likewise.
	* (x86_cons_fix_new): Likewise.
	* (lex_got): Remove bnd_prefix from parameters' list in macro and
	declarations. Don't use BFD_RELOC_X86_64_PLT32_BND.
	* (x86_cons): Update call to lex_got accordingly.
	* (i386_immediate): Likewise.
	* (i386_displacement): Likewise.
	* (md_apply_fix): Don't use BFD_RELOC_X86_64_PLT32_BND nor
	BFD_RELOC_X86_64_PC32_BND.
	* (tc_gen_reloc): Likewise.

include/

2014-11-18  Igor Zamyatin  <igor.zamyatin@intel.com>

	* bfdlink.h (struct bfd_link_info): Add bndplt.

ld/

2014-11-18  Igor Zamyatin  <igor.zamyatin@intel.com>

	* emulparams/elf_x86_64.sh (BNDPLT): Set to yes for x86_64.
	* emultempl/elf32.em (gld${EMULATION_NAME}_handle_option): Handle
	"-z bndplt" if BNDPLT is yes.
	(gld${EMULATION_NAME}_list_options): Add "-z bndplt" entry.
	* ld.texinfo: Add description for bndplt.

ld/testsuite/

2014-11-18  Igor Zamyatin  <igor.zamyatin@intel.com>

	* testsuite/ld-x86-64/bnd-ifunc-1.d: Add bndplt option.
	* testsuite/ld-x86-64/bnd-ifunc-2.d: Likewise.
	* testsuite/ld-x86-64/bnd-plt-1.d: Likewise.  Update dissassembly
	sections.
	* testsuite/ld-x86-64/mpx.exp: Handle mpx3 and mpx4 tests.
	* testsuite/ld-x86-64/mpx1a.rd: Remove _BND from relocation name.
	* testsuite/ld-x86-64/mpx1c.rd: Likewise.
	* testsuite/ld-x86-64/mpx2a.rd: Likewise.
	* testsuite/ld-x86-64/mpx2c.rd: Likewise.
	* testsuite/ld-x86-64/mpx3.dd: New file.
	* testsuite/ld-x86-64/mpx3a.s: Likewise.
	* testsuite/ld-x86-64/mpx3b.s: Likewise.
	* testsuite/ld-x86-64/mpx4.dd: Likewise.
	* testsuite/ld-x86-64/mpx4a.s: Likewise.
	* testsuite/ld-x86-64/mpx4b.s: Likewise.
2014-11-18 05:40:17 -08:00
H.J. Lu
0be3630492 Mark R_X86_64_GOTPLT64 obsolete
* x86-64.h (R_X86_64_GOTPLT64): Mark it obsolete.
2014-11-13 11:26:47 -08:00
Sandra Loosemore
b4714c7c30 Add mach parameter to nios2_find_opcode_hash.
2014-11-06  Sandra Loosemore  <sandra@codesourcery.com>

	include/opcode/
	* nios2.h (nios2_find_opcode_hash): Add mach parameter to
	declaration.  Fix obsolete comment.

	opcodes/
	* nios2-dis.c (nios2_find_opcode_hash): Add mach parameter.
	(nios2_disassemble): Adjust call to nios2_find_opcode_hash.

	gas/
	* config/tc-nios2.c (nios2_diagnose_overflow): Adjust call to
	nios2_find_opcode_hash.
2014-11-06 13:12:21 -08:00
Naveen H.S
2c62985659 MIPS: Add Octeon 3 support
binutils:
2014-10-31  Andrew Pinski  <apinski@cavium.com>
            Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* readelf.c (print_mips_isa_ext): Print the value of Octeon3.

gas:
2014-10-31  Andrew Pinski  <apinski@cavium.com>
            Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* config/tc-mips.c (CPU_IS_OCTEON): Handle CPU_OCTEON3.
	(mips_cpu_info_table): Octeon3 enables virt ase.
	* doc/c-mips.texi: Document octeon3 as an acceptable value for
	-march=.

gas/testsuite:
2014-10-31  Andrew Pinski  <apinski@cavium.com>
            Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* gas/mips/mips.exp: Add support for Octeon3 architecture.
	Also add in support for running Octeon3 tests.
	* gas/mips/octeon3.d: New test.
	* gas/mips/octeon3.s: New test source.

opcodes:
2014-10-31  Andrew Pinski  <apinski@cavium.com>
            Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* mips-dis.c (mips_arch_choices): Add octeon3.
	* mips-opc.c (IOCT): Include INSN_OCTEON3.
	(IOCT2): Likewise.
	(IOCT3): New define.
	(IVIRT): New define.
	(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
	tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
	IVIRT instructions.
	Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
	operand for IOCT3.

bfd:
2014-10-31  Andrew Pinski  <apinski@cavium.com>
            Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* archures.c: Add octeon3 for mips target.
	* bfd-in2.h: Regenerate.
	* bfd/cpu-mips.c: Define I_mipsocteon3.
	nfo_struct): Add octeon3 support.
	* bfd/elfxx-mips.c: (_bfd_elf_mips_mach): Add support for
	octeon3.
	(mips_set_isa_flags): Add support for octeon3.
	(bfd_mips_isa_ext): Add bfd_mach_mips_octeon3.
	(mips_mach_extensions): Make bfd_mach_mips_octeon3 an
	extension of bfd_mach_mips_octeon2.
	(print_mips_isa_ext): Print the value of Octeon3.
2014-10-31 13:50:10 -07:00
Sandra Loosemore
96ba42336f Refactoring/cleanup of nios2 opcodes and assembler code.
2014-10-23  Sandra Loosemore  <sandra@codesourcery.com>

	include/opcode/
	* nios2.h (enum iw_format_type): New.
	(struct nios2_opcode): Update comments.  Add size and format fields.
	(NIOS2_INSN_OPTARG): New.
	(REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
	(struct nios2_reg): Add regtype field.
	(GET_INSN_FIELD, SET_INSN_FIELD): Delete.
	(IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
	(IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
	(IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
	(IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
	(IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
	(IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
	(IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
	(IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
	(IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
	(IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
	(IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
	(OP_MASK_OP, OP_SH_OP): Delete.
	(OP_MASK_IOP, OP_SH_IOP): Delete.
	(OP_MASK_IRD, OP_SH_IRD): Delete.
	(OP_MASK_IRT, OP_SH_IRT): Delete.
	(OP_MASK_IRS, OP_SH_IRS): Delete.
	(OP_MASK_ROP, OP_SH_ROP): Delete.
	(OP_MASK_RRD, OP_SH_RRD): Delete.
	(OP_MASK_RRT, OP_SH_RRT): Delete.
	(OP_MASK_RRS, OP_SH_RRS): Delete.
	(OP_MASK_JOP, OP_SH_JOP): Delete.
	(OP_MASK_IMM26, OP_SH_IMM26): Delete.
	(OP_MASK_RCTL, OP_SH_RCTL): Delete.
	(OP_MASK_IMM5, OP_SH_IMM5): Delete.
	(OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
	(OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
	(OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
	(OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
	(OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
	(OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
	(OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
	(OP_MASK_<insn>, OP_MASK): Delete.
	(GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
	(GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
	Include nios2r1.h to define new instruction opcode constants
	and accessors.
	(nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
	(bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
	(bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
	(NUMOPCODES, NUMREGISTERS): Delete.
	* nios2r1.h: New file.

	opcodes/
	* nios2-opc.c (nios2_builtin_regs): Add regtype field initializers.
	(nios2_builtin_opcodes): Rename to nios2_r1_opcodes.  Use new
	MATCH_R1_<insn> and MASK_R1_<insn> macros in initializers.  Add
	size and format initializers.  Merge 'b' arguments into 'j'.
	(NIOS2_NUM_OPCODES): Adjust definition.
	(bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
	(nios2_opcodes): Adjust.
	(bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
	* nios2-dis.c (INSNLEN): Update comment.
	(nios2_hash_init, nios2_hash): Delete.
	(OPCODE_HASH_SIZE): New.
	(nios2_r1_extract_opcode): New.
	(nios2_disassembler_state): New.
	(nios2_r1_disassembler_state): New.
	(nios2_init_opcode_hash): Add state parameter.  Adjust to use it.
	(nios2_find_opcode_hash): Use state object.
	(bad_opcode): New.
	(nios2_print_insn_arg): Add op parameter.  Use it to access
	format.  Remove 'b' case.
	(nios2_disassemble): Remove special case for nop.  Remove
	hard-coded instruction size.

	gas/
	* config/tc-nios2.c (nios2_insn_infoS): Add constant_bits field.
	(nios2_arg_infoS, nios2_arg_hash, nios2_arg_lookup): Delete.
	(nios2_control_register_arg_p): Delete.
	(nios2_coproc_reg): Delete.
	(nios2_relax_frag): Remove hard-coded instruction size.
	(md_convert_frag): Use new insn accessor macros.
	(nios2_diagnose_overflow): Remove hard-coded instruction size.
	(md_apply_fix): Likewise.
	(bad_opcode): New.
	(nios2_parse_reg): New.
	(nios2_assemble_expression): Remove prev_reloc parameter.  Adjust
	uses and callers.
	(nios2_assemble_arg_c): New.
	(nios2_assemble_arg_d): New.
	(nios2_assemble_arg_s): New.
	(nios2_assemble_arg_t): New.
	(nios2_assemble_arg_i): New.
	(nios2_assemble_arg_u): New.
	(nios2_assemble_arg_o): New.
	(nios2_assemble_arg_j): New.
	(nios2_assemble_arg_l): New.
	(nios2_assemble_arg_m): New.
	(nios2_assemble_args): New.
	(nios2_assemble_args_dst): Delete.
	(nios2_assemble_args_tsi): Delete.
	(nios2_assemble_args_tsu): Delete.
	(nios2_assemble_args_sto): Delete.
	(nios2_assemble_args_o): Delete.
	(nios2_assemble_args_is): Delete.
	(nios2_assemble_args_m): Delete.
	(nios2_assemble_args_s): Delete.
	(nios2_assemble_args_tis): Delete.
	(nios2_assemble_args_dc): Delete.
	(nios2_assemble_args_cs): Delete.
	(nios2_assemble_args_ds): Delete.
	(nios2_assemble_args_ldst): Delete.
	(nios2_assemble_args_none): Delete.
	(nios2_assemble_args_dsj): Delete.
	(nios2_assemble_args_d): Delete.
	(nios2_assemble_args_b): Delete.
	(nios2_arg_info_structs): Delete.
	(NIOS2_NUM_ARGS): Delete.
	(nios2_consume_arg): Remove insn parameter.  Use new macros.
	Don't check register arguments here.  Remove 'b' case.
	(nios2_consume_separator): Move check for missing separators to...
	(nios2_parse_args): ...here.  Remove special case for optional
	arguments.
	(output_insn): Avoid using hard-coded insn size.
	(output_ubranch): Likewise.
	(output_cbranch): Likewise.
	(output_call): Use new macros.
	(output_addi): Likewise.
	(output_ori): Likewise.
	(output_xori): Likewise.
	(output_movia): Likewise.
	(md_begin): Remove nios2_arg_info_structs initialization.
	(md_assemble): Initialize constant_bits field.  Use
	nios2_parse_args instead of looking up parse function in hash table.

	gdb/
	* nios2-tdep.c (nios2_analyze_prologue): Use new instruction field
	accessors and constants from nios2 opcodes update.
	(nios2_get_next_pc): Likewise.
2014-10-23 09:54:15 -07:00
Matthew Fortune
00ac7aa072 Show information about unknown ASEs and extensions in .MIPS.abiflags
bfd/
	* elfxx-mips.c (print_mips_ases): Print unknown ASEs.
	(print_mips_isa_ext): Print the value of an unknown extension.

binutils/

	* readelf.c (print_mips_ases): Print unknown ASEs.
	(print_mips_isa_ext): Print the value of an unknown extension.

include/

	* elf/mips.h (AFL_ASE_MASK): Define.
2014-10-22 10:37:26 +01:00
Jose E. Marchesi
0b6be41550 opcodes, elf: annotate instructions with HWCAP2_VIS3B.
This patch annotates the following SPARC instructions as VIS3B
instructions: ldx *, %efsr, fpadd64, fpsub64, fpcmpule8, fpcmpune8,
fpcmpugt8, fpcmpueq8.  It also improves the documentation of the VIS3B
capability in several headers.

Tested in sparc64-unknown-linux-gnu and sparc-unknown-linux-gnu.
No visible regressions.

opcodes/ChangeLog:

  2014-10-17  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc-opc.c (sparc-opcodes): Annotate several instructions with
	the HWCAP2_VIS3B hwcap.

include/opcodes/ChangeLog:

  2014-10-17  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc.h (HWCAP2_VIS3B): Documentation improved.

include/elf/ChangeLog:

  2014-10-17  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc.h (ELF_SPARC_HWCAP2_VIS3B): Documentation improved.
2014-10-17 22:00:02 +02:00
Iain Buclaw
b55f967878 Sync libiberty with upstream GCC.
include/ChangeLog
	* libiberty.h (PEX_STDOUT_APPEND): New flag.
	(PEX_STDERR_APPEND): Likewise.

	* demangle.h (DMGL_DLANG): New macro.
	(DMGL_STYLE_MASK): Add DMGL_DLANG.
	(demangling_styles): Add dlang_demangling.
	(DLANG_DEMANGLING_STYLE_STRING): New macro.
	(DLANG_DEMANGLING): New macro.
	(dlang_demangle): New prototype.

	* longlong.h: Add __udiv_w_sdiv prototype.

libiberty/ChangeLog
	* cp-demangle.c (d_substitution): Handle abi tags on abbreviation.

	* pex-common.h (struct pex_funcs): Add new parameter for open_write field.
	* pex-unix.c (pex_unix_open_write): Add support for new parameter.
	* pex-djgpp.c (pex_djgpp_open_write): Likewise.
	* pex-win32.c (pex_win32_open_write): Likewise.
	* pex-common.c (pex_run_in_environment): Likewise.

	* Makefile.in (CFILES): Add d-demangle.c.
	(REQUIRED_OFILES): Add d-demangle.o.
	* cplus-dem.c (libiberty_demanglers): Add dlang_demangling case.
	(cplus_demangle): Likewise.
	* d-demangle.c: New file.
	* testsuite/Makefile.in (really-check): Add check-d-demangle.
	* testsuite/d-demangle-expected: New file.

	* simple-object-elf.c (simple_object_elf_write_ehdr): Correctly
	handle objects with more than SHN_LORESERVE sections.
	(simple_object_elf_write_shdr): Add sh_link parameter.
	(simple_object_elf_write_to_file): Correctly handle objects with
	more than SHN_LORESERVE sections.

	* cp-demangle.c (d_dump): Only access field from s_fixed part of
	the union for DEMANGLE_COMPONENT_FIXED_TYPE.
	(d_count_templates_scopes): Likewise.

	* testsuite/demangler-fuzzer.c: New file.
	* testsuite/Makefile.in (fuzz-demangler): New rule.
	(demangler-fuzzer): Likewise.
	(mostlyclean): Clean up demangler fuzzer.
2014-10-11 10:29:10 +01:00
Jose E. Marchesi
3d68f91c0f This is a series of patches that add support for the SPARC M7 cpu to
binutils.  They were discussed and approved here:

  https://sourceware.org/ml/binutils/2014-10/msg00038.html
2014-10-09 13:16:53 +01:00
Will Newton
23664eacaf include/elf/aarch64.h: Add reloc numbers from ABI release 1.0
Add the relocation numbers defined in ABI release 1.0 but missing
from the current header. This will allow tools like objdump to dump
objects that use these relocations.

include/elf/ChangeLog:

2014-10-08  Will Newton  <will.newton@linaro.org>

	* aarch64.h: Sync up relocations with ABI release 1.0.
2014-10-08 10:07:45 +01:00
Kuan-Lin Chen
1c8f6a4d1f NDS32: Code refactoring of relaxation.
Refactor each relaxation pattern to raise the maintainability.
In origin, all patterns is analysed in nds32_elf_relax_section,
so it is hard to debug and maintain.  Therefore, we classify all
patterns into different functions in this patch.
Moreover, we adjust all optimizations into nds32_elf_relax_section
to take these optimizations in turn.  This can promise all relaxation
being done after calling gld${EMULATION_NAME}_after_allocation.
2014-09-16 13:08:00 +08:00
Kuan-Lin Chen
40c7a7cb74 NDS32/opcodes: Add audio ISA extension and modify the disassemble implemnt.
First, add nds32 audio ISA extension including opcodes and registers.
Second, redesign the disassemble implement.
The original disassemble decode instruction opcode using switch-case.
It is hard to synchronize when adding new instructions.
Therefore, the new implement reuses nds32_opcodes to dump the instructions.
2014-09-16 12:28:11 +08:00
Andrew Bennett
7361da2c95 Add support for MIPS R6.
bfd/
 	* aoutx.h (NAME (aout, machine_type)): Add mips32r6 and mips64r6.
 	* archures.c (bfd_architecture): Likewise.
 	* bfd-in2.h (bfd_architecture): Likewise.
 	(bfd_reloc_code_real): Add relocs BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3 and
 	BFD_RELOC_MIPS_19_PCREL_S2.
 	* cpu-mips.c (arch_info_struct): Add mips32r6 and mips64r6.
 	* elf32-mips.c: Define relocs R_MIPS_PC21_S2, R_MIPS_PC26_S2
 	R_MIPS_PC18_S3, R_MIPS_PC19_S2, R_MIPS_PCHI16 and R_MIPS_PCLO16.
 	(mips_reloc_map): Add entries for BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
 	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
 	BFD_RELOC_LO16_PCREL.
 	* elf64-mips.c: Define REL, and RELA relocations R_MIPS_PC21_S2,
	R_MIPS_PC26_S2, R_MIPS_PC18_S3, R_MIPS_PC19_S2, R_MIPS_PCHI16
	and R_MIPS_PCLO16.
 	(mips_reloc_map): Add entries for BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
 	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
 	BFD_RELOC_LO16_PCREL.
 	* elfn32-mips.c: Likewise.
 	* elfxx-mips.c (MIPSR6_P): New define.
 	(mipsr6_exec_plt_entry): New array.
	(hi16_reloc_p): Add support for R_MIPS_PCHI16.
	(lo16_reloc_p): Add support for R_MIPS_PCLO16.
 	(aligned_pcrel_reloc_p): New function.
 	(mips_elf_relocation_needs_la25_stub): Add support for relocs:
 	R_MIPS_PC21_S2 and R_MIPS_PC26_S2.
 	(mips_elf_calculate_relocation): Add support for relocs:
 	R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3, R_MIPS_PC19_S2,
 	R_MIPS_PCHI16 and R_MIPS_PCLO16.
 	(_bfd_elf_mips_mach): Add support for mips32r6 and mips64r6.
	(mips_elf_add_lo16_rel_addend): Add support for R_MIPS_PCHI16.
 	(_bfd_mips_elf_check_relocs): Add support for relocs:
	R_MIPS_PC21_S2 and R_MIPS_PC26_S2.
 	(_bfd_mips_elf_relocate_section): Add a check for unaligned
 	pc relative relocs.
 	(_bfd_mips_elf_finish_dynamic_symbol): Add support for MIPS r6
 	plt entry.
 	(mips_set_isa_flags): Add support for mips32r6 and mips64r6.
 	(_bfd_mips_elf_print_private_bfd_data): Likewise.
 	(mips_32bit_flags_p): Add support for mips32r6.
 	* libbfd.h (bfd_reloc_code_real_names): Add entries for
 	BFD_RELOC_MIPS_21_PCREL_S2, BFD_RELOC_MIPS_26_PCREL_S2,
 	BFD_RELOC_MIPS_18_PCREL_S3 and BFD_RELOC_MIPS_19_PCREL_S2.
 	* reloc.c: Document relocs BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3 and
 	BFD_RELOC_MIPS_19_PCREL_S2.

binutils/
 	* readelf.c (get_machine_flags): Add support for mips32r6 and
 	mips64r6.

elfcpp/
 	* mips.h (E_MIPS_ARCH_32R6, E_MIPS_ARCH_64R6): New enum constants.

gas/
 	* config/tc-mips.c (mips_nan2008): New static global.
	(mips_flag_nan2008): Removed.
	(LL_SC_FMT): New define.
	(COP12_FMT): Updated.
	(ISA_IS_R6): New define.
 	(ISA_HAS_64BIT_REGS): Add mips64r6.
 	(ISA_HAS_DROR): Likewise.
 	(ISA_HAS_64BIT_FPRS): Add mips32r6 and mips64r6.
 	(ISA_HAS_ROR): Likewise.
 	(ISA_HAS_ODD_SINGLE_FPR): Likewise.
 	(ISA_HAS_MXHC1): Likewise.
 	(hilo_interlocks): Likewise.
 	(md_longopts): Likewise.
	(ISA_HAS_LEGACY_NAN): New define.
 	(options): Add OPTION_MIPS32R6 and OPTION_MIPS64R6.
 	(mips_ase): Add field rem_rev.
 	(mips_ases): Updated to add which ISA an ASE was removed in.
 	(mips_isa_rev): Add support for mips32r6 and mips64r6.
 	(mips_check_isa_supports_ase): Add support to check if an ASE
 	has been removed in the specified MIPS ISA revision.
 	(validate_mips_insn): Skip '-' character.
	(macro_build): Likewise.
	(mips_check_options): Prevent R6 working with fp32, mips16,
	micromips, or branch relaxation.
	(file_mips_check_options): Set R6 floating point registers to
	64 bit.  Also deal with the nan2008 option.
 	(limited_pcrel_reloc_p): Add relocs: BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
 	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
 	BFD_RELOC_LO16_PCREL.
 	(operand_reg_mask): Add support for OP_SAME_RS_RT, OP_CHECK_PREV
	and OP_NON_ZERO_REG.
 	(match_check_prev_operand): New static function.
 	(match_same_rs_rt_operand): New static function.
	(match_non_zero_reg_operand): New static function.
 	(match_operand): Added entries for: OP_SAME_RS_RT, OP_CHECK_PREV
	and OP_NON_ZERO_REG.
 	(insns_between): Added case to deal with forbidden slots.
 	(append_insn): Added support for relocs: BFD_RELOC_MIPS_21_PCREL_S2
 	and BFD_RELOC_MIPS_26_PCREL_S2.
 	(match_insn): Add support for operands -A, -B, +' and +".  Also
 	skip '-' character.
 	(mips_percent_op): Add entries for %pcrel_hi and %pcrel_lo.
 	(md_parse_option): Add support for mips32r6 and mips64r6.  Also
	update the nan option handling.
 	(md_pcrel_from): Add cases for relocs: BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2.
 	(mips_force_relocation): Prevent forced relaxation for MIPS r6.
 	(md_apply_fix): Add support for relocs: BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
 	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
 	BFD_RELOC_LO16_PCREL.
 	(s_mipsset): Add support for mips32r6 and mips64r6.
	(s_nan): Update to support the new nan2008 framework.
 	(tc_gen_reloc): Add relocs: BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
 	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
 	BFD_RELOC_LO16_PCREL.
	(mips_elf_final_processing): Updated to use the mips_nan2008.
 	(mips_cpu_info_table): Add entries for mips32r6 and mips64r6.
	(macro): Enable ldc2, sdc2, ll, lld, swc2, sc, scd, cache, pref
	macros for R6.
	(mips_fix_adjustable): Make PC relative R6 relocations relative
	to the symbol and not the section.
 	* configure.ac: Add support for mips32r6 and mips64r6.
 	* configure: Regenerate.
 	* doc/c-mips.texi: Document the -mips32r6 and -mips64r6 command line
 	options.
	* doc/as.texinfo: Likewise.

gas/testsuite/
	* gas/mips/24k-triple-stores-1.s: If testing for r6 prevent
	non-supported instructions from being tested.
	* gas/mips/24k-triple-stores-2.s: Likewise.
	* gas/mips/24k-triple-stores-3.s: Likewise.
	* gas/mips/24k-triple-stores-6.s: Likewise.
	* gas/mips/beq.s: Likewise.
	* gas/mips/eva.s: Likewise.
	* gas/mips/ld-zero-3.s: Likewise.
	* gas/mips/mips32-cp2.s: Likewise.
	* gas/mips/mips32.s: Likewise.
	* gas/mips/mips4.s: Likewise.
	* gas/mips/add.s: Don't test the add instructions if r6, and
	add padding.
	* gas/mips/add.d: Check for a triple dot not a nop at the end of the
	disassembly output.
	* gas/mips/micromips@add.d: Likewise.
	* gas/mips/mipsr6@24k-branch-delay-1.d: New file.
	* gas/mips/mipsr6@24k-triple-stores-1.d: New file.
	* gas/mips/mipsr6@24k-triple-stores-2-llsc.d: New file.
	* gas/mips/mipsr6@24k-triple-stores-2.d: New file.
	* gas/mips/mipsr6@24k-triple-stores-3.d: New file.
	* gas/mips/mipsr6@24k-triple-stores-6.d: New file.
	* gas/mips/mipsr6@add.d: New file.
	* gas/mips/mipsr6@attr-gnu-4-1-msingle-float.l: New file.
	* gas/mips/mipsr6@attr-gnu-4-1-msingle-float.s: New file.
	* gas/mips/mipsr6@attr-gnu-4-1-msoft-float.l: New file.
	* gas/mips/mipsr6@attr-gnu-4-1-msoft-float.s: New file.
	* gas/mips/mipsr6@attr-gnu-4-2-mdouble-float.l: New file.
	* gas/mips/mipsr6@attr-gnu-4-2-mdouble-float.s: New file.
	* gas/mips/mipsr6@beq.d: New file.
	* gas/mips/mipsr6@bge.d: New file.
	* gas/mips/mipsr6@bgeu.d: New file.
	* gas/mips/mipsr6@blt.d: New file.
	* gas/mips/mipsr6@bltu.d: New file.
	* gas/mips/mipsr6@branch-misc-1.d: New file.
	* gas/mips/mipsr6@branch-misc-2-64.d: New file.
	* gas/mips/mipsr6@branch-misc-2pic-64.d: New file.
	* gas/mips/mipsr6@branch-misc-4-64.d: New file.
	* gas/mips/mipsr6@cache.d: New file.
	* gas/mips/mipsr6@eva.d: New file.
	* gas/mips/mipsr6@jal-svr4pic-noreorder.d: New file.
	* gas/mips/mipsr6@jal-svr4pic.d: New file.
	* gas/mips/mipsr6@ld-zero-2.d: New file.
	* gas/mips/mipsr6@ld-zero-3.d: New file.
	* gas/mips/mipsr6@loc-swap-dis.d: New file.
	* gas/mips/mipsr6@mips32-cp2.d: New file.
	* gas/mips/mipsr6@mips32-imm.d: New file.
	* gas/mips/mipsr6@mips32.d: New file.
	* gas/mips/mipsr6@mips32r2.d: New file.
	* gas/mips/mipsr6@mips4-fp.d: New file.
	* gas/mips/mipsr6@mips4-fp.l: New file.
	* gas/mips/mipsr6@mips4-fp.s: New file.
	* gas/mips/mipsr6@mips4.d: New file.
	* gas/mips/mipsr6@mips5-fp.d: New file.
	* gas/mips/mipsr6@mips5-fp.l: New file.
	* gas/mips/mipsr6@mips5-fp.s: New file.
	* gas/mips/mipsr6@mips64.d: New file.
	* gas/mips/mipsr6@msa-branch.d: New file.
	* gas/mips/mipsr6@msa.d: New file.
	* gas/mips/mipsr6@pref.d: New file.
	* gas/mips/mipsr6@relax-swap3.d: New file.
	* gas/mips/r6-64-n32.d: New file.
	* gas/mips/r6-64-n64.d: New file.
	* gas/mips/r6-64-removed.l: New file.
	* gas/mips/r6-64-removed.s: New file.
	* gas/mips/r6-64.s: New file.
	* gas/mips/r6-attr-none-double.d: New file.
	* gas/mips/r6-n32.d: New file.
	* gas/mips/r6-n64.d: New file.
	* gas/mips/r6-removed.l: New file.
	* gas/mips/r6-removed.s: New file.
	* gas/mips/r6.d: New file.
	* gas/mips/r6.s: New file.
	* gas/mips/mipsr6@mips32-dsp.d: New file.
	* gas/mips/mipsr6@mips32-dspr2.d: New file.
	* gas/mips/mipsr6@mips32r2-ill.l: New file.
	* gas/mips/mipsr6@mips32r2-ill.s: New file.
	* gas/mips/cache.s: Add r6 instruction varients.
	* gas/mips/mips.exp: Add support for the mips32r6 and mips64r6
	architectures.  Also prevent non r6 supported tests from running.
	Finally, add in support for running the new r6 tests.
	(run_dump_test_arch): Add support for mipsr6 tests.
	(run_list_test_arch): Add support for using files of the
	form arch@testname.l .

include/elf/
 	* mips.h: Add relocs: R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3,
 	R_MIPS_PC19_S2, R_MIPS_PCHI16 and R_MIPS_PCLO16.
 	(E_MIPS_ARCH_32R6): New define.
 	(E_MIPS_ARCH_64R6): New define.

include/opcode/
 	* mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
 	OP_CHECK_PREV and OP_NON_ZERO_REG.  Add descriptions for the MIPS R6
	instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
	 +I, +O, +R, +:, +\, +", +;
	(mips_check_prev_operand): New struct.
 	(INSN2_FORBIDDEN_SLOT): New define.
 	(INSN_ISA32R6): New define.
 	(INSN_ISA64R6): New define.
	(INSN_UPTO32R6): New define.
	(INSN_UPTO64R6): New define.
	(mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
 	(ISA_MIPS32R6): New define.
 	(ISA_MIPS64R6): New define.
 	(CPU_MIPS32R6): New define.
 	(CPU_MIPS64R6): New define.
 	(cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.

ld/
 	* ldmain.c (get_emulation): Add support for -mips32r6 and -mips64r6.

opcodes/
 	* mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
 	mips64r6.
 	(parse_mips_dis_option): Allow MSA and virtualization support for
 	mips64r6.
 	(mips_print_arg_state): Add fields dest_regno and seen_dest.
 	(mips_seen_register): New function.
 	(print_insn_arg): Refactored code to use mips_seen_register
	function.  Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
	OP_NON_ZERO_REG.  Changed OP_REPEAT_DEST_REG case to print out
	the register rather than aborting.
 	(print_insn_args): Add length argument.  Add code to correctly
	calculate the instruction address for pc relative instructions.
	(validate_insn_args): New static function.
 	(print_insn_mips): Prevent jalx disassembling for r6.  Use
	validate_insn_args.
	(print_insn_micromips): Use validate_insn_args.
	all the arguments are valid.
	* mips-formats.h (PREV_CHECK): New define.
 	* mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
 	-t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
 	(RD_pc): New define.
 	(FS): New define.
 	(I37): New define.
 	(I69): New define.
 	(mips_builtin_opcodes): Add MIPS R6 instructions.  Exclude recoded
 	MIPS R6 instructions from MIPS R2 instructions.
2014-09-15 12:15:55 +01:00
Jiong Wang
ee804238f0 [PATCH/AArch64] Implement LSE feature
2014-09-03  Jiong Wang  <jiong.wang@arm.com>

  gas/
	* config/tc-aarch64.c (parse_operands): Recognize PAIRREG.
	(aarch64_features): Add entry for lse extension.

  include/opcode/
	* aarch64.h (AARCH64_FEATURE_LSE): New feature added.
	(aarch64_opnd): Add AARCH64_OPND_PAIRREG.
	(aarch64_insn_class): Add lse_atomic.
	(F_LSE_SZ): New field added.
	(opcode_has_special_coder): Recognize F_LSE_SZ.

  opcode/
	* aarch64-tbl.h (QL_R4NIL): New qualifiers.
	(aarch64_feature_lse): New feature added.
	(LSE): New Added.
	(aarch64_opcode_table): New LSE instructions added.  Improve
	descriptions for ldarb/ldarh/ldar.
	(aarch64_opcode_table): Describe PAIRREG.
	* aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
	* aarch64-opc.c (fields): Add entry for F_LSE_SZ.
	(aarch64_print_operand): Recognize PAIRREG.
	(operand_general_constraint_met_p): Check reg pair constraints for CASP
	instructions.
	* aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
	(do_special_decoding): Recognize F_LSE_SZ.
	* aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.

  gas/testsuite/
	* gas/aarch64/lse-atomic.d: New.
	* gas/aarch64/lse-atomic.s: Likewise.
	* gas/aarch64/illegal-lse.d: Likewise.
	* gas/aarch64/illegal-lse.l: Likewise.
	* gas/aarch64/illegal-lse.s: Likewise.
	* gas/aarch64/diagnostic.s: Check processor feature detect for lse
	instruction.
	* gas/aarch64/diagnostic.l: Likewise.
2014-09-03 14:53:53 +01:00
DJ Delorie
599b6fb8a3 rl78.h (RL78_RELAXA_MASK): New. Relax types are enums, not bits 2014-08-26 17:01:04 -04:00
Maciej W. Rozycki
5575639b8d MIPS: Make the CODE10 operand code consistent between ISAs
This change moves the microMIPS 10-bit uninterpreted immediate code
embedded at bits 25..16 in the SYSCALL, WAIT, SDBBP and HYPCALL
instructions from `B' over to `+J' which is the operand code used in
the standard MIPS instruction set for a similar code embedded at bits
20..11, currently used by HYPCALL only in that set.

	opcodes/
	* micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
	(micromips_opcodes): Use "+J" in place of "B" for "hypcall",
	"sdbbp", "syscall" and "wait".

	include/opcode/
	* mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
	over to `+J'.
2014-08-26 13:44:34 +01:00
Nick Clifton
2d5c3743a3 Enabling the HIGH_ENTROPY_VA flag allows the operating system to use
addresses outside of the 32-bit range before memory exhaustion. This
results in a higher entropy implementation of ASLR when used with the
DYNAMIC_BASE flag.

	* include/coff/pe.h: Add HIGH_ENTROPY_VA flag
	* ld/emultempl/pep.em: Add --high-entropy-va switch
	* ld/ld.texinfo: Document the --high-entropy-va switch
2014-08-20 16:10:29 +01:00
Alan Modra
4613510308 Change ld "notice" interface for better handling of indirect symbols
The main aim of this change was to have non_ir_ref set correctly on
new indirect symbols.  I could have added a "copy" param to the "notice"
function, so that indirect symbols could be created in plugin_notice,
but it seemed cleaner to create indirect syms earlier and pass them
rather than "string" to "notice".

include/
	* bfdlink.h (struct bfd_link_callbacks <notice>): Remove "string"
	param, add "inh".
bfd/
	* coff-aux.c (coff_m68k_aux_link_add_one_symbol): Only call "notice"
	here when not calling the generic add_symbol function.  Formatting.
	Correct handling of indirect symbols.  Update notice call.
	* elflink.c (_bfd_elf_notice_as_needed): Update notice call.
	* linker.c (_bfd_generic_link_add_one_symbol): Create indirect
	symbols early.  Update notice call.  Add comments regarding weak
	symbols vs. indirect.
ld/
	* ldmain.c (notice): Update args.
	* plugin.c (plugin_notice): Likewise.  Follow warning sym link.
	Handle new indirect symbol.
2014-08-12 20:47:36 +09:30
Alan Modra
88d3f0870b missing changelog 2014-08-12 11:08:26 +09:30
Alan Modra
61f41c3c24 Fix non-plugin warning symbol handling
PR ld/16746
include/
	* bfdlink.h (struct bfd_link_info): Add lto_plugin_active.
bfd/
	* linker.c (_bfd_generic_link_add_one_symbol <WARN>): Handle
	!lto_plugin_active.
ld/
	* plugin.c (plugin_load_plugins): Set link_info.lto_plugin_active.
2014-08-12 10:31:41 +09:30