Commit graph

57 commits

Author SHA1 Message Date
Jeff Law
aabce0f46c * Makefile.in: Fix typo.
* simops.c: Add condition code handling to "sub" "subr" and
        "divh" instructions.
1996-08-30 03:07:24 +00:00
Jeff Law
0ef0eba580 * interp.c (hash): Update to be more accurate.
(lookup_hash): Call hash rather than computing the hash
        code here.
        (do_format_1_2): Handle format 1 and format 2 instructions.
        Get operands correctly and call the target function.
        (do_format_6): Get operands correctly and call the target
        function.
        (do_formats_9_10): Rough cut so shift ops will work.
        (sim_resume): Tweak to deal with format 1 and format 2
        handling in a single funtion.  Don't update the PC
        for format 3 insns.  Fix typos.
        * simops.c: Slightly reorganize.  Add condition code handling
        to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
        and "not" instructions.
        * v850_sim.h (reg_t): Registers are 32bits.
        (_state): The V850 has 32 general registers.  Add a 32bit
        psw and pc register too.  Add accessor macros
Fixing lots of stuff.  Starting to add condition code support.  Basically
check pointing the work to date.
1996-08-29 23:39:23 +00:00
Jeff Law
775533747d * simops.c: Add shift support. 1996-08-29 22:29:41 +00:00
Jeff Law
fb8eb42bd6 Fix typos in multiply and divide code. 1996-08-29 22:05:15 +00:00
Jeff Law
e98e3b2c5a * simops.c: Add multiply & divide support. Abort for system
instructions.
1996-08-29 20:08:37 +00:00
Jeff Law
1fe983dcdf * simops.c: Add logicals, mov, movhi, movea, add, addi, sub
and subr.  No condition codes yet.
1996-08-29 19:53:37 +00:00
Jeff Law
22c1c7ddea * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
gencode.c, interp.c, simops.c: Created.
So we've got something to hack on.
1996-08-29 01:06:42 +00:00