the extension part of the instruction if necessary.
(mn10300_insert_operand): Accept pointer to extension word
argument. Make insn a pointer argument too. Return type
is now void. All callers changed.
So we can correct insert operands into any instruction except those
which have 32bit operands.
alpha_macro emit field to expect a const argument, and change the
arg field to be const. Fix some spacing to follow the GNU
standard.
Fri Nov 1 10:32:03 1996 Richard Henderson <rth@tamu.edu>
* config/tc-alpha.c (md_parse_option): Add knowledge of 21164pc
(pca56) and 21264 (ev6) cpus.
(md_apply_fix): Private relocation types are now negative.
(alpha_force_relocation): Likewise.
(tc_gen_reloc): Likewise.
(emit_insn): Likewise.
(emit_ldXu): Do the right thing when the hardware can do byte insns.
(emit_stX): Likewise.
(emit_sextX): Likewise.
* config/tc-v850.c: Fix some indention problems.
(md_relax_table): Define for D9->D99 branch displacement
relaxing.
(md_convert_frag): Do something useful instead of aborting.
(md_estimate_size_before_relax): Likewise.
(md_assemble): Note if the matching instruction has a relaxable
operand. If it does, allocate frag with frag_var and don't
do any fixups.
So we can do 9bit displacement to 22bit displacement relaxing.
hacks to improve parsing of complex hi, lo, zda, etc
expressions.
(md_assemble): Don't demand and eat a trailing ')' after finding
a v850 relocation prefix. Sign extend the constant in a
BFD_RELOC_LO16 expression. Do eat a trailing ')' after a complete
operand.
(parse_cons_expression_v850): Don't eat a trailing ')' after
finding a v850 relocation prefix.
Trying to get nec's sample code to assemble. Why oh why didn't JT try
to assemble any of their code...
(TC_CONS_FIX_NEW): Likewise.
* config/tc-v850.c (parse_cons_expression_v850): New function.
(cons_fix_new_v850): Likewise.
So we can handle ".hword lo(_foo)".
(md_pcrel_from_section): New function.
* config/tc-v850.h (MD_PCREL_FROM_SECTION): Define.
So we don't screw up pc-relative jumps/calls from one section
into another section within the same .o file.
Fixes global ctors/dtors to work with DECL_ONE_ONLY stuff.
assembler now always builds a symbol table, which means that
objdump will no longer report `No symbols in FILE'. Change the
expected output accordingly.
* config/obj-elf.c (elf_frob_file): Move ECOFF debug processing to ...
(elf_frob_file_after_relocs): ... here. New function.
* config/obj-elf.h (obj_from_file_after_relocs): New macro.
* write.c (write_object_file): Call *frob_after_relocs after the
call to write_relocs.
* config/tc-alpha.c: Use new BFD_RELOC_ALPHA_ELF_LITERAL reloc.
* config/tc-alpha.c (load_expression): Don't SET_VALUE on the section
symbol, as this messes up linking. Instead, expand the recursive call
inline and change up the appropriate bits to get the 0x8000 offset
in the reloc addend.
with a single 8bit or 16bit immediate operand.
We should correctly assemble just about everything except opcodes with:
multiple immediate operands,
3 register operands,
really weird stuff
instructions. Add missing test in do_mov1.
* gas/mn10300/mov1.s: Add missing test.
We should now assemble just about anything without any
immediate operands.
