Commit graph

924 commits

Author SHA1 Message Date
Ian Lance Taylor
bfb25a00c4 From Peter Thiemann <thiemann@informatik.uni-tuebingen.de>:
* ppc-opc.c (insert_mbe): Handle wrapping bitmasks.
	(extract_mbe): Likewise.
1998-08-12 18:02:01 +00:00
Jeff Law
75fb9c4c3e * m10300-opc.c: Fix typo in udf20 .. udf25 instruction opcodes. 1998-08-12 17:47:45 +00:00
Jeff Law
ffd95d63ec * m10300-opc.c: First cut at UDF instructions. 1998-08-12 17:12:31 +00:00
Ken Raeburn
3d759c53c9 sanitize-vr5400 -> sanitize-cygnus, for 98r2 1998-08-12 10:50:35 +00:00
Catherine Moore
420cfe32ad Fix indentation. 1998-08-10 17:54:33 +00:00
Catherine Moore
0ff7faafe6 * arm-dis.c (print_insn_big_arm): Check for thumb symbol
attributes.
        (print_insn_little_arm): Likewise.
1998-08-10 01:27:05 +00:00
Doug Evans
c2009f4a31 Move all global state data into opcode table struct, and treat
opcode table as something that is "opened/closed".
	* cgen-asm.c (all fns): New first arg of opcode table descriptor.
	(cgen_asm_init): Delete.
	(cgen_set_parse_operand_fn): New function.
	* cgen-dis.c (all fns): New first arg of opcode table descriptor.
	(cgen_dis_init): Delete.
	* cgen-opc.c (all fns): New first arg of opcode table descriptor.
	(cgen_current_{opcode_table_mach,endian}): Delete.
	* cgen-asm.in (all fns): New first arg of opcode table descriptor.
	* cgen-dis.in (all fns): Ditto.
	* cgen-opc.in (all fns): Ditto.
	* m32r-asm.c,m32r-dis.c,m32r-opc.c,m32r-opc.h: Regenerate.

	* cgen-asm.in (parse_insn_normal): Ignore case in mnemonics.

	* cgen-dis.in (print_normal): Split into two.
	(print_address): New function.
	(extract_insn_normal): Clarify insn_value arg.
	(print_int_insn): Renamed from print_insn.
	(print_insn): New arg.
	(print_insn_@arch@): Open opcode table if not already done so.
	Move reading of insn into print_insn.
1998-08-03 19:56:43 +00:00
Frank Ch. Eigler
98c5616ad4 * Fix for PR 16389, brought over from d30v branch
Thu Jul 30 21:41:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
	* d30v-opc.c (d30v_opcode_table): Add new "LKR" flag to some
	instructions.
1998-07-30 19:38:15 +00:00
Jeff Law
9509185b58 * m10300-opc.c: Add entries for "no_match_operands" field in
the opcode table.
1998-07-28 17:01:21 +00:00
Jeff Law
7210606cf0 * m10300-dis.c: Do not emit a comma before a PLUS (autoincrement)
operand.
1998-07-24 21:23:35 +00:00
Doug Evans
2e6dfccc09 * m32r-asm.c,m32r-opc.c: Regenerate (-Wall cleanups). 1998-07-24 18:45:13 +00:00
Ian Lance Taylor
faec70d605 remove d30v sanitization 1998-07-24 03:58:14 +00:00
Jeff Law
47254a1631 * m10300-opc.c: Add DSP autoincrement memory loads/stores. 1998-07-23 15:51:24 +00:00
Jeff Law
b0b57954c5 * m10300-opc.c: Add autoincrement memory loads/stores. 1998-07-23 15:22:17 +00:00
Jeff Law
faac4767b1 * mips-opc.c: Make phmadh and phmsbh synonyms for phmaddh and
phmsubh respectively.
pr16537
1998-07-22 23:07:38 +00:00
Doug Evans
b00ea55caf regenerate, get displacement operand shifts right 1998-07-21 23:46:56 +00:00
Doug Evans
0cc2fbf340 tweak 1998-07-21 21:08:03 +00:00
Doug Evans
fbc8134df6 * cgen-opc.in (@arch@_cgen_lookup_insn): Update call to
CGEN_EXTRACT_FN.
	(@arch@_cgen_get_insn_operands): @arch@_cgen_get_operand renamed to
	@arch_cgen_get_int_operand.
	* cgen-asm.in (insert_insn_normal): New arg `pc', callers updated.
	Update call to @arch@_cgen_insert_operand.
	(@arch@_cgen_assemble_insn): Update call to CGEN_INSERT_FN.
	* cgen-dis.in (print_normal): Delete use of CGEN_PCREL_OFFSET.
	(extract_insn_normal): New arg `pc', callers updated.
	Update call to @arch@_cgen_extract_operand.
	(print_insn): Update call to CGEN_EXTRACT_FN.
	* m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c: Regenerate.
1998-07-21 20:59:23 +00:00
Jeff Law
f10a9bdead * m10300-opc.c (mn10300_opcodes): Fix opcode for 4 operand "mul" and
"mulu".
1998-07-17 00:06:55 +00:00
Ian Lance Taylor
33b111fa62 Mon Jul 13 14:53:59 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
* i386-dis.c (ckprefix): Handle fwait specially only when it isn't
	the first prefix.
	(dofloat): Correct test for fnstsw.  Print `fnstsw %ax' rather
	than `fnstsw %eax'.
	(OP_J): Remove unnecessary subtraction when 16-bit displacement
	will be masked later.
1998-07-13 18:54:43 +00:00
Jeff Law
228695a5d8 * m10300-opc.c (mn10300_opcodes): Fix destination operand for 3 operand
instructions.
1998-07-11 05:12:03 +00:00
Jeff Law
ccd5eb2da9 * m10300-dis.c (disassemble): When printing RREGs and XRREGs, map
from raw register #s to symbolic names to make debugging easier.
1998-07-08 17:38:15 +00:00
Doug Evans
1b9ec81e15 * m32r-opc.h (CGEN_MIN_INSN_SIZE): New #define. 1998-07-03 00:11:25 +00:00
Doug Evans
0499462e76 * Makefile.am (CGENDIR): Set via configure.
(CGEN): New variable.
	(CGENFILES): object.scm renamed to cos.scm.
	(run-cgen): Renamed from cgen.  stamp file renamed to stamp-$prefix.
	(stamp-m32r): Pass prefix to run-cgen.
	* Makefile.in: Regenerate.
	* cgen-asm.in: @arch@-opc.h renamed to @prefix@-opc.h.
	* cgen-dis.in: Ditto.
	* cgen-opc.in: Ditto.
	* cgen.sh: New args cgen,prefix.  Delete args scheme,schemeflags.
	* configure.in: AC_SUBST cgen,cgendir.  No longer look for guile.
	* configure: Regenerate.
	* m32r-asm.c,m32r-dis.c,m32r-opc.c,m32r-opc.h: Regenerate.
1998-07-01 23:31:27 +00:00
Doug Evans
3c88e9a988 * dvp-opc.c (DVP_OPERAND_RELOC_11_S4): Temporarily back out
the DVP_OPERAND_RELOC_11_S4 relocation.
	* dvp-opc.c (LIMM11, LUIMM15): New symbol types
	DVP_OPERAND_RELOC_U15_S3 and DVP_OPERAND_RELOC_11_S4 to allow labels to
	be used as immediate values.
1998-07-01 19:34:55 +00:00
Nick Clifton
e38a77d3ca Replace object.scm with cos.scm 1998-07-01 16:42:36 +00:00
Jeff Law
ff7a9bc9b4 * m10300-opc.c: Reorder "movbu" and "movhu" instructions too.
Why oh why didn't they take our advice about register prefixing.  It would
have avoided the ambigious syntax issues.  Sigh.
1998-06-30 16:04:44 +00:00
Jeff Law
a841b47c4b * m10300-opc.c: Reorder more instructions so that we do not
accidentally match a mn10300 instruction when we really
        wanted an am33 instruction.
1998-06-29 20:57:25 +00:00
Jeff Law
0c9b3858c1 * m10300-dis.c: Only recognize instructions from the currently
selected machine.
        * m10300-opc.c: Add field indicating the particular variant of
        the mn10300 each instruction is available on.
1998-06-26 17:12:10 +00:00
Ian Lance Taylor
69ad8cac12 * configure.in: For bfd_vax_arch, build vax-dis.lo.
* Makefile.am: Rebuild dependencies.
 	(CFILES): Add vax-dis.c.
	(ALL_MACHINES): Add vax-dis.lo.
	* aclocal.m4: Rebuild with current libtool.
	* configure, Makefile.in: Rebuild.

Fri Jun 26 12:03:20 1998  Klaus Kaempf  <kkaempf@progis.de>

	* vax-dis.c: New file, from work by Pauline Middelink
	<middelin@polyware.iaf.nl>.
	* disassemble.c (ARCH_vax): Define if ARCH_all.
	(disassembler): Add case for ARCH_vax.
	* makefile.vms: Support compilation on vms/vax.
1998-06-26 16:08:02 +00:00
Jeff Law
1c2a961d56 * m10300-dis.c (print_insn_mn10300): 0xf7 opcode prefix specifies
4 byte instructions.
        (disassemble): Correctly handle FMT_D10 instructions.
1998-06-24 19:04:06 +00:00
Jeff Law
59557be25d * mn10300-opc.c (mn10300_opcodes): Fix typo in IMM24 versions of the
am33 shift instructions.
1998-06-24 19:02:27 +00:00
Jeff Law
c29d7797d2 * mn10300-dis.c (print_insn_mn10300): 0xf9 opcode prefix specifies
3 byte instructions.
        (disassemble): Handle new instruction formats FMT_D6, FMT_D7, FMT_D8
        FMT_D9 and FMT_D10.  Handle various new opcode flags for the am33.
1998-06-24 16:00:43 +00:00
Jeff Law
4da06098ff * mn10300-opc.c (IMM32_HIGH8_MEM): New operand type.
(mn10300_opcodes): Reorder so as to try and select opcodes from
        the core chip when multiple alternatives exist.  Change several
        am33 instructions to use IMM32_HIGH8_MEM.  Fix typos in "mac" and
        "macbu" instructions.  Fix typos in a couple DSP instructions too.
1998-06-24 15:56:40 +00:00
Mark Alexander
42fc298244 * m10200-dis.c (print_insn_mn10200): Fix various non-portabilities
related to sign extension and the size of ints.
1998-06-24 02:49:07 +00:00
Jeff Law
8b727aa4d3 * m10300-opc.c: Support one operand "asr", "lsr" and "asl"
instructions.  Support (sp) addressing mode by expanding it into
        (0,sp).
1998-06-23 17:01:44 +00:00
Jeff Law
c5a6e18b2e * m10300-opc.c: Support 4 byte DSP instructions. 1998-06-22 19:38:35 +00:00
Jeff Law
d7f444fd7a * m10300-opc.c: Support 6 and 7 byte am33 instructions. 1998-06-19 22:49:43 +00:00
Mark Alexander
7b61b0945f * m10200-dis.c (print_insn_mn10200): Recognize 'break' pseudo-op. 1998-06-19 16:19:12 +00:00
Jeff Law
b17af7f6ef * m10300-opc.c: Support for 3 byte and 4 byte extended instructions
found on the mn10300.
1998-06-19 15:45:13 +00:00
Ian Lance Taylor
4b035e8ea9 formatting fixes 1998-06-19 14:43:45 +00:00
Ulrich Drepper
d2a24cee53 Update. 1998-06-19 01:58:48 +00:00
John Metzler
7648738c81 Fix compile errors in set_mips_isa_type 1998-06-18 22:47:43 +00:00
John Metzler
8b023c48d5 *** empty log message *** 1998-06-18 21:08:52 +00:00
Jeff Law
a145a5ac84 Rework ChangeLog entry to avoid mentioning vr5400 in a r5900 entry. 1998-06-18 19:14:20 +00:00
John Metzler
20af011086 * mips-dis.c (print_insn_little_mips): Previously, instruction
printing references the symbol table to determine whether the
 	instruction resides in a block regular instructions or mips16
 	instructions. However, when the disassembler gets used in other
 	environments where the symbol table is not present, we no longer
 	rely in the symbol table, rather, use the low bit of the
 	instructions address to guess. There should be no change for usage
 	of the disassembler in host based programse, gdb ,objdump.
	(print_insn_big_mips): ditto.
	(print_insn_mips): ditto
1998-06-18 17:30:26 +00:00
Ian Lance Taylor
d845999e69 tipo 1998-06-18 16:20:45 +00:00
Jeff Law
9eb61c7c61 start-sanitize-am33
* m10300-opc.c (USP, SSP, MSP, PC, IMM4, EPSW, RN0, RM1): New
        operands for the am33.
        (mn10300_opcodes): Add new instructions from the am33.
end-sanitize-am33
        * m10300-opc.c (mn10300_opcodes): Change opcode for "syscall".

Snapshot current work.
1998-06-17 23:54:25 +00:00
Ian Lance Taylor
e6db632454 Tue Jun 16 13:10:51 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
* i386-dis.c (index16): Add '%' to register names.  Use ','
	instead of '+'.
1998-06-16 17:11:47 +00:00
Ian Lance Taylor
5f90dab190 Sat Jun 13 11:33:55 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
* i386-dis.c: Don't print opcode suffix when we can figure out the
	size (and gas can!) by register operands, or from the default
	size.
	(putop): Handle 'A', 'B', 'L', 'P', 'Q', 'R' macros.  Rename 'C'
	macro to 'E'.
	(dis386, dis386_twobyte, grps): Use new suffix macros.
	(dis386): Correct imul Ib to imul sIb.  Change jnl to jge to be
	consistent.  Add suffix for call, jmp, lcall, ljmp, iret.  Reverse
	order of cmps operands to agree with Intel docs.  Correct operand
	of aad and aam (Ib -> sIb).  Change ud2b from 0fb8 to 0fb9 to
	agree with Intel docs.
	(print_insn_x86): Print orphan fwait before other prefixes.
	Return correct byte count for orphan fwait with prefixes.  Don't
	print `bound' operands in reverse order.
	(ckprefix): Stop accumulating prefixes if we get fwait.
	(OP_DIR): Print `$' before Ap operands of ljmp, lcall.
1998-06-13 15:38:32 +00:00