Andrew Cagney
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cd0d873d0f
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Preliminary suport for xor-endian suport in core module.
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1997-05-23 09:19:43 +00:00 |
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Andrew Cagney
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b526378484
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Incorrect test for zero-r0 code gen.
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1997-05-23 02:01:04 +00:00 |
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Andrew Cagney
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37a684b84d
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o Make tic80 insn file more `cache ready'
o Have igen always zero r0 instead of constantly checking if
the designated register is r0.
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1997-05-16 03:27:40 +00:00 |
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Michael Meissner
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d23af88239
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Fix problems -Wall found
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1997-05-05 18:16:10 +00:00 |
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Andrew Cagney
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15c1649391
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TIc80 simulator checkpoint - runs 3 instructions - trap, addu, br.a.
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1997-04-22 17:46:07 +00:00 |
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