Jeff Law
ba853302f2
* interp.c: Remove various debugging printfs.
1996-08-30 16:42:49 +00:00
Jeff Law
0e4ccc58f2
* simops.c: Fix satadd, satsub boundary case handling.
1996-08-30 16:41:39 +00:00
Jeff Law
83fc3bac9f
* interp.c (hash): Fix.
...
* interp.c (do_format_8): Get operands correctly and
call the target function.
* simops.c: Rough cut at "clr1", "not1", "set1", and "tst1".
1996-08-30 16:35:10 +00:00
Jeff Law
3cb6bf7818
* interp.c (do_format_4): Get operands correctly and
...
call the target function.
* simops.c: Rough cut at "sld.b", "sld.h", "sld.w", "sst.b",
"sst.h", and "sst.w".
1996-08-30 05:49:07 +00:00
Jeff Law
28647e4c0c
* v850_sim.h: The V850 doesn't have split I&D spaces. Change
...
accordingly. Remove many unused definitions.
* interp.c: The V850 doesn't have split I&D spaces. Change
accordingly.
(get_longlong, get_longword, get_word): Deleted.
(write_longlong, write_longword, write_word): Deleted.
(get_operands): Deleted.
(get_byte, get_half, get_word): New functions.
(put_byte, put_half, put_word): New functions.
* simops.c: Remove unused functions. Rough cut at
"ld.b", "ld.h", "ld.w", "st.b", "st.h", "st.w" insns.
1996-08-30 05:41:10 +00:00
Jeff Law
614f1c68ed
* v850_sim.h (struct _state): Remove "psw" field. Add
...
"sregs" field.
(PSW): Remove bogus definition.
* simops.c: Change condition code handling to use the psw
register within the sregs array. Handle "ldsr" and "stsr".
1996-08-30 05:09:08 +00:00
Jeff Law
dca41ba76b
* simops.c: Handle "satadd", "satsub", "satsubi", "satsubr".
1996-08-30 04:59:02 +00:00
Jeff Law
e9b6cbaca5
* interp.c (do_format_5): Get operands correctly and
...
call the target function.
(sim_resume): Don't do a PC update for format 5 instructions.
* simops.c: Handle "jarl" and "jmp" instructions.
1996-08-30 04:27:48 +00:00
Jeff Law
3095b8dfc5
* simops.c: Fix minor typos. Handle "cmp", "setf", "tst"
...
"di", and "ei" instructions correctly.
1996-08-30 04:11:32 +00:00
Jeff Law
2108e86459
* interp.c (do_format_3): Get operands correctly and call
...
the target function.
* simops.c: Handle bCC instructions.
1996-08-30 03:48:13 +00:00
Jeff Law
35404c7d07
* simops.c: Add condition code handling to shift insns.
...
Fix minor typos in condition code handling for other insns.
1996-08-30 03:23:36 +00:00
Jeff Law
aabce0f46c
* Makefile.in: Fix typo.
...
* simops.c: Add condition code handling to "sub" "subr" and
"divh" instructions.
1996-08-30 03:07:24 +00:00
Jeff Law
0ef0eba580
* interp.c (hash): Update to be more accurate.
...
(lookup_hash): Call hash rather than computing the hash
code here.
(do_format_1_2): Handle format 1 and format 2 instructions.
Get operands correctly and call the target function.
(do_format_6): Get operands correctly and call the target
function.
(do_formats_9_10): Rough cut so shift ops will work.
(sim_resume): Tweak to deal with format 1 and format 2
handling in a single funtion. Don't update the PC
for format 3 insns. Fix typos.
* simops.c: Slightly reorganize. Add condition code handling
to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
and "not" instructions.
* v850_sim.h (reg_t): Registers are 32bits.
(_state): The V850 has 32 general registers. Add a 32bit
psw and pc register too. Add accessor macros
Fixing lots of stuff. Starting to add condition code support. Basically
check pointing the work to date.
1996-08-29 23:39:23 +00:00
Jeff Law
775533747d
* simops.c: Add shift support.
1996-08-29 22:29:41 +00:00
Jeff Law
fb8eb42bd6
Fix typos in multiply and divide code.
1996-08-29 22:05:15 +00:00
Jeff Law
e98e3b2c5a
* simops.c: Add multiply & divide support. Abort for system
...
instructions.
1996-08-29 20:08:37 +00:00
Jeff Law
1fe983dcdf
* simops.c: Add logicals, mov, movhi, movea, add, addi, sub
...
and subr. No condition codes yet.
1996-08-29 19:53:37 +00:00
Jeff Law
22c1c7ddea
* ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
...
gencode.c, interp.c, simops.c: Created.
So we've got something to hack on.
1996-08-29 01:06:42 +00:00
