darkkirb/old-cross-binutils
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22 commits

Author SHA1 Message Date
Doug Evans
a4b44a2b08 * sim-core.c (sim_core_signal): Use sim_stopped instead of 
sim_signalled.
 1997-11-19 08:03:53 +00:00
Doug Evans
1ebc7e0e24 * sim-signal.c, sim-signal.h: New files. 
* Make-common.in (sim-signal.o): Add rule for.
	(SIM_NEW_COMMON_OBJS): Add sim-signal.o.
	* sim-abort.c: Don't include <signal.h>.
	* sim-basics.h: #include "sim-signal.h".
	* sim-break.c: Don't include <signal.h>.
	(sim_handle_breakpoint): Replace SIGTRAP with SIM_SIGTRAP.
	* sim-core.c: Don't include <signal.h>.
	(SIGBUS): Delete definition.
	(sim_core_signal): Replace SIGSEGV,SIGBUS with SIM_SIGSEGV,SIM_SIGBUS.
	* sim-engine.c: Don't include <signal.h>.
	(sim_engine_abort): Replace SIGABRT with SIM_SIGABRT.
	* sim-reason.c (sim_stop_reason): Call sim_signal_to_host.
	* sim-resume.c: Don't include <signal.h>.
	(SIGTRAP): Delete definition.
	(has_stepped): Replace SIGTRAP with SIM_SIGTRAP.
	* sim-stop.c: Don't include <signal.h>.
	(control_c_simulation): Replace SIGINT with SIM_SIGINT.
	* sim-watch.c: Don't include <signal.h>.
	(handle_watchpoint): Replace SIGINT with SIM_SIGINT.
 1997-11-19 08:00:37 +00:00
Doug Evans
340d8e209e * sim-core.c (sim_core_signal): Use CIA_ADDR to fetch value. 1997-11-18 23:59:29 +00:00
Doug Evans
cf02c13ce2 (sim_core_signal): Add missing "\n" in message. 
Forgot to check in yesterday.
 1997-11-14 21:52:04 +00:00
Andrew Cagney
63be8febf7 Rewrite the MIPS simulator's memory model so that it uses the generic 
common/sim-core.

Add support for 3, 5, 6, 7 byte transfers to sim core.
 1997-11-05 08:17:26 +00:00
Andrew Cagney
fcc86d82f7 Make memory regions layered (just like existing device regions) so 
that overlapping regions can be defined.
Allow the layer (level) of a memory region to be specified as part of
an address parameter to memory options.
Update simulators.
 1997-10-31 08:49:10 +00:00
Andrew Cagney
a86809d323 Implement sim_core_{read,write}_word using sim_core_{read,write}_<N>. 1997-10-28 02:13:09 +00:00
Andrew Cagney
f45dd42b32 Add 128 bit transfers to sim core. 1997-10-27 03:00:12 +00:00
Andrew Cagney
fd89abc204 Handle core regions which start at a poorly aligned address. 1997-10-14 23:45:52 +00:00
Felix Lee
31dda65aff * sim-core.h (sim_cpu_core): [WITH_XOR_ENDIAN + 1], to avoid 
illegal zero-sized array.
	* sim-core.c (sim_core_xor_read_buffer): same.
 1997-09-10 04:46:37 +00:00
Andrew Cagney
1bba340afe Redo watchpoint code so that it target can specify interrupt names. 
Replace v850 interrupt code with this common watchpoint code.
Other minor fixes to core.
 1997-09-05 08:16:23 +00:00
Andrew Cagney
30efae3acd Define SIGNED64 and UNSIGNED64 macros - handle MSC/GCC LL issue. 1997-09-05 00:30:38 +00:00
Andrew Cagney
a34abff813 o Add modulo argument to sim_core_attach 
o	Add sim-memopt module - memory option processing.
 1997-09-04 03:47:39 +00:00
Andrew Cagney
80c651f02d Stanify error reporting memory overlaps. 1997-09-03 04:06:27 +00:00
Andrew Cagney
f90b720ba1 Passify GCC. Convert 0x0LL to something more portable in the FP code. 1997-08-30 00:02:19 +00:00
Andrew Cagney
cd0d873d0f Preliminary suport for xor-endian suport in core module. 1997-05-23 09:19:43 +00:00
Andrew Cagney
50a2a69182 Watchpoint interface. 1997-05-21 06:54:13 +00:00
Andrew Cagney
c445af5a2b c80 simulator fixes. 1997-05-12 04:57:49 +00:00
Andrew Cagney
7a418800c1 Start of implementation of a distributed (between processors) 
simulator core object.
 1997-05-05 13:21:04 +00:00
Andrew Cagney
1fe052808a Update devo version of m32r sim to build with recent sim/common changes. 1997-05-02 08:41:15 +00:00
David Edelsohn
c967f1874a * Makefile.in (sim-options_h): Define. 
(sim-{module,options,trace,profile,utils}.o): Clean up dependencies.
	(sim-model.o): Add new rule.
	(cgen-{scache,trace,utils}.o): Add new rules.
	* aclocal.m4 (SIM_AC_OPTION_{SCACHE,DEFAULT_MODEL}): Add.
	* cgen-scache.c (scache_print_profile): Change `sd' arg to `cpu'.
	Indent output by 2 spaces.
	* cgen-scache.h (scache_print_profile): Update.
	* cgen-trace.c (trace_insn_fini): Indent output by 2 spaces.
	Use trace_printf, not fprintf.
	(trace_extract): Use trace_printf, not cgen_trace_printf.
	* genmloop.sh (!FAST case): Increment `insn_count'.
	* sim-base.h (sim_state_base): Only include scache_size if WITH_SCACHE.
	(sim_cpu_base): Rename member `sd' to `state' to be consistent with
	access macro's name.
	* sim-core.c (sim_core_init): Use EXTERN_SIM_CORE to define it.
	Change return type to SIM_RC.
	(sim_core_{install,uninstall}): New functions.
	* sim-core.h (sim_core_{install,uninstall}): Declare.
	(sim_core_init): Use EXTERN_SIM_CORE to define it.
	Change return type to SIM_RC.
	* sim-model.h (models,machs,model_install): Declare.
	* sim-module.c (modules): Add scache_install, model_install.
	(sim_post_argv_init): Set cpu->state backlinks.
	* sim-options.c (standard_options): Delete --simcache-size,--max-insns.
	(standard_option_handler): Likewise.
	* sim-profile.c (PROFILE_{HISTOGRAM,LABEL}_WIDTH): Move to
	sim-profile.h.
	(*): Assume ANSI C.
	(profile_options): Delete --profile-simcache.
	(profile_option_handler): Likewise.
	(profile_print_insn): Change `sd' arg to `cpu'.  Indent output 2
	spaces.
	(profile_print_{memory,model}): Likewise.
	(profile_print_simcache): Delete.
	(profile_print_speed): New function.
	(profile_print): Rewrite.
	* sim-profile.h (PROFILE_scache): Renamed from PROFILE_simcache.
	(WITH_PROFILE_SCACHE_P): Renamed from WITH_PROFILE_SIMCACHE_P.
	(PROFILE_DATA): Delete members simcache_{hits,misses}.
	(PROFILE_COUNT_SIMCACHE_{HIT,MISS}): Delete.
	(PROFILE_{CALLBACK,CPU_CALLBACK}): New types.
	(profile_print): Update prototype.
 1997-05-01 18:05:37 +00:00
Andrew Cagney
f2de7dfd8c Add a number of per-simulator options: hostendian, endian, inline, warnings. 
Rename *-n.h files to be dos compatible
 1997-03-14 15:13:58 +00:00