* config/tc-ppc.c (ppc_cleanup): Do something only if format
is ELF.
(ppc_apuinfo_section_add): Define only if format is ELF.
(md_assemble): Emit APUinfo section only if format is ELF.
Fix formatting.
From matthew green <mrg@redhat.com>
* config/tc-ppc.c (PPC_OPCODE_CLASSIC): Enable this everywhere
PPC_OPCODE_PPC is, except for BookE architectures.
(md_parse_option): Add support for -mspe.
(md_show_usage): Add -mspe.
(md_parse_option): Add support for -me500 and
-me500x2 to generate code for Motorola e500 core complex.
(md_show_usage): Add -me500 and -me500x2.
(PPC_APUINFO_ISEL, PPC_APUINFO_PMR, PPC_APUINFO_RFMCI,
PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE, PPC_APUINFO_EFS,
PPC_APUINFO_BRLOCK): New macros.
(ppc_cleanup): New function.
(ppc_apuinfo_section_add): New function.
(APUID): New macro.
(md_assemble): Collect info and write the APUinfo section.
* config/tc-ppc.h (md_cleanup): Define.
(ppc_cleanup): Export.
(ELF_TC_SPECIAL_SECTIONS): Add .PPC.EMB.apuinfo section.
(ppc_cpu): Make it unsigned long to agree with struct powerpc_opcode
flags.
(ppc_size): Delete.
(ppc_xcoff64): Rename to ppc_obj64.
(md_parse_option <m>): Encode old ppc_size value in ppc_cpu.
(ppc_set_cpu): Set PPC_OPCODE_32 too.
(ppc_arch): Use ppc_obj64 instead of ppc_size to select bfd_mach_ppc64
or bfd_mach_ppc.
(ppc_target_format): Use ppc_obj64 to select format.
(md_begin): Adjust for PPC_OPCODE_32/64 in ppc_cpu.
(ppc_insert_operand): Use ppc_obj64 instead of ppc_size.
(ppc_elf_suffix): Likewise. Don't depend on BFD_DEFAULT_TARGET_SIZE.
(tc_frob_symbol): Likewise.
(md_assemble): Use ppc_obj64 instead of ppc_size. Don't depend on
BFD_DEFAULT_TARGET_SIZE.
(ppc_tc): Likewise.
(ppc_is_toc_sym): Likewise.
(md_apply_fix3): Likewise.
* config/tc-ppc.h (TC_FORCE_RELOCATION): Don't depend on
BFD_DEFAULT_TARGET_SIZE.
(ELF_TC_SPECIAL_SECTIONS): Likewise.
(tc_frob_symbol): Likewise.
* config/tc-ppc.c (md_parse_option): BookE is not Motorola specific.
[include/opcode/ChangeLog]
* ppc.h (PPC_OPCODE_BOOKE): BookE is not Motorola specific.
(PPC_OPCODE_BOOKE64): Likewise.
(ppc_size): Select PPC_OPCODE_64 if 64 bit.
(md_begin): Don't set ppc_size here.
(ppc_target_format): Test ppc_size as well as BFD_DEFAULT_TARGET_SIZE.
(md_shortopts): Constify.
(md_longopts): Likewise.
(md_longopts_size): Likewise.
(ppc_elf_suffix): Only allow 64-bit relocs when ppc_size specifies
64-bit opcodes.
(ppc_machine): Explain why this function is a nop.
* config/tc-ppc.c (md_parse_option): New -m7410, -m7450 and -m7455
flags, equivalent to -m7400. New -maltivec to enable AltiVec
instructions. New -mbook64 and -mbooke/-mbooke32 flags to enable
64-bit and 32-bit BookE support, respectively. Change -m403 and
-m405 to set PPC403 option.
(md_show_usage): Adjust for new options.
* doc/all.texi: Set PPC.
* doc/as.texinfo: Add PPC support and pull in c-ppc.texi.
* doc/c-ppc.texi: New file.
* doc/Makefile.am (CPU_DOCS): Add c-ppc.texi.
* doc/Makefile.in: Regenerate.
[gas/testsuite/ChangeLog]
* gas/ppc/booke.s: New test for Motorola BookE.
* gas/ppc/booke.d: New file.
* gas/ppc/ppc.exp: Test booke.s.
[include/opcode/ChangeLog]
* ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_403): New opcode flags for
BookE and PowerPC403 instructions.
[opcodes/ChangeLog]
* ppc-opc.c (insert_de, extract_de, insert_des, extract_des): New
instruction field instruction/extraction functions for new BookE
DE form instructions.
(CT): New macro for CT field in an X form instruction.
(DE, DES, DEO, DE_MASK): New macros for DE/DES fields in DE form
instructions.
(PPC64): Don't include PPC_OPCODE_PPC.
(403): New opcode macro for PPC403 processors.
(BOOKE): New opcode macro for BookE processors.
(bce, bcel, bcea, bcela, bclre, bclrel: New BookE instructions.
(bcctre, bcctrel, be, bel, bea, bela, icbt, icbte, lwzxe): Likewise.
(dcbste, lwzuxe, luxe, dcbfe, lbzxe, lwarxe, lbzuxe): Likewise.
(stwcxe, stwxe, stxe, stwuxe, stuxe, stbxe, dcbtste, stbuxe): Likewise.
(mfapidi, dcbte, lhzxe, lhzuxe, lhaxe, lhauxe, subfe64): Likewise.
(subfeo64, adde64, addeo64, sthxe, sthuxe, subfze64): Likewise.
(subfzeo64, addze64, addzeo64, dcbie, subfme64, subfmeo64): Likewise.
(addme64, addmeo64, stdcxe., mcrxr64, lwbrxe, lfsxe, lfsuxe): Likewise.
(lfdxe, lfduxe, stwbrxe, stfsxe, stfsuxe, stfdxe, dcbae): Likewise.
(stfduxe, tlbivax, tlbivaxe, lhbrxe, ldxe, lduxe, tlbsx): Likewise.
(tlbsxe, sthbrxe, stdxe, stduxe, icbie, stfiwxe, dcbze, lbze): Likewise.
(lbzue, ldue, lhze, lhzue, lhae, lhaue, lwze, lwzue): Likewise.
(stbe, stbue, sthe, sthue, stwe, stwue, lfse, lfsue, lfde): Likewise.
(lfdue, stde, stdue, stfse, stfsue, stfde, stfdue): Likewise.
* ppc-dis.c (print_insn_big_powerpc, print_insn_little_powerpc): Look
for a disassembler option of `booke', `booke32' or `booke64' to enable
BookE support in the disassembler.
* configure: Regenerate.
* config/tc-ppc.c (PPC_LO, PPC_HI, PPC_HA, PPC_HIGHER,
PPC_HIGHERA, PPC_HIGHEST, PPC_HIGHESTA, SEX16): New macros.
(md_assemble): Use them.
(ppc_machine): Support stub for ELF64 as well as XCOFF.
(md_pseudo_table): Add "llong", "quad".
(md_parse_option): Match default_cpu of powerpc*.
(ppc_arch): Likewise.
(ppc_subseg_align): Only for OBJ_XCOFF.
(ppc_target_format): Return elf64-powerpc strings for 64 bit ELF.
(md_begin): Select PPC_OPCODE_64 for 64 bit.
(ppc_insert_operand): Don't bother testing 'file' before calling
as_bad_where. Use as_bad_where for operand->insert errors.
(mapping): Add ELF64 relocation modifiers.
(ppc_elf_suffix): Replace symbol on BFD_RELOC_PPC64_TOC reloc
expressions with abs_symbol.
(ppc_elf_cons): Correct offset for little endian targets.
(ppc_elf_frob_symbol): New.
(md_assemble): Add support for 64 bit ELF relocs.
(ppc_tc): Ensure 8 byte alignment when 64 bit.
(ppc_is_toc_sym): Only define for OBJ_XCOFF and OBJ_ELF. Match
".toc" section for 64 bit ELF.
(ppc_fix_adjustable): New. Macro body moved from tc-ppc.h.
(md_apply_fix3): Silence warning with ATTRIBUTE_UNUSED. Only do
the ppc_is_toc_sym check for OBJ_XCOFF and OBJ_ELF. For 64 bit,
use BFD_RELOC_PPC64_TOC16_DS instead of BFD_RELOC_PPC_TOC16.
Expand on comments, error message. Add support for 64 bit relocs,
and use PPC_HI etc. macros.
* config/tc-ppc.h (MAX_MEM_FOR_RS_ALIGN_CODE): Define.
(HANDLE_ALIGN): Define to generate nops in code sections rather
than zeros.
(TC_FORCE_RELOCATION): Force for BFD_RELOC_PPC64_TOC.
(ELF_TC_SPECIAL_SECTIONS): Add 64 bit ELF sections.
(tc_fix_adjustable): Move body of macro to tc-ppc.c.
(ppc_fix_adjustable): Declare.
(tc_frob_symbol): Define.
(ppc_elf_frob_symbol): Declare.
2000-08-30 Mark Hatle <mhatle@mvista.com>
* config/tc-ppc.c (md_parse_option): Recognize -m405.
In src/opcodes/ChangeLog:
2000-08-30 Mark Hatle <mhatle@mvista.com>
* ppc-opc.c Add XTLB macro for a few PPC 4xx extended mnemonics.
(powerpc_opcodes): Add table entries for PPC 405 instructions.
Changed rfci, icbt, mfdcr, dccci, mtdcr, iccci from PPC to PPC403
instructions.
Added extended mnemonic mftbl as defined in the 405GP manual
for all PPCs.
