2004-11-25 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (optimize_imm): Adjust immediates to only those
permissible for the selected instruction suffix.
(process_suffix): For DefaultSize instructions, suppressing the
guessing of a 'q' suffix if the instruction doesn't support it is
pointless, because only an 'l' suffix can be guessed in this place.
gas/testsuite/
2004-11-25 Jan Beulich <jbeulich@novell.com>
* gas/i386/x86-64-inval.[sl]: Remove sahf/lahf.
include/opcode/
2004-11-25 Jan Beulich <jbeulich@novell.com>
* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
to/from test registers are illegal in 64-bit mode. Add missing
NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
(previously one had to explicitly encode a rex64 prefix). Re-enable
lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
They should be correct now.
* gas/mn10300/relax.s: Add further tests of the relaxing of branch instructions.
* gas/mn10300/relax.d: Add expected relocations.
2004-11-23 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.h (CpuMMX2): Declare. Artificial classifier to
indicate the MMX extensions added by both SSE and 3DNow!A.
(Cpu3dnowA): Declare.
(CpuUnknownFlags): Update.
* config/tc-i386.c (cpu_sub_arch_name): Declare.
(cpu_arch): i586 and pentium do not imply MMX. i686 and pentiumpro do
neither imply SSE nor MMX. k6 implies MMX. k6_2 additionally implies
3DNow!. Athlon additionally implies 3DNow!A. Several new
entries (those starting with a dot are for sub-arch specification).
(set_cpu_arch): Handle sub-arch specifications.
(parse_insn): Distinguish between instructions not supported because
of insufficient CPU features and because of 64-bit mode.
* doc/c-i386.texi: Describe enhanced .arch directive.
include/opcode/
2004-11-23 Jan Beulich <jbeulich@novell.com>
* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
available only with SSE2. Change the MMX additions introduced by SSE
and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
instructions by their now designated identifier (since combining i686
and 3DNow! does not really imply 3DNow!A).
* elf32-arm.c (PLT_THUMB_STUB_SIZE): Define.
(elf32_arm_plt_thumb_stub): New.
(struct elf32_arm_link_hash_entry): Add plt_thumb_refcount
and plt_got_offset.
(elf32_arm_link_hash_traverse): Fix typo.
(elf32_arm_link_hash_table): Add obfd.
(elf32_arm_link_hash_newfunc): Initialize new fields.
(elf32_arm_copy_indirect_symbol): Copy plt_thumb_refcount.
(elf32_arm_link_hash_table_create): Initialize obfd.
(record_arm_to_thumb_glue): Mark the glue as a local ARM function.
(record_thumb_to_arm_glue): Mark the glue as a local Thumb function.
(bfd_elf32_arm_get_bfd_for_interworking): Verify that the
interworking BFD is not dynamic.
(bfd_elf32_arm_process_before_allocation): Handle R_ARM_PLT32. Do
not emit glue for PLT references.
(elf32_arm_final_link_relocate): Handle Thumb functions. Do not
emit glue for PLT references. Support the Thumb PLT prefix.
(elf32_arm_gc_sweep_hook): Handle R_ARM_THM_PC22 and
plt_thumb_refcount.
(elf32_arm_check_relocs): Likewise.
(elf32_arm_adjust_dynamic_symbol): Handle Thumb functions and
plt_thumb_refcount.
(allocate_dynrelocs): Handle Thumb PLT references.
(elf32_arm_finish_dynamic_symbol): Likewise.
(elf32_arm_symbol_processing): New function.
(elf_backend_symbol_processing): Define.
opcodes/
* arm-dis.c (WORD_ADDRESS): Define.
(print_insn): Use it. Correct big-endian end-of-section handling.
gas/testsuite/
* gas/arm/mapping.d: Expect F markers for Thumb code.
* gas/arm/unwind.d: Update big-endian pattern.
ld/
* emultempl/armelf.em (arm_elf_set_bfd_for_interworking): Don't use
a dynamic object for stubs.
ld/testsuite/
* ld-arm/mixed-app.d, ld-arm/mixed-app.r, ld-arm/mixed-app.s,
ld-arm/mixed-app.sym, ld-arm/mixed-lib.d, ld-arm/mixed-lib.r,
ld-arm/mixed-lib.s, ld-arm/mixed-lib.sym, ld-arm/arm-dyn.ld,
ld-arm/arm-lib.ld: New files.
* ld-arm/arm-app-abs32.d, ld-arm/arm-app-abs32.r, ld-arm/arm-app.d,
ld-arm/arm-app.r, ld-arm/arm-lib-plt32.d, ld-arm/arm-lib-plt32.r,
ld-arm/arm-lib.d, ld-arm/arm-lib.r, ld-arm/arm-static-app.d,
ld-arm/arm-static-app.r: Update for big-endian.
* ld-arm/arm-elf.exp: Run the new tests.
include/ChangeLog
* xtensa-isa-internal.h (xtensa_interface_internal): Add class_id.
* xtensa-isa.h (xtensa_interface_class_id): New prototype.
bfd/ChangeLog
* xtensa-isa.c (xtensa_interface_class_id): New.
gas/ChangeLog
* config/tc-xtensa.c (finish_vinsn): Clear pending instruction if
there is a conflict.
(check_t1_t2_reads_and_writes): Check for both reads and writes to
interfaces that are related as determined by xtensa_interface_class_id.
* config/tc-xtensa.c (MAX_IMMED6): Change value to 65.
gas/testsuite/
* gas/xtensa/short_branch_offset.s: New.
* gas/xtensa/short_branch_offset.d: New.
* gas/xtensa/all.exp: Run new test.
PR 528
* symbols.c (resolve_symbol_value): Convert weak symbols only
for Windows PECOFF.
(symbol_equated_reloc_p): Don't equate weaks when relocating
only for Windows PECOFF.
* config/tc-crx.c: Rename argument types.
(processing_arg_number): Rename to 'cur_arg_num'.
(get_number_of_bits): Rename to 'set_operand_size'.
(get_operandtype): Rename to 'parse_operand', totally rewrite.
(set_cons_rparams): Rename to 'set_operand', totally rewrite.
(set_indexmode_parameters): Remove function, integrate its code into
'set_operand'.
(set_operand_size): Get rid of 'Operand Number' function parameter -
use global variable 'cur_arg_num' instead.
Use a local 'argument' pointer to reference the current argument.
(parse_operand): Likewise.
(set_operand): Likewise.
(process_label_constant): Likewise.
* config/tc-crx.c: Rename argument types.
(processing_arg_number): Rename to 'cur_arg_num'.
(get_number_of_bits): Rename to 'set_operand_size'.
(get_operandtype): Rename to 'parse_operand', totally rewrite.
(set_cons_rparams): Rename to 'set_operand', totally rewrite.
(set_indexmode_parameters): Remove function, integrate its code into 'set_operand'.
(set_operand_size): Get rid of 'Operand Number' function parameter - use global variable 'cur_arg_num' instead.
Use a local 'argument' pointer to reference the current argument.
(parse_operand): Likewise.
(set_operand): Likewise.
(process_label_constant): Likewise.
DEFAULT_CRIS_ARCH. Handle crisv32-*-linux-gnu* like
cris-*-linux-gnu* and crisv32-*-* like cris-*-*.
* configure: Regenerate.
* config/tc-cris.c (enum cris_archs): New.
(cris_mach, cris_arch_from_string, s_cris_arch, get_sup_reg)
(cris_insn_ver_valid_for_arch): New functions.
(DEFAULT_CRIS_ARCH): New macro, default to cris_any_v0_v10.
(cris_arch): New variable.
(md_pseudo_table): New pseudo .arch.
(err_for_dangerous_mul_placement): Initialize according to
DEFAULT_CRIS_ARCH.
(STATE_COND_BRANCH): Renamed from STATE_CONDITIONAL_BRANCH.
All users changed.
(STATE_COND_BRANCH_V32, STATE_COND_BRANCH_COMMON)
(STATE_ABS_BRANCH_V32, STATE_LAPC, BRANCH_BF_V32, BRANCH_BB_V32)
(BRANCH_WF_V32, BRANCH_WB_V32): New.
(BRANCH_BF, BRANCH_BB, BRANCH_WF, BRANCH_WB): Don't undef after
use in md_cris_relax_table.
(md_cris_relax_table): Add entries for STATE_COND_BRANCH_V32,
STATE_COND_BRANCH_COMMON, STATE_ABS_BRANCH_V32, STATE_LAPC.
Update and improve head comment.
(OPTION_PIC): Define in terms of previous option, OPTION_US.
(OPTION_MULBUG_ABORT_ON, OPTION_MULBUG_ABORT_OFF): Similar.
(OPTION_ARCH): New.
(md_longopts): New option --march=...
(cris_any_v0_v10_long_jump_size, crisv32_long_jump_size): New
macros.
(md_long_jump_size): Initialize in terms of DEFAULT_CRIS_ARCH.
(HANDLE_RELAXABLE): New macro.
(md_estimate_size_before_relax): Use HANDLE_RELAXABLE for common
cases. Check for weak symbols and assume not relaxable. Handle
STATE_COND_BRANCH_V32, STATE_COND_BRANCH_COMMON,
STATE_ABS_BRANCH_V32, STATE_LAPC. Use new variable symbolP, not
fragP->fr_symbol.
(md_convert_frag): Handle STATE_COND_BRANCH_V32,
STATE_COND_BRANCH_COMMON, STATE_ABS_BRANCH_V32, STATE_LAPC.
(cris_create_short_jump): Adjust for CRISv32.
(md_create_long_jump): Ditto. Emit error for common_v10_v32.
(md_begin): Define symbols "..asm.arch.cris.v32",
"..asm.arch.cris.v10", "..asm.arch.cris.common_v10_v32" and
"..asm.arch.cris.any_v0_v10". Use cris_insn_ver_valid_for_arch
when entering opcode table entry points.
(md_assemble): Adjust branch handling for CRISv32. Handle LAPC
relaxation. In fix_new_exp call for main insn, pass 1 for pcrel
parameter for 8, 16 and 32-bit pc-relative insns and LAPC.
(cris_process_instruction): Initialize out_insnp->insn_type to
CRIS_INSN_NONE, not CRIS_INSN_NORMAL.
<case ']', '[', 'A', 'd', 'Q', 'N', 'n', 'Y', 'U', 'u', 'T'>: New
cases.
<case 'm'>: Check that modified_char == '.'.
<invalid operands>: Consume the rest of the line.
When operands don't match, skip over subsequent insns with
non-matching version specifier but same mnemonic.
<immediate constant, case SIZE_SPEC_REG>: Immediate operands for
special registers in CRISv32 are always 32 bit long.
<immediate constant, case SIZE_FIELD_SIGNED, SIZE_FIELD_UNSIGNED>:
New cases.
(get_gen_reg): Only recognize "PC" when followed by "+]" for v32
and compatible. Recognize "ACR" for v32, unless followed by "+".
(get_spec_reg): Consider cris_arch when looking up register.
(get_autoinc_prefix_or_indir_op): Don't recognize assignment for
v32 or compatible.
(get_3op_or_dip_prefix_op): Check for ']' after seeing '[rN+'.
(cris_get_expression): Restore input_line_pointer if failing "early".
(get_flags): Consider cris_arch and recognize flags accordingly.
(branch_disp): Adjust for CRISv32.
(gen_cond_branch_32): Similar. Emit error for common_v10_v32.
(cris_number_to_imm): Use as_bad_where, not as_bad. Remove
related FIXME. Don't insist on BFD_RELOC_32_PCREL fixup to be
resolved. Don't enter zeros in object file for
BFD_RELOC_32_PCREL.
<case BFD_RELOC_CRIS_LAPCQ_OFFSET, BFD_RELOC_CRIS_SIGNED_16>
<case BFD_RELOC_CRIS_SIGNED_8>: New case.
(md_parse_option): Break out "return 1".
<OPTION_ARCH> New case.
(tc_gen_reloc): <case BFD_RELOC_CRIS_LAPCQ_OFFSET>
<case BFD_RELOC_CRIS_SIGNED_16, BFD_RELOC_CRIS_SIGNED_8>
<case BFD_RELOC_CRIS_UNSIGNED_8, BFD_RELOC_CRIS_UNSIGNED_16>
<case BFD_RELOC_32_PCREL>: New cases.
Addends for non-zero fx_pcrel are too in fx_offset.
(md_show_usage): Show --march=<arch>.
(md_apply_fix3): Adjust val for BFD_RELOC_CRIS_LAPCQ_OFFSET.
(md_pcrel_from): BFD_RELOC_CRIS_LAPCQ_OFFSET is PC-relative too.
(s_syntax) <struct syntaxes>: Properly constify member operand.
* config/tc-cris.h (TARGET_MACH): Define.
(cris_mach): Declare.
* doc/as.texinfo (Overview) <CRIS>: Add --march=...
* doc/c-cris.texi (CRIS-Symbols): New node for built-in symbols.
(CRIS-Opts): Document --march=...
(CRIS-Pseudos): Document .arch.
