2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
Ali Lown <ali.lown@imgtec.com>
sim/common/
* sim-bits.h (EXTEND6): New macro.
(EXTEND12): New macro.
(EXTEND25): New macro.
sim/mips/
* Makefile.in (tmp-micromips): New rule.
(tmp-mach-multi): Add support for micromips.
* configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
that works for both mips64 and micromips64.
(mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
micromips32.
Add build support for micromips.
* dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
Refactored instruction code to use these functions.
* dsp2.igen: Refactored instruction code to use the new functions.
* interp.c (decode_coproc): Refactored to work with any instruction
encoding.
(isa_mode): New variable
(RSVD_INSTRUCTION): Changed to 0x00000039.
* m16.igen (BREAK16): Refactored instruction to use do_break16.
(JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
* micromips.dc: New file.
* micromips.igen: New file.
* micromips16.dc: New file.
* micromipsdsp.igen: New file.
* micromipsrun.c: New file.
* mips.igen (do_swc1): Changed to work with any instruction encoding.
(do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo
do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu
do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu
do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub
do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo
do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd
do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt
do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt
do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt
do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu
do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32
do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf
do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt
do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps
do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1
do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1
do_trunc_fmt): New functions, refactored from existing instructions.
Refactored instruction code to use these functions.
(RSVD): Changed to use new reserved instruction.
(loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32,
check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32
and micromips64 models.
Added include for micromips.igen and micromipsdsp.igen
Add micromips32 and micromips64 models.
(DecodeCoproc): Updated to use new macro definition.
* mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
do_seb, do_seh do_rdhwr, do_wsbh): New functions.
Refactored instruction code to use these functions.
* sim-main.h (CP0_operation): New enum.
(DecodeCoproc): Updated macro.
(IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32,
ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines.
(sim_state): Add isa_mode field.
sim/testsuite/sim/mips/
* basic.exp (run_micromips_test, run_sim_tests): New functions
Add support for micromips tests.
* hilo-hazard-4.s: New file.
* testutils.inc (_dowrite): Changed reserved instruction encoding.
(writemsg): Moved the la and li instructions before the data they are
assigned to, which prevents a bug where MIPS32 relocations are used instead
of micromips relocations when building for micromips.
The bfin/msp430 ports already had trace logic set up for reading/writing
cpu registers, albeit using different unrelated levels (core & vpu). Add
a proper register class for these and for other ports.
This helper macro has largely the same behavior as libiberty's lbasename.
There is a slight nuance related to colons, but it's not clear what the
point of that is, and the code implies that it just wants the basename.
Since --trace-debug is for people hacking on the sim sources rather than
people just using the sim, default it to off. This matches the behavior
of other debug knobs we have.
Since we always include the raw syscall number when tracing, also
including it in the name when it's unknown is redundant. Simplify
the code by using a constant string.
The new helpers for walking the maps tested the wrong value for exiting
the for loop. This caused crashes when looking up entries that were not
in the map.
Many ports have the same sim syscall logic, so add some helpers to handle
all the common details. The arches still have to deal with the unpacking
and packing of the syscall arguments, but the rest of the sim<->callback
glue is now shared.
When tracing, we often want to display the human readable name for the
various syscall/errno values. Rather than make each target duplicate
the lookup, extend the existing maps to include the string directly,
and add helper functions to look up the constants.
While most targets are autogenerated (from libgloss), the bfin/cris
targets have custom maps for the Linux ABI which need to be updated
by hand.
The Blackfin port had some TRACE_xxx macros for easily logging trace data.
Use these as a base for common ones that have a simple form and match the
existing sets of helper macros.
The cgen code declares some macros/funcs using the trace_xxx prefix, but
the code isn't generic and only works with cgen targets. This is blocking
the creation of new common trace functions.
Let's blindly add cgen_xxx prefixes to all these symbols. Some already
use this convention to avoid conflicts, so it makes sense to align them.
In the future we might want to move some to the common trace core, but
one thing at a time.
First we convert the ETRACE_P to STRACE_EVENTS_P. This means we move from
using the sim_events.trace storage to the common sim_state_base.trace_data
array. With that deleted, the common trace init code can be simplified so
the sim state works the same as the sim cpu.
Now that libgloss has a header tracking the syscalls for this arch, we
can update the database to include it for the symbolic constants/maps.
Then we can switch the mcore syscall callbacks over to the common ones.
Since newlib no longer shares the same repo as binutils/gdb, we have to go
searching further afield to locate the sources. We still look at the top
level for newlib, but if that is not found, we also try up one dir outside
of this source tree. It sucks, but better than the status quo (no workie).
Since every target typedefs this the same way, move it to the common code.
We have to leave Blackfin behind here for now because of inter-dependencies
on types and headers: sim-base.h includes sim-model.h which needs types in
machs.h which needs types in bfim-sim.h which needs SIM_CPU.
Almost every target defines sim_cia the same way -- either using the
address_word type directly, or a type of equivalent size. The only
odd one out is sh64 (who has 32bit address_word and 64bit cia), and
even that case doesn't seem to make sense. We'll put off clean up
though of sh64 and at least set up a sensible default for everyone.
The CIA_{GET,SET} macros serve the same function as CPU_PC_{GET,SET}
except the latter adds a layer of indirection via the sim state. This
lets models set up different functions at runtime and doesn't reach so
directly into the arch-specific cpu state.
It also doesn't make sense to have two sets of macros that do exactly
the same thing, so lets standardize on the one that gets us more.
Now that all the targets are utilizing CPU_PC_{FETCH,STORE}, and the
cpu state is multicore, and the STATE_CPU defines match, we can move
it all to the common code.
The old run frontend had a --version option, but the new common
sim-options file does not. Restore support for that so we can
get version info out of `run` when using the new frontend.
Now that all targets have been converted to nrun, we can finally punt
this old inconsistent interface.
A few stray references to the old run were sprinkled about; clean them
up in the process.
We leave behind the run(1) man page mostly so that we get it updated for
the new nrun interface.
With newer versions of gcc (5.x), the extern inline we're using with the
cgen-{mem,ops} modules no longer work. Since this code really wants the
gnu inline semantics, use that attribute explicitly.
With newer versions of gcc (5.x), the extern inline we're using with the
sim-arange module no longer works. Since this code really wants the gnu
inline semantics, use that attribute explicitly.
Reported-by: DJ Delorie <dj@redhat.com>
Reported-by: Joel Sherrill <joel.sherrill@oarcorp.com>
The profile code was using STATE_WATCHPOINTS to get access to the PC, but
we already have a standard method for getting the pc, so switch to that.
This assumes that sizeof_pc is the same size as sim_cia, but we already
assume this in places by way of sim_pc_{get,set}, and this is how it's
documented in the sim-base.h API.
