darkkirb/old-cross-binutils
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90 commits

Author SHA1 Message Date
Nick Clifton
4f3c3dbb37 Fix BLX(1) for Thumb 2001-03-06 22:33:47 +00:00
Nick Clifton
917bca4f21 Add support for disabling alignment checks when performing GDB interface 
calls or SWI emulaiton routines.  (Alignment checking code has not yet been
contributed).
 2001-02-28 01:04:24 +00:00
Nick Clifton
2ef048fc9f Remove Prefetch abort for breakpoints. Instead set the state to RESUME. 2001-02-16 22:04:22 +00:00
Nick Clifton
44e23e575b Add code to preserve processor mode when a prefetch 
abort is signalled after processing a breakpoint.
 2001-02-15 02:38:15 +00:00
Nick Clifton
5f7d0a33db Reset processor into ARM mode for any machine type except the early ARMs. 2001-02-14 22:21:20 +00:00
Nick Clifton
1e5d4e465c Prevent Aborts from happening whilst emulating a SWI 2001-02-14 03:50:46 +00:00
Nick Clifton
179ae6ea64 Fix definition of NEGBRANCH 2001-02-12 23:29:49 +00:00
Nick Clifton
dda308f5fd Update base address register after restoring register bank. 2001-02-01 20:39:51 +00:00
Nick Clifton
88694af3f9 Detect installation of SWI vector by running program as well as loading program. 2001-02-01 00:14:40 +00:00
Nick Clifton
ac1c9d3aad Fix test for StoreDouble Instruction. 2000-12-19 00:58:04 +00:00
Nick Clifton
9a6b6a66b7 Add 0x91 as an FPE SWI. 2000-12-11 03:08:17 +00:00
Nick Clifton
760a7bbec5 Add emulation of double word load and store instructions. 2000-12-08 01:38:47 +00:00
Nick Clifton
7f53bc3526 Suppress support of DEMON swi's in XScale mode. 2000-12-03 23:28:46 +00:00
Nick Clifton
f1129fb8ff Add support for ARM's v5TE architecture and Intel's XScale extenstions 2000-11-30 01:55:12 +00:00
Nick Clifton
3943c96b07 Replace StrongARM property with v4 and v5 properties. 2000-09-15 23:55:50 +00:00
Nick Clifton
4bc1de7b2d Compute write back value for post increment loads before 
performing the load in case the offset register is overwritten.
 2000-08-15 00:10:52 +00:00
Fernando Nasser
0a4321b903 2000-07-14 Fernando Nasser <fnasser@cygnus.com> 
* wrapper.c (sim_create_inferior): Fix typo in the previous patch.
 2000-07-14 21:27:15 +00:00
Fernando Nasser
64a1067567 2000-07-14 Fernando Nasser <fnasser@cygnus.com> 
* wrapper.c (sim_create_inferior): Reset mode to ARM when creating a
        new inferior.
 2000-07-14 16:49:46 +00:00
Alexandre Oliva
ae3c7619e1 * armvirt.c (ABORTS): Do not define. 2000-07-04 08:00:19 +00:00
Alexandre Oliva
1e6b544a97 * armdefs.h (struct ARMul_State): Add is_StrongARM. 
(ARM_Strong_Prop, STRONGARM): Define.
* arminit.c (ARMul_NewState): Reset is_StrongARM.
(ARMul_SelectProcessor): Set is_StrongARM.
* wrapper.c (sim_create_inferior): Use bfd machine type to
determine processor type to emulate.
* armemu.h (BUSUSEDINCPCS, BUSUSEDINCPCN): Don't increment PC
when emulating StrongARM.
 2000-07-04 07:18:18 +00:00
Alexandre Oliva
66210567f0 * armemu.c (ARMul_Emulate, t_undefined): Proceed to next insn. 2000-07-04 06:54:48 +00:00
Alexandre Oliva
e063aa3bd8 * armemu.h (INSN_SIZE): New macro. 
(SET_ABORT): Save CPSR in SPSR and set LR.
* armemu.c (ARMul_Emulate, isize): Set to INSN_SIZE.
(WriteR15, WriteSR15): Do not discard bit 1 in Thumb mode.
* arminit.c (ARMul_Abort): Use new SETABORT and INSN_SIZE.
 2000-07-04 06:52:30 +00:00
Alexandre Oliva
13b6dd6f68 * armemu.c (LoadSMult): Use WriteR15() to discard the least 
significant bits of PC.
 2000-07-04 06:39:39 +00:00
Alexandre Oliva
892c6b9d8f * armemu.h (WRITEDESTB): New macro. 
* armemu.c (ARMul_Emulate26, bl): Use WriteR15Branch() to
modify PC.  Moved the existing logic...
(WriteR15Branch): ... here.  New function.
(WriteR15, WriteSR15): Drop the two least significant bits.
(LoadSMult): Use WriteR15Branch() to modify PC.
(LoadMult): Use WRITEDESTB() instead of WRITEDEST().
 2000-07-04 06:35:36 +00:00
Alexandre Oliva
cf52c765b0 * armemu.h (GETSPSR): Call ARMul_GetSPSR(). 
* armsupp.c (ARMul_CPSRAltered): Zero out bits as they're
extracted from state->Cpsr, but preserve the unused bits.
(ARMul_GetCPSR): Get bits preserved in state->Cpsr.
(ARMul_GetSPSR, ARMul_FixCPSR): Use ARMul_GetCPSR() to
get the full CPSR word.
 2000-07-04 06:19:29 +00:00
Alexandre Oliva
4ef2594f4e * armemu.h (PSR_FBITS, PSR_SBITS, PSR_XBITS, PSR_CBITS): New. 
(SETPSR_F, SETPSR_S, SETPSR_X, SETPSR_C): New macros.
(SETPSR, SET_INTMODE, SETCC): Removed.
* armsupp.c (ARMul_FixCPSR, ARMul_FixSPSR): Do not test bit
mask.  Use SETPSR_* to modify PSR.
(ARMul_SetCPSR): Load all bits from value.
* armemu.c (ARMul_Emulate, msr): Do not test bit mask.
 2000-07-04 06:06:30 +00:00
Alexandre Oliva
e62263b8ec * armemu.c (ARMul_Emulate): Compute writeback value before 
loading, since the offset register may be the destination
register.
 2000-07-04 05:30:43 +00:00
Alexandre Oliva
b0eae074ca * armdefs.h (SYSTEMBANK): Define as USERBANK. 
* armsupp.c (ARMul_SwitchMode): Remove SYSTEMBANK cases.
 2000-07-04 05:16:20 +00:00
Alexandre Oliva
f9c22bc3a4 * armemu.c (Multiply64): Fix computation of flag N. 2000-06-22 20:42:34 +00:00
Alexandre Oliva
ee9a777240 * armemu.c (MultiplyAdd64): Fix computation of flag N. 2000-06-22 20:03:32 +00:00
Alexandre Oliva
fe47e8dfd3 * armemu.h (NEGBRANCH): Do not overwrite the two most significant 
bits of the offset.
 2000-06-20 09:36:12 +00:00
Nick Clifton
c1a72ffdd6 Add support for v4 SystemMode. 2000-05-30 17:13:37 +00:00
Andrew Cagney
eb2d80b469 Change profiling so that it is enabled by default. Re-generate everything. 2000-05-24 04:39:50 +00:00
Nick Clifton
3463c3fbbb Add special case handling when GDB set CPSR register 2000-05-23 23:52:46 +00:00
Frank Ch. Eigler
5d0d395e94 * arm abort fix 
2000-03-11  Philip Blundell  <philb@gnu.org>

	* armemu.c (LoadSMult, LoadMult): Correct handling of aborts.
	Patch from Allan Skillman <Allan.Skillman@arm.com>.
 2000-04-10 15:35:56 +00:00
Frank Ch. Eigler
6c9e0292a3 * memory corruption fix 
Wed Mar 22 15:24:21 2000  glen mccready  <gkm@pobox.com>

	* wrapper.c (sim_open,sim_close): Copy into myname, free myname.
 2000-03-23 23:28:43 +00:00
Frank Ch. Eigler
d018757450 * adding forgotten entry 2000-03-02 21:53:51 +00:00
Nick Clifton
6d358e869b Fix compile time warning messages. 2000-02-08 20:54:27 +00:00
Jason Molenda
dfcd3bfb6f import gdb-2000-02-04 snapshot 2000-02-05 07:30:26 +00:00
Jason Molenda
c2d11a7da0 import gdb-1999-12-06 snapshot 1999-12-07 03:56:43 +00:00
Jason Molenda
5c44784c11 import gdb-1999-11-01 snapshot 1999-11-02 04:44:47 +00:00
Jason Molenda
2df3850c7b import gdb-1999-10-11 snapshot 1999-10-12 04:37:53 +00:00
Jason Molenda
2acceee218 import gdb-1999-10-04 snapshot 1999-10-05 23:13:56 +00:00
Stan Shebs
d4f3574e77 import gdb-1999-09-08 snapshot 1999-09-09 00:02:17 +00:00
Jason Molenda
43e526b9b4 import gdb-1999-07-12 snapshot 1999-07-12 11:15:22 +00:00
Stan Shebs
cd0fc7c3eb import gdb-1999-05-10 1999-05-11 13:35:55 +00:00
Stan Shebs
7a292a7adf import gdb-19990422 snapshot 1999-04-26 18:34:20 +00:00
Stan Shebs
c906108c21 Initial creation of sourceware repository 1999-04-16 01:35:26 +00:00
Stan Shebs
071ea11e85 Initial creation of sourceware repository 1999-04-16 01:34:07 +00:00
Nick Clifton
043333a61a define SIM_HAVE_BIENDIAN 1998-09-14 16:58:00 +00:00