Jeff Law
ecb4b5a357
* simops.c Implement remaining 4 byte instructions.
1996-11-27 17:19:44 +00:00
Jeff Law
2e35551c74
* simops.c Implement remaining 3 byte instructions.
...
Moving right along...
1996-11-27 16:51:30 +00:00
Jeff Law
f5f13c1d73
* simops.c: Implement remaining 2 byte instructions. Call
...
abort for instructions we're not implementing now.
1996-11-27 16:25:03 +00:00
Jeff Law
707641f658
* simops.c: Implement lots of random instructions.
...
Implments most instructions with first nibble 0x0 - 0xe and
those with the first byte 0xf0 - 0xf2.
1996-11-27 07:20:36 +00:00
Jeff Law
1f3bea2169
* simops.c: Implement "movm" and "bCC" insns.
...
Function calls and conditional branches work!
1996-11-27 05:29:49 +00:00
Jeff Law
92284aaa35
* mn10300_sim.h (_state): Add another register (MDR).
...
(REG_MDR): Define.
* simops.c: Implement "cmp", "calls", "rets", "jmp" and
a few additional random insns.
We can now function calls. We get out of crt0 into main now, then lose
when calls are nested (because don't handle movm yet).
1996-11-27 00:53:25 +00:00
Jeff Law
73e6529893
* mn10300_sim.h (PSW_*): Define for CC status tracking.
...
(REG_D0, REG_A0, REG_SP): Define.
* simops.c: Implement "add", "addc" and a few other random
instructions.
Starting to simulate instructions for the mn10300. Executes some of
the crt0 code now!
1996-11-26 22:58:24 +00:00
Jeff Law
b5f831ac51
* gencode.c, interp.c: Snapshot current simulator code.
...
(crude) hashing works, along with dispatch to the OP_* functions.
1996-11-26 20:40:19 +00:00
Jeff Law
05ccbdfdd2
* Makefile.in, config.in, configure, configure.in: New files.
...
* gencode.c, interp.c, mn10300_sim.h, simops.c: New files.
Skeleton mn10300 simulator
1996-11-25 19:52:08 +00:00
