Commit graph

2341 commits

Author SHA1 Message Date
Ben Elliston
f18ee7ef71 2001-07-31 Ben Elliston <bje@redhat.com>
* lib/sim-defs.exp (run_sim_test): Include a description such as
	"assembling" or "linking" that identifies the phase a test fails
	in, for easier analysis of failures.
2001-07-31 04:59:59 +00:00
Stephane Carrez
eefde3513e * dv-m68hc11eepr.c (m68hc11eepr_info): Fix print of current write
address.
	(m68hc11eepr_port_event): Fix detach/attach logic.
2001-07-28 19:19:05 +00:00
Stephane Carrez
00d0c012ef * Makefile.in (SIM_OBJS): Remove sim-resume.o
* interp.c (sim_resume): New function from sim-resume.c, install
	the stepping event after having processed the pending ticks.
	(has_stepped): Likewise.
	(sim_info): Produce an output only if verbose or STATE_VERBOSE_P.
2001-07-22 12:33:58 +00:00
Andrew Cagney
bf1bef8f1c Regenerate using autoconf 2.13. 2001-07-18 06:20:29 +00:00
Daniel Jacobowitz
54cfd411af Makefile.in: Add dependencies on $(CPU_H). 2001-07-16 18:36:37 +00:00
Andrew Cagney
b51c76031a * Makefile.in (gencode): Provide explicit path to gencode.c. 2001-07-10 22:46:59 +00:00
Ben Elliston
e3e473dacc 2001-07-05 Ben Elliston <bje@redhat.com>
* Make-common.in (srccgen): Remove.
	(CGEN_CPU_DIR): Define.
	(CGEN_READ_SCM): Redefine without $(srccgen).
	(CGEN_ARCH_SCM): Ditto.
	(CGEN_CPU_SCM): Ditto.
	(CGEN_DECODE_SCM): Ditto.
	(CGEN_DESC_SCM): Ditto.

	* $arch/Makefile.in: Use $(CGEN_CPU_DIR) where applicable.
2001-07-05 13:51:26 +00:00
Stephane Carrez
81e09ed832 Improve HC11 simulator to support HC12 2001-05-20 15:40:27 +00:00
Stephane Carrez
11115521f6 * dv-m68hc11sio.c (m68hc11sio_tx_poll): Always check for
pending interrupts.
	* interrupts.c (interrupts_process): Keep track of the last number
	of masked insn cycles.
	(interrupts_initialize): Clear last number of masked insn cycles.
	(interrupts_info): Report them.
	(interrupts_update_pending): Compute clear and set masks of
	interrupts and clear the interrupt bits before setting them
	(due to SCI interrupt sharing).
	* interrupts.h (struct interrupts): New members last_mask_cycles
	and xirq_last_mask_cycles.
2001-05-20 15:36:29 +00:00
Nick Clifton
fb7a8ef0df Fix handling of XScale LDRD and STRD instructions with post indexed addressing modes. 2001-05-11 21:51:07 +00:00
Andrew Cagney
d448180670 Don't loose last block during a dma. 2001-05-10 17:48:10 +00:00
Nick Clifton
dac07255f9 Check Mode not Bank in order to determine rocesor mode. 2001-05-08 08:28:28 +00:00
Jim Blandy
ff88f59d5a *** empty log message *** 2001-05-07 06:10:25 +00:00
Jim Blandy
be5fcb106b * mn10300.igen: Doc fixes. 2001-05-07 04:52:00 +00:00
Alexandre Oliva
cc274e7c27 * Makefile.in (idecode.o, op_utils.o, semantics.o, simops.o):
Depend on targ-vals.h.
2001-04-26 19:23:16 +00:00
Frank Ch. Eigler
2836ee25d9 * thanks, nickc
2001-04-25  Frank Ch. Eigler  <fche@redhat.com>

	* sim-load.c (sim_load_file): Put it back [...]
2001-04-25 21:14:28 +00:00
Andrew Cagney
5b77812558 Revert call to bfd_cache_close(). 2001-04-21 22:50:55 +00:00
Frank Ch. Eigler
6ec9f4a9be * bug fix
2001-04-19  Frank Ch. Eigler  <fche@redhat.com>

	* sim-utils.c (sim_analyze_program): Call bfd_cache_close after
	we're finished with its immediate use.
	* sim-load.c (sim_load_file): Ditto.
2001-04-19 20:59:30 +00:00
Matthew Green
c3ae2f98d0 * XScale coprocessor support.
2001-04-18  matthew green  <mrg@redhat.com>

	* armcopro.c (write_cp15_reg): Set CHANGEMODE if endianness changes.
	(read_cp15_reg): Make non-static.
	(XScale_cp15_LDC): Update for write_cp15_reg() change.
	(XScale_cp15_MCR): Likewise.
	(XScale_cp15_write_reg): Likewise.
	(XScale_check_memacc): New function. Check for breakpoints being
	activated by memory accesses.  Does not support the Branch Target
	Buffer.
	(XScale_set_fsr_far): New function. Set FSR and FAR for XScale.
	(XScale_debug_moe): New function. Set the debug Method Of Entry,
	if configured.
	(write_cp14_reg): Reset count counter if requested.
	* armdefs.h (struct ARMul_State): New members `LastTime' and
	`CP14R0_CCD' used for the timer/counters.
	(ARMul_CP13_R0_FIQ, ARMul_CP13_R0_IRQ, ARMul_CP13_R8_PMUS,
	ARMul_CP14_R0_ENABLE, ARMul_CP14_R0_CLKRST, ARMul_CP14_R0_CCD,
	ARMul_CP14_R0_INTEN0, ARMul_CP14_R0_INTEN1, ARMul_CP14_R0_INTEN2,
	ARMul_CP14_R0_FLAG0, ARMul_CP14_R0_FLAG1, ARMul_CP14_R0_FLAG2,
	ARMul_CP14_R10_MOE_IB, ARMul_CP14_R10_MOE_DB, ARMul_CP14_R10_MOE_BT,
	ARMul_CP15_R1_ENDIAN, ARMul_CP15_R1_ALIGN, ARMul_CP15_R5_X,
	ARMul_CP15_R5_ST_ALIGN, ARMul_CP15_R5_IMPRE, ARMul_CP15_R5_MMU_EXCPT,
	ARMul_CP15_DBCON_M, ARMul_CP15_DBCON_E1, ARMul_CP15_DBCON_E0): New
	defines for XScale registers.
	(XScale_check_memacc, XScale_set_fsr_far, XScale_debug_moe): Prototype.
	(ARMul_Emulate32, ARMul_Emulate26): Clean up function definition.
	(ARMul_Emulate32): Handle the clock counter and hardware instruction
	breakpoints.  Call XScale_set_fsr_far() for software breakpoints and
	software interrupts.
	(LoadMult): Call XScale_set_fsr_far() for data aborts.
	(LoadSMult): Likewise.
	(StoreMult): Likewise.
	(StoreSMult): Likewise.
	* armemu.h (write_cp15_reg): Update prototype.
	* arminit.c (ARMul_NewState): Initialise CP14R0_CCD and LastTime.
	(ARMul_Abort): If XScale, check for FIQ and IRQ being enabled in CP13
	register 0.
	* armvirt.c (GetWord): Call XScale_check_memacc().
	(PutWord): Likewise.
2001-04-18 16:39:37 +00:00
J.T. Conklin
d4424adaef * Makefile.in (simops.o): Add simops.h to dependency list. 2001-04-15 19:57:10 +00:00
Jim Blandy
c0efbca4a3 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
set of the FCSR.
* sim-main.h (COCIDX): Remove definition; this isn't supported by
PENDING_FILL, and you can get the intended effect gracefully by
calling PENDING_SCHED directly.
2001-04-12 14:53:20 +00:00
Nick Clifton
3cf84db9ef Do not enable alignment checking when loading unaligned thumb instructions. 2001-03-20 17:48:02 +00:00
Frank Ch. Eigler
764f1408a3 * mmap support for common simulators
2001-03-16  Frank Ch. Eigler  <fche@redhat.com>

	Add support for mmap-based memory regions.
	* sim-memopt.c (mmap_next_fd): New global.
	(sim_memory_init): Reinitialize it.
	(OPTION_MEMORY_MAPFILE, memory_option_handler): Support new
	"--memory-mapfile FILE" option.  Check for some errors.
	(do_memopt_add): Conditionally do mmap instead of malloc for
	backing store of simulated memory.  Check for more errors.
	(do_simopt_delete, sim_memory_uninstall): Corresponding cleanup.
	* sim-memopt.h (munmap_length): New member of _sim_memopt.
	* configure.in: Look for mmap/fstat related functions and headers.
	* config.in, configure: Regenerated.
2001-03-20 17:13:39 +00:00
Frank Ch. Eigler
35c209920b * tweak
2001-03-15  Frank Ch. Eigler  <fche@redhat.com>

	* sim-core.c (sim_core_map_attach): Correct overlap-related
	error messages.
2001-03-16 03:20:26 +00:00
Andrew Cagney
1e6cd1593b Link with libintl, needed by libopcodes. 2001-03-14 21:51:31 +00:00
Michael Meissner
f6bb7a3bb0 Remove reference to alloca-conf.h 2001-03-07 20:19:41 +00:00
Nick Clifton
4f3c3dbb37 Fix BLX(1) for Thumb 2001-03-06 22:33:47 +00:00
Andrew Cagney
c663138840 Fixes for NetBSD 1.5. NetBSD has been renumbering/renaming its
SYS_* interfaces.
2001-03-05 16:22:45 +00:00
Dave Brolley
55552082e8 2001-03-05 Dave Brolley <brolley
arch.c: Regenerate.
        arch.h: Regenerate.
        cpu.c: Regenerate.
        cpu.h: Regenerate.
        cpuall.h: Regenerate.
        cpux.c: Regenerate.
        cpux.h: Regenerate.
        decode.c: Regenerate.
        decode.h: Regenerate.
        decodex.c: Regenerate.
        decodex.h: Regenerate.
        model.c: Regenerate.
        modelx.c: Regenerate.
        sem-switch.c: Regenerate.
        sem.c: Regenerate.
        semx-switch.c: Regenerate.
2001-03-05 16:05:38 +00:00
Dave Brolley
52fa932eab 2001-03-05 Dave Brolley <brolley@
* arch.c: Regenerate.
        * arch.h: Regenerate.
        * cpu.c: Regenerate.
        * cpu.h: Regenerate.
        * cpuall.h: Regenerate.
        * decode.c: Regenerate.
        * decode.h: Regenerate.
        * model.c: Regenerate.
        * sem-switch.c: Regenerate.
        * sem.c: Regenerate.
2001-03-05 16:00:17 +00:00
Nick Clifton
917bca4f21 Add support for disabling alignment checks when performing GDB interface
calls or SWI emulaiton routines.  (Alignment checking code has not yet been
contributed).
2001-02-28 01:04:24 +00:00
Ben Elliston
fb891446b7 2001-02-23 Ben Elliston <bje@redhat.com>
* sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
	already defined elsewhere.
2001-02-24 02:43:11 +00:00
Ben Elliston
01816cd804 2001-02-22 Ben Elliston <bje@redhat.com>
* sim-trace.h (TRACE_VPU_IDX): Add.
	(TRACE_vpu): Define.
	(WITH_TRACE_VPU_P): Likewise.
	(TRACE_VPU_P): Likewise.
	* sim-trace.c (OPTION_TRACE_VPU): Define.
	(trace_options): Add --trace-vpu.
	(trace_option_handler): Handle OPTION_TRACE_VPU.
	(trace_option_handler): Include VPU tracing in --trace-semantics.
	(trace_idx_to_str): Handle TRACE_VPU_IDX.
2001-02-22 20:47:49 +00:00
Ben Elliston
44a9331cdf 2001-02-21 Ben Elliston <bje@redhat.com>
* sim-trace.h (TRACE_BRANCH_INPUT1): New macro.
	(TRACE_BRANCH_INPUT2): Likewise.
2001-02-21 21:35:41 +00:00
Ben Elliston
8030f85769 2001-02-19 Ben Elliston <bje@redhat.com>
* sim-main.h (sim_monitor): Return an int.
	* interp.c (sim_monitor): Add return values.
	(signal_exception): Handle error conditions from sim_monitor.
2001-02-19 21:57:03 +00:00
Nick Clifton
2ef048fc9f Remove Prefetch abort for breakpoints. Instead set the state to RESUME. 2001-02-16 22:04:22 +00:00
Ben Elliston
9afc4bbfbb 2001-02-16 Ben Elliston <bje@redhat.com>
* MAINTAINERS: Add myself for common portions.
2001-02-15 23:03:41 +00:00
Ben Elliston
c43ad8eb1e * profiling bug fixes.
2001-02-09  Ben Elliston  <bje@redhat.com>

	* (profile_print_pc): Write header out in target byte order.

2001-02-09  Ben Elliston  <bje@redhat.com>

	* sim-profile.c (profile_pc_init): Correct bug in loop logic when
	adjusting the pc shift value.
2001-02-15 21:14:40 +00:00
Nick Clifton
44e23e575b Add code to preserve processor mode when a prefetch
abort is signalled after processing a breakpoint.
2001-02-15 02:38:15 +00:00
Nick Clifton
5f7d0a33db Reset processor into ARM mode for any machine type except the early ARMs. 2001-02-14 22:21:20 +00:00
Nick Clifton
94ab9d7b9e remove spurious whitespace 2001-02-14 03:55:57 +00:00
Nick Clifton
1e5d4e465c Prevent Aborts from happening whilst emulating a SWI 2001-02-14 03:50:46 +00:00
Nick Clifton
179ae6ea64 Fix definition of NEGBRANCH 2001-02-12 23:29:49 +00:00
Chris Demetriou
56b48a7a9b 2001-02-08 Ben Elliston <bje@redhat.com>
* sim-main.c (load_memory): Pass cia to sim_core_read* functions.
        (store_memory): Likewise, pass cia to sim_core_write*.
2001-02-08 05:22:04 +00:00
DJ Delorie
ddcd33c11d * i960-desc.c: Update all the A macro definitions to the new
stdc-sensitive versions that cgen would have used.
2001-02-07 01:16:05 +00:00
Nick Clifton
fae0bf59e6 Add parentheses ready for future conbtribution 2001-02-01 20:56:35 +00:00
Nick Clifton
dda308f5fd Update base address register after restoring register bank. 2001-02-01 20:39:51 +00:00
Jonathan Larmour
42acc51e30 * Makefile.in (gencode): Link with libopcodes in build tree rather
than building source files from there.
2001-02-01 06:56:29 +00:00
Nick Clifton
88694af3f9 Detect installation of SWI vector by running program as well as loading program. 2001-02-01 00:14:40 +00:00
Alexandre Oliva
de0492b6fb * interp.c (sim_create_inferior): Record program arguments for
later inspection by the trap handler.
(count_argc): New function.
(prog_argv): Declare static.
(sim_write): Declare.
(trap): Implement argc, argnlen and argn system calls. Do not
abort on unknown system calls--simply return -1.
* syscall.h (SYS_argc, SYS_argnlen, SYS_argn): Define.
2001-01-30 23:03:56 +00:00
Alexandre Oliva
554064594b * interp.c (trap): Implement time. 2001-01-24 13:17:01 +00:00
Geoffrey Keating
428e1889bc * emul_netbsd.c (do_open): Translate the flag parameter to the
open syscall to the numbers supported by the host.
2001-01-15 23:24:30 +00:00
Chris Demetriou
0b8c7076b5 * MAINTAINERS: Added self and Andrew for the mips sim. 2001-01-15 19:16:57 +00:00
Ben Elliston
badd2b1e70 * Tidy. 2001-01-15 00:23:00 +00:00
Frank Ch. Eigler
9397fcbf1c * configury fix
[common/ChangeLog]
2001-01-12  Chris Demetriou  <cgd@sibyte.com>

	* aclocal.m4 (SIM_AC_OPTION_SCACHE): Properly
	handle the case where a numeric value is supplied.

[eg. m32r/ChangeLog]
2001-01-12  Frank Ch. Eigler  <fche@redhat.com>

	* configure: Regenerated with sim_scache fix.
2001-01-12 18:51:28 +00:00
Ben Elliston
63fe103861 2001-01-06 Ben Elliston <bje@redhat.com>
* cgen.sh: Allow extrafiles to include the semantics files when
	generating an ISA-specific decoder.
2001-01-05 04:36:09 +00:00
Alexandre Oliva
b6f6b44d62 * Make-common.in (sim-io.o): Depend on targ-vals.h. 2000-12-27 17:47:20 +00:00
Ben Elliston
ad8707b58d 2000-12-23 Ben Elliston <bje@redhat.com>
* cgen-trace.c (trace_result): Handle 'f' type operands; output
	them to the trace stream using sim_fpu_printn_fpu. Include
	"sim-fpu.h".
2000-12-23 21:52:14 +00:00
Ben Elliston
b94c096644 2000-12-15 Ben Elliston <bje@redhat.com>
* sim-fpu.h (sim_fpu_printn_fpu): Declare.
	* sim-fpu.c (print_bits): Add digits parameter. Print only as many
	trailing digits as specified (-1 to print all digits).
	(sim_fpu_print_fpu): New wrapper around sim_fpu_printn_fpu.
	(sim_fpu_printn_fpu): Rename from sim_fpu_print_fpu; update calls
	to print_bits ().
2000-12-23 11:51:04 +00:00
Nick Clifton
ac1c9d3aad Fix test for StoreDouble Instruction. 2000-12-19 00:58:04 +00:00
Ben Elliston
fd5d712edf 2000-12-13 Ben Elliston <bje@redhat.com>
* cgen.sh: Set prefix/PREFIX (append ISA if applicable). Factor
	sed expressions into $sedscript, substituting @prefix@/@PREFIX@.
	(defs): New action.
2000-12-13 22:55:54 +00:00
Geoffrey Keating
4c15ccf7af In sim/common:
* sim-endian.h: Don't have parameters on macro definitions which
	are simply renaming functions, to permit use of XCONCAT2 in both
	the macro name and the arguments in a use of such a definition.
In sim/ppc:
	* sim-endian.h: Don't have parameters on macro definitions which
	are simply renaming functions, to permit use of XCONCAT2 in both
	the macro name and the arguments in a use of such a definition.
2000-12-12 20:54:13 +00:00
Ben Elliston
0d277f51d0 2000-12-11 Ben Elliston <bje@redhat.com>
* cgen-ops.h (SUBWORDDFDI): New function.
2000-12-11 07:14:34 +00:00
Nick Clifton
9a6b6a66b7 Add 0x91 as an FPE SWI. 2000-12-11 03:08:17 +00:00
Michael Chastain
7c721b2a2a 2000-11-15 Jim Blandy <jimb@redhat.com>
* sim_calls.c: Doc fix.
	(sim_fetch_register, sim_store_register): Call
	gdbarch_register_name directly, instead of going through
	REGISTER_NAME macro.
2000-12-08 01:52:41 +00:00
Nick Clifton
df38a86eec oops - remove redundant prototype introduced in previous delta 2000-12-08 01:39:48 +00:00
Nick Clifton
760a7bbec5 Add emulation of double word load and store instructions. 2000-12-08 01:38:47 +00:00
Ben Elliston
c79688eb6e 2000-12-05 Ben Elliston <bje@redhat.com>
* Make-common.in (cgen-defs): New target.
	(cgen-decode): Pass $(EXTRAFILES).
2000-12-05 00:56:44 +00:00
Ben Elliston
bb4e03e555 2000-12-05 Ben Elliston <bje@redhat.com>
* genmloop.sh: Use @prefix@, not @cpu@ throughout. Add -prefix and
	-outfile-suffix options.
2000-12-05 00:46:04 +00:00
Ben Elliston
6227bc851d 2000-12-04 Ben Elliston <bje@redhat.com>
* cgen-ops.h (SUBWORDSIQI): Mask off top bits.
	(SUBWORDSIUQI): Likewise.
	(SUBWORDDIHI): Likewise.
	(SUBWORDDIQI): New function.
2000-12-04 04:05:45 +00:00
Ben Elliston
76440e4ba0 2000-12-04 Ben Elliston <bje@redhat.com>
* cgen-trace.c (disassemble_insn): Remove unused declaration.
	* cgen-scache.c (scache_option_handler): Remove unused local var.
2000-12-04 00:57:57 +00:00
Nick Clifton
7f53bc3526 Suppress support of DEMON swi's in XScale mode. 2000-12-03 23:28:46 +00:00
Ben Elliston
cdc2a5c395 2000-12-03 Ben Elliston <bje@redhat.com>
* sim-profile.c (profile_option_handler): Remove unused prof_nr.
2000-12-03 04:23:54 +00:00
Nick Clifton
f1129fb8ff Add support for ARM's v5TE architecture and Intel's XScale extenstions 2000-11-30 01:55:12 +00:00
Nick Clifton
2a1aa0e97c Add GNU Free Documentation License 2000-11-30 01:54:16 +00:00
Stephane Carrez
4e73b9c108 Fix delete_hw_event_data() to free the scheduled events 2000-11-27 19:53:35 +00:00
Stephane Carrez
ce9bc8d1f1 Remove space == 0 restriction in the simulator (dv-core) 2000-11-27 19:49:46 +00:00
Stephane Carrez
b93775f586 Preliminary support for 68HC12 2000-11-26 21:41:31 +00:00
Stephane Carrez
639aa4f72f Register a delete handler for 68HC11 core device node 2000-11-26 20:53:11 +00:00
Stephane Carrez
ce13044d7a Fix for sim/common hw_delete()/hw_tree_delete() 2000-11-25 09:18:52 +00:00
Stephane Carrez
7c070881e4 Fix memory leak in sim_parse_args 2000-11-25 09:16:22 +00:00
Stephane Carrez
6e73e7ed64 Fix device memory allocation in 68hc11 simulator 2000-11-24 20:53:35 +00:00
Ben Elliston
4f49fa1bf0 2000-11-20 Ben Elliston <bje@redhat.com>
* cgen-ops.h (SUBBI): New macro.
	(SUBWORDSIQI, SUBWORDSIHI, SUBWORDSIUQI): New functions.
	(SUBWORDDIHI, SUBWORDDIUQI, SUBWORDDIDF): Likewise.
2000-11-19 22:27:14 +00:00
Greg McGary
fec7d8b0e7 * Makefile.in: remove `@true' commands for rules that have
$(CGEN_MAINT) as a prerequisite.
2000-11-18 09:08:59 +00:00
Ben Elliston
2d84da1b7c 2000-11-16 Ben Elliston <bje@redhat.com>
* cgen-types.h (VOID): New type.
2000-11-16 03:21:48 +00:00
Ben Elliston
dbc168afd2 2000-11-09 Ben Elliston <bje@redhat.com>
* sim-fpu.c (sim_fpu_one): Set exponent to 0.
	(sim_fpu_two): Set exponent to 1.
2000-11-08 23:19:45 +00:00
Ben Elliston
620abd4dfd * Spelling corrections. 2000-11-08 23:12:43 +00:00
Dave Brolley
0ab7df8a89 2000-11-01 Dave Brolley <brolley@cygnus.com>
* lib/sim-defs.exp (run_sm_test): Correct comment. "output" and
	"xerror" options do not use a list of machines. Clear options from
	previous test case. Use "$cpu_option"  to identify the machine to the
	assembler, if specified.
2000-11-01 15:40:35 +00:00
Elena Zannoni
e4f5c43e77 2000-10-26 Ben Elliston <bje@redhat.com>
* cgen.sh: Handle an isa argument between cpu and mach. Default to
        `all'. Pass `-i' options to cgen applications.
        * Make-common.in (cgen-arch, cgen-cpu, cgen-decode, cgen-cpu-decode,
        cgen-desc): Pass $(isa) to cgen.sh.
2000-10-26 16:21:34 +00:00
Geoffrey Keating
c56a7a95d1 * MAINTAINERS: Added self and Andrew for the ppc sim. 2000-10-25 18:18:41 +00:00
Geoffrey Keating
ae02957b46 * ppc-instructions (lfsux): Correct XO field of lfsux instruction. 2000-10-24 16:16:43 +00:00
Ben Elliston
8f1e3ff591 * pendanticism
2000-10-24  Ben Elliston  <bje@redhat.com>

	* gencode.c (tab): Delimit strings with commas where applicable.
2000-10-24 01:02:53 +00:00
Frank Ch. Eigler
d3ee60d90e * cleanup
2000-10-19  Frank Ch. Eigler  <fche@redhat.com>

	On advice from Chris G. Demetriou <cgd@sibyte.com>:
	* sim-main.h (GPR_CLEAR): Remove unused alternative macro.
2000-10-19 10:52:52 +00:00
Ben Elliston
a8d894af63 * usability improvements
2000-10-08  Ben Elliston  <bje@redhat.com>

	* cgen-utils.c (cgen_rtx_error): New function.

2000-10-07  Ben Elliston  <bje@redhat.com>

	* cgen-trace.c (sim_cgen_disassemble_insn): Handle failure
	conditions for sim_core_read_buffer().
2000-10-08 22:37:14 +00:00
Dave Brolley
fb27a91c6c 2000-10-06 Dave Brolley <brolley@redhat.com>
* sem.c: Regenerated.
	* sem-switch.c: Regenerated.
	* semx-switch.c: Regenerated.
2000-10-06 16:59:56 +00:00
Dave Brolley
ce852dd37c 2000-10-06 Dave Brolley <brolley@redhat.com>
* sem.c: Regenerated.
	* sem-switch.c: Regenerated.
2000-10-06 16:58:40 +00:00
Dave Brolley
6d4c43bfc6 2000-09-26 Dave Brolley <brolley@redhat.com>
* cgen-utils.c (RORQI): New function.
	(ROLQI): New function.
	(RORHI): New function.
	(ROLHI): New function.
2000-09-26 17:23:58 +00:00
Nick Clifton
3943c96b07 Replace StrongARM property with v4 and v5 properties. 2000-09-15 23:55:50 +00:00
Stephane Carrez
5f1864472a Missing Makefile.in for 68hc11 simulator 2000-09-12 18:55:37 +00:00
Stephane Carrez
9830501b31 Remove soft reg hack in the 68hc11 simulator 2000-09-10 14:05:29 +00:00
Stephane Carrez
a8afa79ab6 Fix clearing of interrupts in 68hc11 simulator 2000-09-10 12:58:53 +00:00
Stephane Carrez
2990a9f484 * sim-main.h: Define cycle_to_string.
* dv-m68hc11tim.c (cycle_to_string): New function to translate
	the cpu cycle into some formatted time string.
	(m68hc11tim_print_timer): Use it.
	* dv-m68hc11sio.c (m68hc11sio_info): Use cycle_to_string.
	* dv-m68hc11spi.c (m68hc11spi_info): Likewise.
	* interrupts.c (interrupts_info): Likewise.
	* m68hc11_sim.c (cpu_info): Likewise.
2000-09-09 21:00:39 +00:00
Stephane Carrez
401493c8d9 Fix 68hc11 timer device (accuracy, io, timer overflow) 2000-09-06 19:33:12 +00:00
Stephane Carrez
4d72d17a49 Fix 68HC11 SPI simulator 2000-09-05 20:49:46 +00:00
Dave Brolley
de8f5985d0 2000-08-28 Dave Brolley <brolley@redhat.com>
* Makefile.in: Use of @true confuses VPATH. Remove it.
	* cpu.h: Regenerated.
	* cpux.h: Regenerated.
	* decode.c: Regenerated.
	* decodex.c: Regenerated.
	* model.c: Regenerated.
	* modelx.c: Regenerated.
	* sem-switch.c: Regenerated.
	* sem.c: Regenerated.
	* semx-switch.c: Regenerated.
2000-08-28 18:20:30 +00:00
Dave Brolley
e5c590294e 2000-08-28 Dave Brolley <brolley@redhat.com>
* cpu.h: Regenerated.
	* decode.c: Regenerated.
2000-08-28 18:19:41 +00:00
Dave Brolley
0e266e5cc5 2000-08-28 Dave Brolley <brolley@redhat.com>
* cgen-trace.c (sim_cgen_disassemble_insn): Make sure entire insn is
	in insn_value if it will fit.
2000-08-28 18:18:49 +00:00
Dave Brolley
4193618c3c Forgot to check this in with last commit! 2000-08-22 19:27:32 +00:00
Frank Ch. Eigler
604259a086 * Contribute CGEN simulator build support code.
* Patch was posted by bje@redhat.com.
2000-08-21 15:52:39 +00:00
Dave Brolley
80dbae7a49 2000-08-15 Dave Brolley <brolley@redhat.com>
* sim-profile.c (profile_print_speed): Print cpu frequency if not zero.
2000-08-15 18:49:50 +00:00
Dave Brolley
090321281b 2000-08-15 Dave Brolley <brolley@redhat.com>
* sim-profile.h (PROFILE_DATA): Add cpu_freq.
	(PROFILE_CPU_FREQ): New macro.
	* sim-profile.c (OPTION_PROFILE_CPU_FREQUENCY): New enumerator.
	(profile-options): Add profile-cpu-frequency.
	(parse_frequency): New function.
	(profile_option_handler): Handle OPTION_PROFILE_CPU_FREQUENCY.
	(profile_print_speed): Print cpu frequency and simulated execution time.
	Re-indent other items to match.
2000-08-15 18:39:02 +00:00
Nick Clifton
4bc1de7b2d Compute write back value for post increment loads before
performing the load in case the offset register is overwritten.
2000-08-15 00:10:52 +00:00
Stephane Carrez
63348d048f Use address mapping levels for 68hc11 simulator (kill overlap hack) 2000-08-11 18:44:59 +00:00
Kazu Hirata
6d02850247 2000-08-10 Kazu Hirata <kazu@hxi.com>
* compile.c (decode): Clean up the code.
2000-08-11 02:03:02 +00:00
Andrew Cagney
548a3e15c8 Eliminate use of MIN(). 2000-08-11 00:48:51 +00:00
Alexandre Oliva
5425ca992e * am33.igen: Warning clean-up.
(movm): Initialize PC and mask.
(mov, movbu, movhu): Set srcreg2 from RI0.
(bsch): Initialize c.
(sat16_cmp): Actually do the comparison.
(mov_llt): Do not overwrite dstreg with uninitialized variable.
2000-08-09 18:42:04 +00:00
Frank Ch. Eigler
fab307a2bc * Usability improvement
2000-07-27  Frank Ch. Eigler  <fche@redhat.com>

	From Maciej W. Rozycki <macro@ds2.pg.gda.pl>
	* Makefile.in (install): Install run.1 man page.
2000-07-27 15:45:20 +00:00
Andrew Cagney
071da00250 Don't clean *.igen. 2000-07-27 12:03:19 +00:00
Andrew Cagney
46a19b74dd 2000-06-23 Doug Evans <dje@casey.transmeta.com>
* Makefile.in (headers,nltvals.def): Merge.
2000-07-27 11:56:34 +00:00
Andrew Cagney
f9cbceb6b7 2000-06-25 Stephane Carrez <Stephane.Carrez@worldnet.fr>
* nrun.c (main): Print the simulator statistics only in
        verbose mode.
        * hw-properties.h (hw_find_integer_array_property): Fix
        prototype (use signed_cell).
2000-07-27 11:49:07 +00:00
Andrew Cagney
38e64f358e 2000-06-25 Stephane Carrez <Stephane.Carrez@worldnet.fr>
* sim-events.c (sim_events_remain_time): New function returning
        the time that remains before the event is raised.
        * hw-events.c (hw_event_remain_time): Likewise.
        * sim-events.h (sim_events_remain_time): Declare.
        * hw-events.h (hw_event_remain_time): Declare.
2000-07-27 11:37:34 +00:00
Andrew Cagney
0802cc4008 2000-06-25 Stephane Carrez <Stephane.Carrez@worldnet.fr>
* sim-hw.c: Use <errno.h> instead of <sys/errno.h>
        (OPTION_HW_LIST): New option --hw-list to list the devices.
        (hw_option_handler): List the device tree with 'sim_hw_print'.
2000-07-27 11:34:30 +00:00
Andrew Cagney
5d031c16b8 Add m68hc11 configry. 2000-07-27 11:29:14 +00:00
Andrew Cagney
e0709f5044 New simulator. 2000-07-27 11:23:39 +00:00
Andrew Cagney
3c765a5497 From 2000-06-25 Stephane Carrez <Stephane.Carrez@worldnet.fr>:
* sim-bits.h (_MSB_16, _LSB_16): Define for 16-bit targets.
(MASK, LSBIT, MSBIT): Likewise and use _MSB_16 and _LSB_16.
(EXTENDED): Define for 16-bit word size.
* sim-bits.c (LSEXTRACTED, MSEXTRACTED, LSINSERTED,
MSINSERTED, LSSEXT, MSSEXT): Implement for 16-bit word size.
* sim-types.h: Added support for 16-bit targets.
2000-07-27 11:07:01 +00:00
Andrew Cagney
0a17cd5944 * compile.c (decode): Distinguish inc/dec.[wl] and adds/subs
correctly.
2000-07-27 09:39:50 +00:00
Andrew Cagney
a28c02cd2b * m16.igen (break): Call SignalException not sim_engine_halt. 2000-07-20 00:02:22 +00:00
Fernando Nasser
0a4321b903 2000-07-14 Fernando Nasser <fnasser@cygnus.com>
* wrapper.c (sim_create_inferior): Fix typo in the previous patch.
2000-07-14 21:27:15 +00:00
Fernando Nasser
64a1067567 2000-07-14 Fernando Nasser <fnasser@cygnus.com>
* wrapper.c (sim_create_inferior): Reset mode to ARM when creating a
        new inferior.
2000-07-14 16:49:46 +00:00
Nick Clifton
0dbdd75378 Change minimum loop size limit to 0x10 (103792) 2000-07-05 21:40:11 +00:00
Alexandre Oliva
ae3c7619e1 * armvirt.c (ABORTS): Do not define. 2000-07-04 08:00:19 +00:00
Alexandre Oliva
1e6b544a97 * armdefs.h (struct ARMul_State): Add is_StrongARM.
(ARM_Strong_Prop, STRONGARM): Define.
* arminit.c (ARMul_NewState): Reset is_StrongARM.
(ARMul_SelectProcessor): Set is_StrongARM.
* wrapper.c (sim_create_inferior): Use bfd machine type to
determine processor type to emulate.
* armemu.h (BUSUSEDINCPCS, BUSUSEDINCPCN): Don't increment PC
when emulating StrongARM.
2000-07-04 07:18:18 +00:00
Alexandre Oliva
66210567f0 * armemu.c (ARMul_Emulate, t_undefined): Proceed to next insn. 2000-07-04 06:54:48 +00:00
Alexandre Oliva
e063aa3bd8 * armemu.h (INSN_SIZE): New macro.
(SET_ABORT): Save CPSR in SPSR and set LR.
* armemu.c (ARMul_Emulate, isize): Set to INSN_SIZE.
(WriteR15, WriteSR15): Do not discard bit 1 in Thumb mode.
* arminit.c (ARMul_Abort): Use new SETABORT and INSN_SIZE.
2000-07-04 06:52:30 +00:00
Alexandre Oliva
13b6dd6f68 * armemu.c (LoadSMult): Use WriteR15() to discard the least
significant bits of PC.
2000-07-04 06:39:39 +00:00
Alexandre Oliva
892c6b9d8f * armemu.h (WRITEDESTB): New macro.
* armemu.c (ARMul_Emulate26, bl): Use WriteR15Branch() to
modify PC.  Moved the existing logic...
(WriteR15Branch): ... here.  New function.
(WriteR15, WriteSR15): Drop the two least significant bits.
(LoadSMult): Use WriteR15Branch() to modify PC.
(LoadMult): Use WRITEDESTB() instead of WRITEDEST().
2000-07-04 06:35:36 +00:00
Alexandre Oliva
cf52c765b0 * armemu.h (GETSPSR): Call ARMul_GetSPSR().
* armsupp.c (ARMul_CPSRAltered): Zero out bits as they're
extracted from state->Cpsr, but preserve the unused bits.
(ARMul_GetCPSR): Get bits preserved in state->Cpsr.
(ARMul_GetSPSR, ARMul_FixCPSR): Use ARMul_GetCPSR() to
get the full CPSR word.
2000-07-04 06:19:29 +00:00
Alexandre Oliva
4ef2594f4e * armemu.h (PSR_FBITS, PSR_SBITS, PSR_XBITS, PSR_CBITS): New.
(SETPSR_F, SETPSR_S, SETPSR_X, SETPSR_C): New macros.
(SETPSR, SET_INTMODE, SETCC): Removed.
* armsupp.c (ARMul_FixCPSR, ARMul_FixSPSR): Do not test bit
mask.  Use SETPSR_* to modify PSR.
(ARMul_SetCPSR): Load all bits from value.
* armemu.c (ARMul_Emulate, msr): Do not test bit mask.
2000-07-04 06:06:30 +00:00
Alexandre Oliva
e62263b8ec * armemu.c (ARMul_Emulate): Compute writeback value before
loading, since the offset register may be the destination
register.
2000-07-04 05:30:43 +00:00
Alexandre Oliva
b0eae074ca * armdefs.h (SYSTEMBANK): Define as USERBANK.
* armsupp.c (ARMul_SwitchMode): Remove SYSTEMBANK cases.
2000-07-04 05:16:20 +00:00
Andrew Cagney
6c29acca43 TIc80 simulator. 2000-07-04 05:00:54 +00:00
Andrew Cagney
80ee11fa0e Fix MOVN.fmt and MOVZ.fmt, need to test GPR[RT]. 2000-07-04 02:32:58 +00:00
Frank Ch. Eigler
7fb283bce2 * verbosity reduction
2000-06-23  Frank Ch. Eigler  <fche@redhat.com>

	* cgen-trace.h (TRACE_USEFUL_MASK): Remove TRACE_EVENTS_IDX.
2000-06-24 14:47:54 +00:00
Frank Ch. Eigler
ab42ee127d * build cleanliness fix
2000-06-24  Frank Ch. Eigler  <fche@redhat.com>

	From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
	* Makefile.in (distclean): Clean cconfig.h also.
2000-06-24 14:37:57 +00:00
Andrew Cagney
673388c077 Fix printf arguments. 2000-06-23 12:39:41 +00:00
Alexandre Oliva
f9c22bc3a4 * armemu.c (Multiply64): Fix computation of flag N. 2000-06-22 20:42:34 +00:00
Alexandre Oliva
ee9a777240 * armemu.c (MultiplyAdd64): Fix computation of flag N. 2000-06-22 20:03:32 +00:00
Frank Ch. Eigler
97ee9e5aa9 * build fix
2000-06-20  Frank Ch. Eigler  <fche@redhat.com>

	* compile.c: Don't include "wait.h".
	(sim_resume): Use local SIM_WIFEXITED and SIM_WIFSIGNALED macros
	instead of WIF* from host.
2000-06-20 21:12:33 +00:00
Alexandre Oliva
fe47e8dfd3 * armemu.h (NEGBRANCH): Do not overwrite the two most significant
bits of the offset.
2000-06-20 09:36:12 +00:00
Nick Clifton
bcd6576654 Add strongarm tests 2000-06-19 00:56:04 +00:00
Frank Ch. Eigler
98ecb0a78b * "Dont" -> "Don't"
2000-06-13  Frank Ch. Eigler  <fche@redhat.com>

	* compile.c, writecode.c: Correct typo.
2000-06-13 20:32:01 +00:00
Jeff Law
0ef9643e5e 2000-06-13 Kazu Hirata <kazu@hxi.com>
* compile.c: Fix formatting.
2000-06-13 19:54:56 +00:00
Joern Rennecke
2532761bdf sh-dsp support, simulator speedup by using host byte order:
* Makefile.in (interp.o): Depends on ppi.c .
	(ppi.c): New rule.
	* gencode.c (printonmatch, think, genopc): Deleted.
	(MAX_NR_STUFF): Now 42.
	(tab): Add SH-DSP CPU instructions.
	Amalgamate ldc / stc / lds / sts instructions with similar
	bit patterns.  Fix opcodes of stc Rm_BANK,@-<REG_N>.
	Fix semantics of lds.l @<REG_N>+,MACH (no sign extend).
	(movsxy_tab): New array.
	For movs, change MMMM field to GGGG, and mmmm field to MMMM.
	Added entries for movx, movy and parallel processing insns.
	(ppi_tab): New array.
	(qfunc): Stabilize sort.
	(expand_opcode): Handle [01][01]NN, [01][01]xx and [01][01]yy.
	Handle 'M', 'G' 's' 'X', 'a', 'Y' and 'A'.
	(dumptable): Now takes three arguments.  Changed all callers.
	Emit just one contigous jump table.
	(filltable): Now takes an argument.  Changed all callers.
	Make index static.
	(ppi_moves, expand_ppi_code, ppi_filltable, ppi_gensim): New functions.
	(gensim_caselist): New function, broken out of gensim.
	Handle opcode fields 'x', 'y', 's', 'M', 'G', 'X', 'a', and 'Y'.
	Handle ref '9'.
	(gensim): Handle 'N' in code field and '8' in refs field.
	Call gensim_caselist - twice.
	(ppi_index): New static variable.
	(main): Unsupport default action.
	Add dsp support for -x / -s option.  Add -p option.
	* interp.c (sh_jump_table, sh_dsp_table, ppi_table): Declare.
	(saved_state_type): Rearrange to allow amalgamated ldc / stc /
	lds / sts to work efficiently.
	(target_dsp): New static variable.
	(GBR, VBR, SSR, SPC, MACH, MACL): Reflect saved_state_type change.
	(FPUL, Rn_BANK, SET_Rn_BANK, M, Q, S, T, SR_BL, SR_RB): Likewise.
	(SR_MD, SR_RC, SET_SR_BIT, GET_SR, SET_RC, GET_FPSCR): Likewise.
	(RS, RE, MOD, MOD_ME, DSP_R): Likewise.
	(set_fpscr1): Likewise.  Use target_dsp to check for dsp.
	(MOD_MSi, SIG_BUS_FETCH): Deleted.
	(CREG, SREG, PR, SR_MASK_DMY, SR_MASK_DMX, SR_DMY): New macros.
	(SR_DMX, DSR, MOD_DELTA, GET_DSP_GRD): Likewise.
	(SET_MOD): Reflect saved_state_type change.  Set MOD_DELTA instead
	of MOD_MS, and encode SR_DMY / SR_DMX into high word of MOD_ME.
	(set_sr): Reflect saved_state_type change.  Fix SR_RB handling.
	Use SET_MOD.
	(MA, L, TL, TB): Now controlled by ACE_FAST.
	(SEXT32): Just cast to int.
	(SIGN32): Fixed to only shift by 31.
	(CHECK_INSN_PTR): SIGBUS at insn fetch now represented by insn_end 0.
	(ppi_insn): Declare.
	(ppi.c): Include.
	(init_dsp): Set target_dsp.  When it changes, switch end of
	sh_jump_table with sh_dsp_table.
	(sim_resume) Don't declare sh_jump_table0.  Use sh_jump_table instead.
	Don't Declare PR if it's #defined.
	Fix single-stepping (Was broken in Mar  6 16:59:10 patch).
	(sim_store_register, sim_read_register): Translate accesses to
	reflect saved_state_type change.

	* interp.c (set_sr): Set sr.
	(SET_RC, MOD, MOD_MS, MOD_ME, SET_MOD, MOD_MS, MOD_ME): New macros.
	(set_fpscr1): Don't bank-switch fpu registers when simulating sh-dsp.
	(DSP_R): Fix definition.
	(sim_resume): Remove outdated SET_SR use.

	* interp.c (saved_state): New members for struct member asregs:
	rs, re, insn_end, xram_start, yram_start.
	(struct loop_bounds): New struct.
	(SKIP_INSN): New macro.
	(get_loop_bounds): New function.
	(endianw): Renamed to global_endianw.
	(maskw): negated bits.
	(PC): Now insn_ptr.
	(SR_MASK_RC, SR_RC_INCREMENT, SR_RC, RAISE_EXCEPTION): New macros.
	(RS, RE, DSP_R, DSP_GRD, A1, A0, X0, X1, Y0, Y1, M0, A1G): Likewise.
	(M1, A0G, RIAT, PT2H, PH2T, SET_NIP, CHECK_INSN_PTR): Likewise.
	(SIG_BUS_FETCH): Likewise
	(raise_exception, riat_fast): New functions.
	(raise_buserror, sim_stop): Use raise_exception.
	(PROCESS_SPECIAL_ADDRESS): Use xram_start / yram_start.
	(BUSERROR, WRITE_BUSERROR, READ_BUSERROR):
	Reverse sense of mask argument.
	(FP_OP, set_dr): Use RAISE_EXCEPTION.
	(wlat_fast, wwat_fast, wbat_fast, rlat_fast, rwat_fast, rbat_fast):
	Declare.  Remove redundant masking.
	(wwat_fast, rwat_fast): Add argument endianw.  Changed callers.
	(MA): Updated for change pc -> PC.
	(Delay_Slot): Use RIAT.
	(empty): Deleted.
	(trap): Remove argument little_endian.  Add argument endianw.
	Changed all callers.  Use raise_exception.
	(macw): Add argument endainw.  Changed all callers.
	(init_dsp): New function, extended after broken out of init_pointers.
	(sim_resume): Replace pc with insn_ptr.  Replace little_endian with
	endianw.  Replace nia with nip.  Reverse sense of maskb / maskw /
	maskl.  Implement logic for zero-overhead loops.  Don't try to
	interpret garbage when getting a SIGBUS at insn fetch.
	(sim_open): Call init_dsp.
	* gencode.c (tab): Use SET_NIP instead of nia = .  Use PH2T / PT2H /
	RAISE_EXCEPTION where appropriate.
	Add extra cycles for brai, braf , bsr, bsrf, jmp, jsr.

	* interp.c (sim_store_register, sim_fetch_register):
	Do proper endianness switch.

	* interp.c (saved_state_type): New members for struct member asregs:
	xymem_select, xmem, ymem, xmem_offset, ymem_offset.
	(special_address): Delete.
	(BUSERROR): Now a two-argument predicate.
	(PROCESS_SPECIAL_ADDRESS, WRITE_BUSERROR, READ_BUSERROR): New macros.
	(wlat_little, wwat_little, wbat_any, wlat_big, wwat_big): Delete.
	(process_wlat_addr, process_wwat_addr): New functions.
	(process_wbat_addr, process_rlat_addr, process_rwat_addr): Likewise.
	(process_rbat_addr): Likewise.
	(wlat_fast, wwat_fast, wbat_fast): Use WRITE_BUSERROR.
	(rlat_little, rwat_little, rbat_any, rlat_big, rwat_big): Delete.
	(rlat_fast, rwat_fast, rbat_fast): Use READ_BUSERROR.
	(RWAT, RLAT, RBAT, WWAT, WLAT, WBAT): Delete SLOW versions.
	(do_rdat, trap): Delete SLOW code.
	(SEXT32, SIGN32): New macros.
	(swap, swap16): Now integer in - integer out.  Changed all callers.
	(strswaplen, strnswap): Delete SLOW versions.
	(init_pointers): Initialize dsp memory selection (preliminary).
	(sim_store_register, sim_fetch_register): Use swap instead of
	big / little endian read / write functions.

	* interp.c (maskl): Deleted.
	(endianw, endianb): New variables.
	(special_address): Now inline.
	(bp_holder): Put raising of buserror there, rename to:
	(raise_buserror).
	(BUSERROR): Now yields a value.  Changed all users.
	(wbat_big): Delete.
	(wlat_fast, wwat_fast, wbat_fast): New functions.
	(rlat_fast, rwat_fast, rbat_fast): Likewise.
	(RWAT, RLAT, RBAT, WWAT, WLAT, WBAT): Use new functions.
	(do_rdat, do_wdat): Likewise.  Take maskl argument instead of
	little_endian one.  Changed caller macros.
	(swap, swap16): Use w[rw]lat_big / w[rw]lat_little directly.
	(strswaplen, strnswap): New functions.
	(trap): Use them to fix up endian mismatches;
	disable SYS_execve and SYS_execv; fix double address translation for
	SYS_pipe and SYS_stat.
	(sym_write, sym_read): Add endianness translation.
	(sym_store_register, sym_fetch_register): Add maskl local variable.
	(sim_open): Set endianw and endianb.
2000-06-07 14:59:16 +00:00
Nick Clifton
896ad91016 Remove illegal instruciton pattern, since it is the same as the breakpoint
pattern.
2000-05-30 18:36:57 +00:00
Nick Clifton
c1a72ffdd6 Add support for v4 SystemMode. 2000-05-30 17:13:37 +00:00
Nick Clifton
4c0deff44c Define GPR_CLEAR 2000-05-29 19:38:39 +00:00
Nick Clifton
67f5c7ef0f fix spelling mistake in comment 2000-05-29 19:35:50 +00:00
Nick Clifton
33ae44dea2 Remove RCS tags to make synchronisation easier. 2000-05-29 19:34:13 +00:00
Nick Clifton
86e0da7a81 Use GPR_CLEAR instead of GPR_SET 2000-05-29 19:28:53 +00:00
Nick Clifton
f23b768a5c replace GPR_SET with GPR_CLEAR 2000-05-29 19:26:48 +00:00
Nick Clifton
ceec355905 minor formatting tweaks to aid syncronisation 2000-05-29 19:05:41 +00:00
Andrew Cagney
eb2d80b469 Change profiling so that it is enabled by default. Re-generate everything. 2000-05-24 04:39:50 +00:00
Nick Clifton
3463c3fbbb Add special case handling when GDB set CPSR register 2000-05-23 23:52:46 +00:00
Andrew Cagney
781c552e2d sigrc wasn't initialized before being passed to sim_resume(). 2000-05-23 11:34:27 +00:00
Alexandre Oliva
e33c036475 * am33.igen: Fix leading comments of SP-relative offset insns that
referred to other registers.  Make their offsets unsigned.
2000-05-22 20:34:09 +00:00
Alexandre Oliva
24a39d88a2 * mn10300_sim.h (genericAdd, genericSub, genericCmp, genericOr,
genericXor, genericBtst): Use `unsigned32'.
* op_utils.c: Likewise.
* mn10300.igen, am33.igen: Use `unsigned32', `signed32',
`unsigned64' or `signed64' where type width is relevant.
2000-05-18 22:56:28 +00:00
Joern Rennecke
63978407cb sh-dsp support, simulator speedup by using host byte order:
sim:
	* Makefile.in (interp.o): Depends on ppi.c .
	(ppi.c): New rule.
	* gencode.c (printonmatch, think, genopc): Deleted.
	(MAX_NR_STUFF): Now 42.
	(tab): Add SH-DSP CPU instructions.
	Amalgamate ldc / stc / lds / sts instructions with similar
	bit patterns.  Fix opcodes of stc Rm_BANK,@-<REG_N>.
	Fix semantics of lds.l @<REG_N>+,MACH (no sign extend).
	(movsxy_tab): New array.
	For movs, change MMMM field to GGGG, and mmmm field to MMMM.
	Added entries for movx, movy and parallel processing insns.
	(ppi_tab): New array.
	(qfunc): Stabilize sort.
	(expand_opcode): Handle [01][01]NN, [01][01]xx and [01][01]yy.
	Handle 'M', 'G' 's' 'X', 'a', 'Y' and 'A'.
	(dumptable): Now takes three arguments.  Changed all callers.
	Emit just one contigous jump table.
	(filltable): Now takes an argument.  Changed all callers.
	Make index static.
	(ppi_moves, expand_ppi_code, ppi_filltable, ppi_gensim): New functions.
	(gensim_caselist): New function, broken out of gensim.
	Handle opcode fields 'x', 'y', 's', 'M', 'G', 'X', 'a', and 'Y'.
	Handle ref '9'.
	(gensim): Handle 'N' in code field and '8' in refs field.
	Call gensim_caselist - twice.
	(ppi_index): New static variable.
	(main): Unsupport default action.
	Add dsp support for -x / -s option.  Add -p option.
	* interp.c (sh_jump_table, sh_dsp_table, ppi_table): Declare.
	(saved_state_type): Rearrange to allow amalgamated ldc / stc /
	lds / sts to work efficiently.
	(target_dsp): New static variable.
	(GBR, VBR, SSR, SPC, MACH, MACL): Reflect saved_state_type change.
	(FPUL, Rn_BANK, SET_Rn_BANK, M, Q, S, T, SR_BL, SR_RB): Likewise.
	(SR_MD, SR_RC, SET_SR_BIT, GET_SR, SET_RC, GET_FPSCR): Likewise.
	(RS, RE, MOD, MOD_ME, DSP_R): Likewise.
	(set_fpscr1): Likewise.  Use target_dsp to check for dsp.
	(MOD_MSi, SIG_BUS_FETCH): Deleted.
	(CREG, SREG, PR, SR_MASK_DMY, SR_MASK_DMX, SR_DMY): New macros.
	(SR_DMX, DSR, MOD_DELTA, GET_DSP_GRD): Likewise.
	(SET_MOD): Reflect saved_state_type change.  Set MOD_DELTA instead
	of MOD_MS, and encode SR_DMY / SR_DMX into high word of MOD_ME.
	(set_sr): Reflect saved_state_type change.  Fix SR_RB handling.
	Use SET_MOD.
	(MA, L, TL, TB): Now controlled by ACE_FAST.
	(SEXT32): Just cast to int.
	(SIGN32): Fixed to only shift by 31.
	(CHECK_INSN_PTR): SIGBUS at insn fetch now represented by insn_end 0.
	(ppi_insn): Declare.
	(ppi.c): Include.
	(init_dsp): Set target_dsp.  When it changes, switch end of
	sh_jump_table with sh_dsp_table.
	(sim_resume) Don't declare sh_jump_table0.  Use sh_jump_table instead.
	Don't Declare PR if it's #defined.
	Fix single-stepping (Was broken in Mar  6 16:59:10 patch).
	(sim_store_register, sim_read_register): Translate accesses to
	reflect saved_state_type change.

	* interp.c (set_sr): Set sr.
	(SET_RC, MOD, MOD_MS, MOD_ME, SET_MOD, MOD_MS, MOD_ME): New macros.
	(set_fpscr1): Don't bank-switch fpu registers when simulating sh-dsp.
	(DSP_R): Fix definition.
	(sim_resume): Remove outdated SET_SR use.

	* interp.c (saved_state): New members for struct member asregs:
	rs, re, insn_end, xram_start, yram_start.
	(struct loop_bounds): New struct.
	(SKIP_INSN): New macro.
	(get_loop_bounds): New function.
	(endianw): Renamed to global_endianw.
	(maskw): negated bits.
	(PC): Now insn_ptr.
	(SR_MASK_RC, SR_RC_INCREMENT, SR_RC, RAISE_EXCEPTION): New macros.
	(RS, RE, DSP_R, DSP_GRD, A1, A0, X0, X1, Y0, Y1, M0, A1G): Likewise.
	(M1, A0G, RIAT, PT2H, PH2T, SET_NIP, CHECK_INSN_PTR): Likewise.
	(SIG_BUS_FETCH): Likewise
	(raise_exception, riat_fast): New functions.
	(raise_buserror, sim_stop): Use raise_exception.
	(PROCESS_SPECIAL_ADDRESS): Use xram_start / yram_start.
	(BUSERROR, WRITE_BUSERROR, READ_BUSERROR):
	Reverse sense of mask argument.
	(FP_OP, set_dr): Use RAISE_EXCEPTION.
	(wlat_fast, wwat_fast, wbat_fast, rlat_fast, rwat_fast, rbat_fast):
	Declare.  Remove redundant masking.
	(wwat_fast, rwat_fast): Add argument endianw.  Changed callers.
	(MA): Updated for change pc -> PC.
	(Delay_Slot): Use RIAT.
	(empty): Deleted.
	(trap): Remove argument little_endian.  Add argument endianw.
	Changed all callers.  Use raise_exception.
	(macw): Add argument endainw.  Changed all callers.
	(init_dsp): New function, extended after broken out of init_pointers.
	(sim_resume): Replace pc with insn_ptr.  Replace little_endian with
	endianw.  Replace nia with nip.  Reverse sense of maskb / maskw /
	maskl.  Implement logic for zero-overhead loops.  Don't try to
	interpret garbage when getting a SIGBUS at insn fetch.
	(sim_open): Call init_dsp.
	* gencode.c (tab): Use SET_NIP instead of nia = .  Use PH2T / PT2H /
	RAISE_EXCEPTION where appropriate.
	Add extra cycles for brai, braf , bsr, bsrf, jmp, jsr.

	* interp.c (sim_store_register, sim_fetch_register):
	Do proper endianness switch.

	* interp.c (saved_state_type): New members for struct member asregs:
	xymem_select, xmem, ymem, xmem_offset, ymem_offset.
	(special_address): Delete.
	(BUSERROR): Now a two-argument predicate.
	(PROCESS_SPECIAL_ADDRESS, WRITE_BUSERROR, READ_BUSERROR): New macros.
	(wlat_little, wwat_little, wbat_any, wlat_big, wwat_big): Delete.
	(process_wlat_addr, process_wwat_addr): New functions.
	(process_wbat_addr, process_rlat_addr, process_rwat_addr): Likewise.
	(process_rbat_addr): Likewise.
	(wlat_fast, wwat_fast, wbat_fast): Use WRITE_BUSERROR.
	(rlat_little, rwat_little, rbat_any, rlat_big, rwat_big): Delete.
	(rlat_fast, rwat_fast, rbat_fast): Use READ_BUSERROR.
	(RWAT, RLAT, RBAT, WWAT, WLAT, WBAT): Delete SLOW versions.
	(do_rdat, trap): Delete SLOW code.
	(SEXT32, SIGN32): New macros.
	(swap, swap16): Now integer in - integer out.  Changed all callers.
	(strswaplen, strnswap): Delete SLOW versions.
	(init_pointers): Initialize dsp memory selection (preliminary).
	(sim_store_register, sim_fetch_register): Use swap instead of
	big / little endian read / write functions.

	* interp.c (maskl): Deleted.
	(endianw, endianb): New variables.
	(special_address): Now inline.
	(bp_holder): Put raising of buserror there, rename to:
	(raise_buserror).
	(BUSERROR): Now yields a value.  Changed all users.
	(wbat_big): Delete.
	(wlat_fast, wwat_fast, wbat_fast): New functions.
	(rlat_fast, rwat_fast, rbat_fast): Likewise.
	(RWAT, RLAT, RBAT, WWAT, WLAT, WBAT): Use new functions.
	(do_rdat, do_wdat): Likewise.  Take maskl argument instead of
	little_endian one.  Changed caller macros.
	(swap, swap16): Use w[rw]lat_big / w[rw]lat_little directly.
	(strswaplen, strnswap): New functions.
	(trap): Use them to fix up endian mismatches;
	disable SYS_execve and SYS_execv; fix double address translation for
	SYS_pipe and SYS_stat.
	(sym_write, sym_read): Add endianness translation.
	(sym_store_register, sym_fetch_register): Add maskl local variable.
	(sim_open): Set endianw and endianb.

gdb:

	* sh-tdep.c (sh_dsp_reg_names, sh3_dsp_reg_names): New arrays.
	(sh_processor_type_table): Add entries for bfd_mach_sh_dsp and
	 bfd_mach_sh3_dsp.
	(sh_show_regs): Floating point registers are called fr0-fr15.
	For sh4, display fpul, fpscr and fr0-fr15 / dr0-dr14 as appropriate.
	Handle sh-dsp and sh3-dsp.
	config/sh/tm-sh.h (REGISTER_VIRTUAL_TYPE): sh-dsp / sh3-dsp
	don't have floating point registers.
	(DSR_REGNUM, A0G_REGNUM, A0_REGNUM, A1G_REGNUM, A1_REGNUM): Define.
	(M0_REGNUM, M1_REGNUM, X0_REGNUM, X1_REGNUM, Y0_REGNUM): Likewise.
	(Y1_REGNUM, MOD_REGNUM, RS_REGNUM, RE_REGNUM, R0B_REGNUM): Likewise.
2000-05-15 21:12:42 +00:00
Frank Ch. Eigler
b9791fcdd6 * merge from internal tree
2000-04-14  Gary Thomas  <gthomas@redhat.com>

	* v850.igen: Define 'br *' as illegal since this is the only
	way to provide a breakpoint on some v850 family processors.
2000-05-08 23:07:39 +00:00
Andrew Cagney
ba744a4f56 Add missing ChangeLog.
Sync with mitsu's version.
2000-05-03 09:26:07 +00:00
Andrew Cagney
dd37a34b6f * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call. 2000-05-01 07:06:10 +00:00
Andrew Cagney
5eb1a8fac3 Provide more detailed traces of the event queue. 2000-04-28 06:13:46 +00:00
Andrew Cagney
0c22be818b Fix event insertion when processing more than one event for the current time. 2000-04-28 06:02:51 +00:00
Andrew Cagney
25d704f304 Cleanup tracing. 2000-04-28 05:59:25 +00:00
Alexandre Oliva
bfa8561f01 * am33.igen (inc4 Rn): Use genericAdd so as to modify flags. 2000-04-25 09:48:40 +00:00
Andrew Cagney
27842f65f2 Add support for SIGILL (reserved-instruction-exception). 2000-04-18 07:55:35 +00:00
Frank Ch. Eigler
5d0d395e94 * arm abort fix
2000-03-11  Philip Blundell  <philb@gnu.org>

	* armemu.c (LoadSMult, LoadMult): Correct handling of aborts.
	Patch from Allan Skillman <Allan.Skillman@arm.com>.
2000-04-10 15:35:56 +00:00
Andrew Cagney
e30db7381c Fix printf botch. 2000-04-09 14:15:43 +00:00
Alexandre Oliva
d8e7020fd6 * am33.igen: Make SP-relative offsets unsigned. Add `*am33' for
some instructions that were missing it.
2000-04-09 09:04:54 +00:00
Frank Ch. Eigler
01a991e1cd * updating copyright dates ("1999" -> "1999, 2000") 2000-04-05 22:31:29 +00:00
Dave Brolley
afb2cbbd21 2000-03-30 Dave Brolley <brolley@redhat.com>
* configure: Regenerated.
2000-03-30 20:51:27 +00:00
Dave Brolley
b2ac51e413 2000-03-30 Dave Brolley <brolley@redhat.com>
* aclocal.m4 (cgen): Use guile to run cgen.
2000-03-30 20:49:27 +00:00
Dave Brolley
f8603f2f73 2000-03-23 Dave Brolley <brolley@redhat.com>
* cgen-fpu.h: Rename extsfdf to fextsfdf. Rename truncdfsf to
	ftruncdfsf.
	* cgen-accfp.c (fextsfdf): New function.
	(ftruncdfsf): New function.
	(cgen_init_accurate_fpu): Initialize fextsfdf and ftruncdfsf.
2000-03-30 20:21:37 +00:00
Geoffrey Keating
9ff590a53b * ppc-instructions (Disabled_Exponent_Underflow): Increment
the exponent when denormalizing.
2000-03-25 18:45:41 +00:00
Frank Ch. Eigler
de616bc738 * more compatibility with v850 hardware
2000-03-24  Frank Ch. Eigler  <fche@redhat.com>

	* v850.igen (ilgop): New insn pattern for four-byte breakpoints.
2000-03-25 00:17:21 +00:00
Frank Ch. Eigler
6c9e0292a3 * memory corruption fix
Wed Mar 22 15:24:21 2000  glen mccready  <gkm@pobox.com>

	* wrapper.c (sim_open,sim_close): Copy into myname, free myname.
2000-03-23 23:28:43 +00:00
Frank Ch. Eigler
cb7450ea08 * simplify eCos testing
2000-03-21  Frank Ch. Eigler  <fche@redhat.com>

	* interp.c (sim_open): Sort & extend dummy memory regions for
	--board=jmr3904 for eCos.
2000-03-21 20:45:43 +00:00
Jeff Johnston
0f831eb384 2000-03-13 Jeff Johnston <jjohnstn@cygnus.com>
* cgen-ops.h: Added TRUNCSISI.
2000-03-13 23:51:48 +00:00
Frank Ch. Eigler
e88acae792 * extension
2000-03-08  Dave Brolley  <brolley@redhat.com>

	* cgen-par.h (cgen_write_queue_kind): Add CGEN_FN_SF_WRITE.
	(CGEN_WRITE_QUEUE_ELEMENT): Add fn_sf_write.
	(sim_queue_fn_si_write): Last argument is has type USI.
	(sim_queue_fn_sf_write): New function.
	* cgen-par.c (sim_queue_fn_si_write): Declare 'value' as USI.
	(sim_queue_fn_sf_write): New function.
	(cgen_write_queue_element_execute): Handle CGEN_FN_SF_WRITE.
2000-03-08 21:09:41 +00:00
Frank Ch. Eigler
a05391975e * build fix
2000-03-07  Frank Ch. Eigler  <fche@redhat.com>

	From John Dallaway  <jld@redhat.co.uk>:
	* Makefile.in (install-sis): Add $(EXEEXT) for Windows host.
2000-03-07 15:32:49 +00:00
Frank Ch. Eigler
8ae7f924f3 * moved misplaced ChangeLog entry 2000-03-04 12:46:44 +00:00
Andrew Cagney
7158fd7f9b Transfer SIM maintainership to Frank. 2000-03-04 06:27:00 +00:00
Frank Ch. Eigler
a9e3a73989 * build fix
2000-03-03  Alexandre Oliva  <oliva@lsd.ic.unicamp.br>

	* Makefile.in (IGEN_INSN): Added am33.igen.
2000-03-03 23:25:10 +00:00
Frank Ch. Eigler
0ef33cd05d * build patch
2000-03-03  Jonathan Larmour  <jlarmour@redhat.co.uk>

	* func.c (buffer_read_memory): Change type of size to unsigned to
	match prototype
2000-03-03 15:00:58 +00:00
Frank Ch. Eigler
4cd9361480 * comment tweaks 2000-03-02 22:42:51 +00:00
Frank Ch. Eigler
d018757450 * adding forgotten entry 2000-03-02 21:53:51 +00:00
Frank Ch. Eigler
a3027dd748 * autoconf correction
* merge from internal repo -> sourceware

2000-03-02  Frank Ch. Eigler  <fche@redhat.com>

	* configure: Regenerated.

Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>

	* interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
	calls, conditional on the simulator being in verbose mode.
2000-03-02 18:14:02 +00:00
Frank Ch. Eigler
58fddbac5a * whitespace correction 2000-03-02 18:12:44 +00:00
Andrew Cagney
baa7ae6f10 When SIM_HAVE_ENVIRONMENT: use sim_set_trace() to enable tracing
instead of sim_trace() to run the program; include support for ``-o''
option (operating environment); when a signal occurs, only continue
execution when operating environment mode.
Update d10v.
2000-02-22 08:52:21 +00:00
Nick Clifton
3dfcd3c614 Fix fclose() emulation 2000-02-14 19:49:48 +00:00
Nick Clifton
63a027a3fb Add support for M340 processor 2000-02-10 21:59:03 +00:00