darkkirb/old-cross-binutils
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841 commits

Author SHA1 Message Date
Nick Clifton
64ad9cecb6 Added N step divide routines, courtesy of Sugimoto at NEC. 1997-08-20 22:42:55 +00:00
Nick Clifton
70caad98c1 Fixed interpretation of SR bit in list18 structures. 1997-08-20 20:57:05 +00:00
Nick Clifton
27161f9e55 Add suport for v850e and v850eq 1997-08-18 18:01:42 +00:00
Nick Clifton
6ba5294adf Add support for V850eq variant opcodes. 1997-08-18 18:01:08 +00:00
David Edelsohn
dddbd8c586 Add comment. 1997-08-14 20:36:00 +00:00
David Edelsohn
052d7984df * callback.c (os_poll_quit): Make static. 
Call sim_cb_eprintf, not p->eprintf.
	(sim_cb_printf, sim_cb_eprintf): New functions.
 1997-08-14 19:53:10 +00:00
Nick Clifton
a0a6db4bfa Tidied up sanitization. 1997-08-14 19:45:14 +00:00
Nick Clifton
f7fcba7a84 Added support for v850e and v850eq instructions. 1997-08-14 02:13:32 +00:00
Mark Alexander
9e61ae7d3c * sim-calls.c (sim_store_register): Allow accumulators 
other than A0 to be modified.  Correct error message.
 1997-08-09 04:54:08 +00:00
Andrew Cagney
f1bea83b2b Add test for "mtsa" 1997-07-29 00:57:39 +00:00
Andrew Cagney
9204a35e78 Handle overflow from signed divide by -1. 1997-07-28 13:46:53 +00:00
Andrew Cagney
64f0e81628 More checks for pdivuw 1997-07-28 10:52:39 +00:00
Gavin Romig-Koch
c12e2e4c48 gencode.c: Two arg MADD should not assign result to /bin/bash. 1997-07-25 19:10:05 +00:00
David Edelsohn
63f6871728 * configure.in (sparc*-*-*): Don't build erc32. 
* configure: Regenerate.
 1997-07-25 18:41:12 +00:00
David Edelsohn
5697f15271 Keep sim-watch.[ch]. 1997-07-22 19:05:13 +00:00
David Edelsohn
556d1f8c7f Don't always keep igen, it's currently only kept if d30v or tic80. 1997-07-22 19:03:25 +00:00
David Edelsohn
e6609d8f2a * sim-n-core.h (sim_core_write_unaligned_N): Add missing break 
to FORCED_ALIGNMENT case.
 1997-07-22 17:36:23 +00:00
Andrew Cagney
7cf0d79519 Configure r5900 testsuite sub-directory. 1997-07-15 20:46:15 +00:00
Andrew Cagney
39e9b3369a Similistic configure/build scripts for tx59 simulator tests. 1997-07-15 20:35:26 +00:00
Andrew Cagney
b31dd8eea2 Generic tests for 5900. 1997-07-15 20:25:09 +00:00
Andrew Cagney
d9c61e8391 Standard simulator tests. 1997-07-14 16:53:04 +00:00
Andrew Cagney
ccc034af67 Tests for mips r5900 instructions 1997-07-11 21:36:11 +00:00
Andrew Cagney
1e851d2c82 Fix a number of problems in the r5900 specific p* (parallel) instructions. 
In particular a host endian dependency one fixed resolved most problems.
 1997-07-11 03:07:29 +00:00
Andrew Cagney
0f552ea045 Sync powerpc simulator with public version. Enable FPSCR and string 
instructions.
 1997-07-03 07:44:38 +00:00
Jeff Law
6443523484 * gencode.c (build_instruction): Handle "pext5" according to 
version 1.95 of the r5900 ISA.
Fixes pr12413 (c/h from toshiba).
 1997-07-02 18:41:22 +00:00
Jeff Law
649625bb8e * gencode.c (build_instruction): Handle "ppac5" according to 
version 1.95 of the r5900 ISA.
fixes pr12407 (c/h from toshiba).
 1997-07-02 18:29:16 +00:00
Jeff Law
05d1322f2c * interp.c (sim_engine_run): Reset the ZERO register to zero 
regardless of FEATURE_WARN_ZERO.
 1997-07-02 18:13:00 +00:00
Jeff Law
ae19b07bf8 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO. 
Fix for pr12402 (c/h from toshiba).
 1997-07-02 17:57:56 +00:00
Andrew Cagney
3a8e858f24 Add test for dbt/rtd instructions 1997-06-27 08:33:16 +00:00
Jeff Law
d05b86b7fb * interp.c (sim_resume): Clear State.exited. 
(sim_stop_reason): If State.exited is nonzero, then indicate that
        the simulator exited instead of stopped.
        * mn10300_sim.h (struct _state): Add exited field.
        * simops.c (syscall): Set State.exited for SYS_exit.

Fixes problem found bin Felix.
 1997-06-24 19:45:17 +00:00
Jeff Law
c370b3cd95 * simops.c: Fix thinko in last change. 1997-06-12 04:14:42 +00:00
Jeff Law
dbdb5bd881 * simops.c: "call" stores the callee saved registers into the 
stack!  Update the stack pointer properly when done with
        register saves.
 1997-06-10 22:59:13 +00:00
Jeff Law
0a8fa63cb8 * simops.c: Fix return address computation for "call" instructions. 1997-06-10 18:32:40 +00:00
Andrew Cagney
84e8cd0fcf Open in binary mode when available. 1997-06-06 02:34:55 +00:00
Andrew Cagney
0bdfae1167 Clean up formatting of instruction traces. 1997-06-06 00:31:08 +00:00
Andrew Cagney
897f67b74f Verify magic number of simulator struct. 1997-06-05 04:51:34 +00:00
Andrew Cagney
896eab009e Initialize the sim-engine module. 1997-06-04 02:47:49 +00:00
Andrew Cagney
56e7c84918 o Fixes to repeated watchpoints 
o	Add mips ISA instructions needed to handle interrupts
 1997-06-03 23:03:50 +00:00
Andrew Cagney
c7cebfa32c o Fix padd insn 
o	Take an interrupt when an int event occures.
 1997-06-02 15:00:43 +00:00
Andrew Cagney
128b51546e Add assembler information to igen input files. 1997-05-30 07:25:13 +00:00
Andrew Cagney
4e95b94e1e Fix subu immed - was incorrectly using unsigned. 1997-05-29 07:25:20 +00:00
Andrew Cagney
efe4f1cbf8 Add a simple dissasembler to igen 1997-05-29 07:06:41 +00:00
Andrew Cagney
1a70e182aa Fix watching PC for 64bit (mips) target. 
Stop watchpoints corrupting the event queue.
 1997-05-27 11:25:47 +00:00
Andrew Cagney
2f2e6c5d5b Extend xor-endian and per-cpu support in core module. 
Allow negated test when watching value within core.
 1997-05-27 06:48:20 +00:00
Andrew Cagney
cd0d873d0f Preliminary suport for xor-endian suport in core module. 1997-05-23 09:19:43 +00:00
Andrew Cagney
b526378484 Incorrect test for zero-r0 code gen. 1997-05-23 02:01:04 +00:00
Andrew Cagney
8167e102a5 Enumerate longjmp's return type. 1997-05-23 01:29:16 +00:00
Gavin Romig-Koch
d3d2a9f718 ifdef out uses of simSTOP, simSTEP and simBE when DEBUG is defined. 1997-05-22 13:30:01 +00:00
Gavin Romig-Koch
6e61ecfc92 Change longjmp param/setjmp return value used for simulator restart from 0 to 2. 1997-05-22 13:16:03 +00:00
Jeff Law
09e142d5a2 * interp.c (sim_resume): Add missing case in big switch 
statement (for extb instruction).
 1997-05-22 05:28:34 +00:00