* w89k-rom.c (_initialize_w89k ): Call new init function
(init_w89k_cmds): Convert to dynamic initialization of
monitor_ops data structure for forward compatability with
additions to the data structure.
* dbug-rom.c (_initialize_dbug_rom): ditto
(init_dbug_cmds): ditto
* m32r-rom.c (_initialize_m32r_rom): ditto
(init_m32r_cmds): ditto
* ldlang.c (wild_sort): Correct order of sort.
* scripttempl/elf.sc: Put *crtbegin.o before other .ctors and
.dtors.
* scripttempl/elfd10v.sc: Likewise.
start-sanitize-d30v
* scripttempl/elfd30v.sc: Likewise.
end-sanitize-d30v
* scripttempl/elfppc.sc: Likewise.
* Followup patch for SCEI PR 15853
* First check-in of TX3904 interrupt controller devices for ECC. [sanitized]
* First implementation of MIPS hardware interrupt emulation.
Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
* configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
modules. Recognize TX39 target with "mips*tx39" pattern.
* configure: Rebuilt.
* sim-main.h (*): Added many macros defining bits in
TX39 control registers.
(SignalInterrupt): Send actual PC instead of NULL.
(SignalNMIReset): New exception type.
* interp.c (board): New variable for future use to identify
a particular board being simulated.
(mips_option_handler,mips_options): Added "--board" option.
(interrupt_event): Send actual PC.
(sim_open): Make memory layout conditional on board setting.
(signal_exception): Initial implementation of hardware interrupt
handling. Accept another break instruction variant for simulator
exit.
(decode_coproc): Implement RFE instruction for TX39.
(mips.igen): Decode RFE instruction as such.
start-sanitize-tx3904
* configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
* interp.c: Define "jmr3904" and "jmr3904debug" board types and
bbegin to implement memory map.
* dv-tx3904cpu.c: New file.
* dv-tx3904irc.c: New file.
end-sanitize-tx3904
Mon May 18 12:37:38 1998 Frank Ch. Eigler <fche@cygnus.com>
* config/tc-mips.c (macro): For R5900, use "B" operand format for
"break" instructions generated in macro (div etc.) instructions.
Mon May 18 13:11:45 1998 Frank Ch. Eigler <fche@cygnus.com>
* gas/mips/{div,ld,mul}.d: Add assembler -mcpu= flag to match
disassembler.
start-sanitize-r5900
* gas/mips/break5900.[sd]: Test that break instructions generated
in div/etc. macro instructions are of 20-bit variety for R5900.
end-sanitize-r5900
* sim-engine.h (sim_engine_set_run_state): Declare.
* genmloop.sh (pending_reason,pending_sigrc): New static locals.
(@cpu@_engine_stop): New args reason,sigrc. All callers updated.
(engine_resume): Reorganize. Allow synchronous exit from main loop.
