Commit graph

132 commits

Author SHA1 Message Date
Jeff Law
c500c07496 * simops.c: Include <sys/stat.h>.
(OP_10007E0): Handle SYS_stat.
For RW testing.
1996-10-29 21:24:01 +00:00
Jeff Law
f009978996 * simops.c (OP_500): Mask off low bit in displacement
for sld.w.
        (OP_501): Similarly.
More bugs exposed by tda testing.
1996-10-24 21:19:22 +00:00
Jeff Law
85c09b0518 * simops.c (OP_500): Fix displacement handling for sld.w.
(OP_501): Similarly for sst.w.
More fixes exposed by tda testing.
1996-10-24 20:49:06 +00:00
Jeff Law
0a89af6efd * simops.c (trace_input): Remove all references to SEXT7.
(OP_300, OP_400, OP_500, OP_380, OP_480, OP_501): Displacement
        is zero extended for sst/sld instructions.
        * v850_sim.h (SEX7): Delete.  It's no longer needed (and it
        was incorrect anyway).
So we properly simulate sst/sld instructions.
1996-10-24 18:28:43 +00:00
Stu Grossman
968519095a * Makefile.in: Get rid of srcroot. Set all INSTALL macros via
autoconf.
	* gencode.c (write_opcodes):  Pad operands field to account for
	MSVC braindamage.
	* simops.c:  Include errno.h.  Exclude SYS_chown, since MSVC
	doesn't support it.  (Why is this here in the first place?!?)
	* v850_sim.h:  Get rid of 64 bit defs.  Also, get rid of #elif's.
	Change number of operands in struct simops from 9 to 6.  Define
	SIGTRAP and SIGQUIT for MSVC.
1996-10-24 17:39:30 +00:00
Stu Grossman
254ef34062 * interp.c (MEM_SIZE): It's now bytes, not a power of 2.
* (map):  Add support for external mem in the 1->2 meg range.
	Also, abort() when memory access is way out of bounds.  (Better to
	die than to give wrong result.  (This will be fixed later.))
	* (sim_size):  MEM_SIZE is now bytes, not shift factor.
1996-10-15 23:23:00 +00:00
Stu Grossman
88777ce2a6 * gencode.c (write_opcodes): Output hex values for opcode mask
and patterns.
	* interp.c (sim_resume):  Save and restore PC from the appropriate
	register.
	* (sim_fetch_register sim_store_register):  Fix byte-order problem
	with reading and writing registers.
	* simops.c (OP_FFFF):  Implement pseudo-breakpoint insn.
1996-09-28 01:38:45 +00:00
Jeff Law
da86a4fa81 * simops.c (trace_input): Fix thinko. 1996-09-27 23:41:12 +00:00
Michael Meissner
1d00ce8392 Print line # and function name or filename if they exist for each PC. 1996-09-12 16:06:02 +00:00
Michael Meissner
ead4a3f157 Add tracing support; Fix some problems with hardwired sizes 1996-09-11 20:54:21 +00:00
Jeff Law
9909e232c0 * interp.c (hash): Make this an inline function
when compiling with GCC.  Simplify.
        * simpos.c: Explicitly include "sys/syscall.h".  Remove
        some #if 0'd code.  Enable more emulated syscalls.
Checking in more stuff.
1996-09-10 02:51:07 +00:00
Jeff Law
9fca2fd3c6 * gencode.c: Fix various indention & style problems.
Remove test code.  Remove #if 0 code.
        * interp.c: Provide prototypes for all static functions.
        Fix minor indention problems.
        (sim_open, sim_resume): Remove unused variables.
        (sim_read): Return type is "int".
        * simops.c: Remove unused variables.
        (divh): Make result of divide-by-zero zero.
        (setf): Initialize result to keep compiler quiet.
        (sar instructions): These just clear the overflow bit.
        * v850_sim.h: Provide prototypes for put_byte, put_half
        and put_word.
Cleaning up.
1996-09-03 18:31:48 +00:00
Jeff Law
d81352b8b8 * interp.c: OP should be an array of 32bit operands!
(v850_callback): Declare.
        (do_format_5): Fix extraction of OP[0].
        (sim_size): Remove debugging printf.
        (sim_set_callbacks): Do something useful.
        (sim_stop_reason): Gross hacks to get c-torture running.
        * simops.c: Simplify code for computing targets of bCC
        insns.   Invert 's' bit if 'ov' bit is set for some
        instructions.  Fix 'cy' bit handling for numerous
        instructions.  Make the simulator stop when a halt
        instruction is encountered.  Very crude support for
        emulated syscalls (trap 0).
        * v850_sim.h: Include "callback.h" and declare
        v850_callback.  Items in the operand array are 32bits.
Fixes & syscall stuff.
1996-09-03 16:25:51 +00:00
Jeff Law
787d66bb4d * simops.c: Fix "not1" and "set1". 1996-08-30 21:55:26 +00:00
Jeff Law
3046d87986 * simops.c: Don't forget to initialize temp for
"ld.h" and "ld.w"
1996-08-30 20:15:51 +00:00
Jeff Law
ba853302f2 * interp.c: Remove various debugging printfs. 1996-08-30 16:42:49 +00:00
Jeff Law
0e4ccc58f2 * simops.c: Fix satadd, satsub boundary case handling. 1996-08-30 16:41:39 +00:00
Jeff Law
83fc3bac9f * interp.c (hash): Fix.
* interp.c (do_format_8): Get operands correctly and
        call the target function.
        * simops.c: Rough cut at "clr1", "not1", "set1", and "tst1".
1996-08-30 16:35:10 +00:00
Jeff Law
3cb6bf7818 * interp.c (do_format_4): Get operands correctly and
call the target function.
        * simops.c: Rough cut at "sld.b", "sld.h", "sld.w", "sst.b",
        "sst.h", and "sst.w".
1996-08-30 05:49:07 +00:00
Jeff Law
28647e4c0c * v850_sim.h: The V850 doesn't have split I&D spaces. Change
accordingly.  Remove many unused definitions.
        * interp.c: The V850 doesn't have split I&D spaces.  Change
        accordingly.
        (get_longlong, get_longword, get_word): Deleted.
        (write_longlong, write_longword, write_word): Deleted.
        (get_operands): Deleted.
        (get_byte, get_half, get_word): New functions.
        (put_byte, put_half, put_word): New functions.
        * simops.c: Remove unused functions.  Rough cut at
        "ld.b", "ld.h", "ld.w", "st.b", "st.h", "st.w" insns.
1996-08-30 05:41:10 +00:00
Jeff Law
614f1c68ed * v850_sim.h (struct _state): Remove "psw" field. Add
"sregs" field.
        (PSW): Remove bogus definition.
        * simops.c: Change condition code handling to use the psw
        register within the sregs array.  Handle "ldsr" and "stsr".
1996-08-30 05:09:08 +00:00
Jeff Law
dca41ba76b * simops.c: Handle "satadd", "satsub", "satsubi", "satsubr". 1996-08-30 04:59:02 +00:00
Jeff Law
e9b6cbaca5 * interp.c (do_format_5): Get operands correctly and
call the target function.
        (sim_resume): Don't do a PC update for format 5 instructions.
        * simops.c: Handle "jarl" and "jmp" instructions.
1996-08-30 04:27:48 +00:00
Jeff Law
3095b8dfc5 * simops.c: Fix minor typos. Handle "cmp", "setf", "tst"
"di", and "ei" instructions correctly.
1996-08-30 04:11:32 +00:00
Jeff Law
2108e86459 * interp.c (do_format_3): Get operands correctly and call
the target function.
        * simops.c: Handle bCC instructions.
1996-08-30 03:48:13 +00:00
Jeff Law
35404c7d07 * simops.c: Add condition code handling to shift insns.
Fix minor typos in condition code handling for other insns.
1996-08-30 03:23:36 +00:00
Jeff Law
aabce0f46c * Makefile.in: Fix typo.
* simops.c: Add condition code handling to "sub" "subr" and
        "divh" instructions.
1996-08-30 03:07:24 +00:00
Jeff Law
0ef0eba580 * interp.c (hash): Update to be more accurate.
(lookup_hash): Call hash rather than computing the hash
        code here.
        (do_format_1_2): Handle format 1 and format 2 instructions.
        Get operands correctly and call the target function.
        (do_format_6): Get operands correctly and call the target
        function.
        (do_formats_9_10): Rough cut so shift ops will work.
        (sim_resume): Tweak to deal with format 1 and format 2
        handling in a single funtion.  Don't update the PC
        for format 3 insns.  Fix typos.
        * simops.c: Slightly reorganize.  Add condition code handling
        to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
        and "not" instructions.
        * v850_sim.h (reg_t): Registers are 32bits.
        (_state): The V850 has 32 general registers.  Add a 32bit
        psw and pc register too.  Add accessor macros
Fixing lots of stuff.  Starting to add condition code support.  Basically
check pointing the work to date.
1996-08-29 23:39:23 +00:00
Jeff Law
775533747d * simops.c: Add shift support. 1996-08-29 22:29:41 +00:00
Jeff Law
e98e3b2c5a * simops.c: Add multiply & divide support. Abort for system
instructions.
1996-08-29 20:08:37 +00:00
Jeff Law
1fe983dcdf * simops.c: Add logicals, mov, movhi, movea, add, addi, sub
and subr.  No condition codes yet.
1996-08-29 19:53:37 +00:00
Jeff Law
22c1c7ddea * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
gencode.c, interp.c, simops.c: Created.
So we've got something to hack on.
1996-08-29 01:06:42 +00:00