darkkirb/old-cross-binutils
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13 commits

Author SHA1 Message Date
Joel Brobecker
4744ac1bb0 Switch the license of all files explicitly copyright the FSF 
to GPLv3.
 2007-08-24 14:30:15 +00:00
Daniel Jacobowitz
6aba47ca06 Copyright updates for 2007. 2007-01-09 17:59:20 +00:00
Andrew Cagney
4e0bf4c4d0 2002-11-21 Andrew Cagney <ac131313@redhat.com> 
* filter.c: Re-indent.
	* filter.h, filter_host.h, gen-engine.c, gen-engine.h: Ditto.
	* gen-icache.c, gen-icache.h, gen-idecode.c: Ditto.
	* gen-idecode.h, gen-itable.c, gen-itable.h: Ditto.
	* gen-model.c, gen-model.h, gen-semantics.c: Ditto.
	* gen-semantics.h, gen-support.c, gen-support.h: Ditto.
	* gen.c, gen.h, igen.c, igen.h, ld-cache.c, ld-cache.h: Ditto.
	* ld-decode.c, ld-decode.h, ld-insn.c, ld-insn.h, lf.c: Ditto.
	* lf.h, misc.c, misc.h, table.c, table.h: Ditto.
 2002-11-22 04:20:49 +00:00
Andrew Cagney
feaee4bdbb 2002-11-21 Andrew Cagney <ac131313@redhat.com> 
* Makefile.in: Update copyright.  IGEN contributed to the FSF.
        * filter.c, filter.h, filter_host.c, filter_host.h: Ditto.
        * gen-engine.c, gen-engine.h, gen-icache.c, gen-icache.h: Ditto.
        * gen-idecode.c, gen-idecode.h, gen-itable.c: Ditto.
        * gen-itable.h, gen-model.c, gen-model.h, gen-semantics.c: Ditto.
        * gen-semantics.h, gen-support.c, gen-support.h, gen.c: Ditto.
        * gen.h, igen.c, igen.h, ld-cache.c, ld-cache.h: Ditto.
        * ld-decode.c, ld-decode.h, ld-insn.c, ld-insn.h, lf.c: Ditto.
        * lf.h, misc.c, misc.h, table.c, table.h: Ditto.
 2002-11-22 04:09:40 +00:00
Nick Clifton
86e0da7a81 Use GPR_CLEAR instead of GPR_SET 2000-05-29 19:28:53 +00:00
Stan Shebs
c906108c21 Initial creation of sourceware repository 1999-04-16 01:35:26 +00:00
Stan Shebs
071ea11e85 Initial creation of sourceware repository 1999-04-16 01:34:07 +00:00
Andrew Cagney
687f3f1cef Add multi-sim support to simulator. 1997-09-08 17:40:24 +00:00
Andrew Cagney
cd0d873d0f Preliminary suport for xor-endian suport in core module. 1997-05-23 09:19:43 +00:00
Andrew Cagney
b526378484 Incorrect test for zero-r0 code gen. 1997-05-23 02:01:04 +00:00
Andrew Cagney
37a684b84d o Make tic80 insn file more `cache ready' 
o	Have igen always zero r0 instead of constantly checking if
	the designated register is r0.
 1997-05-16 03:27:40 +00:00
Michael Meissner
d23af88239 Fix problems -Wall found 1997-05-05 18:16:10 +00:00
Andrew Cagney
15c1649391 TIc80 simulator checkpoint - runs 3 instructions - trap, addu, br.a. 1997-04-22 17:46:07 +00:00