Commit graph

45 commits

Author SHA1 Message Date
Joel Brobecker
32d0add0a6 Update year range in copyright notice of all files owned by the GDB project.
gdb/ChangeLog:

        Update year range in copyright notice of all files.
2015-01-01 13:32:14 +04:00
Joel Brobecker
ecd75fc8ee Update Copyright year range in all files maintained by GDB. 2014-01-01 07:54:24 +04:00
Mike Frysinger
48a9389710 sim: bfin: note missing parallel handling of SEARCH
The SEARCH insn is an oddball when it comes to parallel usage.  It places a
big limit on what other insns it can run in parallel with, but we don't
currently track the amount of state needed to verify this (since no other insn
really requires this).  Add a note for now in case we get around to it.
2013-06-24 02:06:32 +00:00
Mike Frysinger
03dccef1ab sim: bfin: handle invalid HLs encoding in dsp shift insns
For many of the 32bit dsp shift related insns, we were just ignoring the HLs
field.  The hardware does not though and will reject the insn if it's set
incorrectly.  Update the sim to match.
2013-06-24 02:03:03 +00:00
Mike Frysinger
f7f8a049bd sim: bfin: stricter insn decoding
We wrote a test case that tries every single 32bit opcode on the hardware
and compared it to the sim.  There were a bunch of places in the sim where
we weren't strict enough (requiring certain parts of the opcode be set) so
we were treating a lot of invalid opcodes as valid ones.  This sprinkles
out a lot additional checks in the dsp32alu class.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2013-06-19 03:12:26 +00:00
Joel Brobecker
8acc9f485b Update years in copyright notice for the GDB files.
Two modifications:
  1. The addition of 2013 to the copyright year range for every file;
  2. The use of a single year range, instead of potentially multiple
     year ranges, as approved by the FSF.
2013-01-01 06:41:43 +00:00
Mike Frysinger
c0c463826f sim: bfin: fix ASTAT issues in immediate shifts
More ASTAT directed fixes, but this time at the dsp32shift insns.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-09 05:56:32 +00:00
Mike Frysinger
ef0b041e05 sim: bfin: fix ASTAT/correctness issues with arithmetic shifts
This improves some of the arithmetic shifts to better match the
hardware (especially wrt ASTAT behavior).  We hit areas where
the published documentation is thin so we have to rely on tests
run on the hardware to figure out how things should behave.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-09 05:52:38 +00:00
Mike Frysinger
ab04c00066 sim: bfin: more parallel insn checks
Now that we keep track of the exact parallel insn slot we're in, we can
make sure that the current insn being decoded is valid for that slot.
This brings us much closer to the hardware in flagging invalid parallel
insn combinations.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-09 03:59:10 +00:00
Mike Frysinger
99265d6b00 sim: bfin: keep track of the exact position of parallel insns
Some insns need to know which slot they're in to determine whether they
are valid.  So add an enum for each slot, and check that rather than the
overall insn len.  This makes tracking things in the code much clearer.
However, this code is functionally the same, so a follow up patch will
leverage this more to properly flag invalid parallel insn combos.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-09 03:49:30 +00:00
Mike Frysinger
a8a0e37c8b sim: bfin: drop excess space in negation insn
The amod1 helper includes a leading space so it can expand into the empty
string when need be, which means the caller need not add spacing itself.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-08 20:48:20 +00:00
Mike Frysinger
1d18e9892e sim: bfin: throw VEC_ILGAL_I with 32bit insn in group1/group2 slots
Parallel insns can only do one 32bit, then two 16bits.  So if we see
a 2nd 32bit insn after the first 32bit in a parallel insn, abort.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-01 04:31:46 +00:00
Mike Frysinger
2fa7a0570b sim: bfin: simplify field width processing and fix build warnings
This fix the build time warning:
warning: format not a string literal, argument types not checked [-Wformat-nonliteral]

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-01 04:23:40 +00:00
Mike Frysinger
e62bb22a4b sim: bfin: fix corner case Logical shift issues
From: Robin Getz <robin.getz@analog.com>

Overflow with shift operations happens independently of saturation, but
we have the logic merged.  Extend the lshift function so that callers
can tell it when to handle each independently, and then do so when it's
needed.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-19 05:06:23 +00:00
Joel Brobecker
c5a5708100 Copyright year update in most files of the GDB Project.
gdb/ChangeLog:

        Copyright year update in most files of the GDB Project.
2012-01-04 08:28:28 +00:00
Mike Frysinger
39c1f96aef sim: bfin: use store buffer for VIT_MAX insns
The VIT_MAX insns can be used in parallel, so we need to use the store
buffer so we don't clobber the output register before we get a chance
to do a memory store with it.

Reported-by: Kai Iskratsch <kai@stella.at>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-09-29 03:19:47 +00:00
Mike Frysinger
1f20b1457b sim: bfin: set ASTAT AV/AVS when shifting accumulators overflow
The LSHIFT/ASHIFT insns that work with accumulators lacked AV/AVS
handling in the ASTAT register, so add it to match the hardware.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 22:03:10 +00:00
Mike Frysinger
b4876e0485 sim: bfin: do not touch ASTAT[V] when shifting accumulators
If we're shifting accumulators, we don't want to touch the V bit in
ASTAT, so add size checks to the ashiftrt/lshiftrt helpers.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 21:59:38 +00:00
Mike Frysinger
d5fcd950e4 sim: bfin: do not extend accumulator in LSHIFT insns
The logical shift insn does not sign extend before shifting, so
we shouldn't either.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 21:58:08 +00:00
Mike Frysinger
a56a195412 sim: bfin: tweak saturation handling with TFU/FU modes and MM bit
This too should have been squashed into an earlier change.  It covers
a few more cases in the V/VS saturation patch when working with TFU
and FU modes of dsp insns.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 21:22:50 +00:00
Mike Frysinger
90e13d65c1 sim: bfin: handle large shift values with accumulator shift insns
When the shift magnitude exceeds 32 bits, the values rotate around (since
the hardware is actually a barrel shifter).  So handle this edge case,
update the corresponding AV bit in ASTAT which was missing previously,
and tweak the AZ setting based on how the hardware behaves.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 20:59:54 +00:00
Mike Frysinger
99dcc4dc65 sim: bfin: handle odd shift values with shift insns
The shift magnitude is a 5-bit signed value.  When it is between 0 and
15, then we do the requested shift, but when it is outside of that, we
have to do the opposite.

That means we flip between lshift and ashiftrt to match the hardware.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 20:59:24 +00:00
Mike Frysinger
a0a71a7f8b sim: bfin: fix M_IH saturation size
This reverts the previous commit and does it right.  This change got
lost in the shuffle of patches I have pending.

Basically the logic is to change the 32bit saturation (and then masked
to 16bits) to a proper 16bit saturation.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 20:10:57 +00:00
Mike Frysinger
388aa9fe20 sim: bfin: handle V/VS saturation in dsp mac insns
Some saturation cases with dsp mac insns were not setting the V flag.
So implement that part and split up the logic between the dual macs.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 20:04:32 +00:00
Mike Frysinger
f2a56d0ad7 sim: bfin: handle the MM flag in M_IU/M_TFU modes with dsp insns
Our handling of the M_IU/M_TFU modes are missing signed saturation when
the MM flag is set, so add it to match the hardware behavior.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 19:44:14 +00:00
Mike Frysinger
ef26d60eba sim: bfin: fix sign extension in dsp insns with MM flag
After testing the hardware with all the different dsp flags, the MM flag
triggers sign extension in all modes.  So drop the limited use of it, and
the local custom helper that was also extending unsigned values.  We also
can see that the flag checks in the mult/mac insns have the same behavior
with sign extending, so add a helper func to keep the logic the same in
both places.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 19:42:55 +00:00
Mike Frysinger
075a845a92 sim: bfin: fix dsp insns IH saturation/rounding behavior
When using the IH modifier, we need to first saturate the value before
rounding it, and then further saturate it a bit more.  This makes the
sim match the hardware behavior with these insns.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 19:24:57 +00:00
Mike Frysinger
73aae8efb2 sim: bfin: fix accumulator edge case saturation
When the accumulator saturates, it needs to be greater than, but not
equal to, the largest unsigned value as this is what the hardware does.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18 17:27:01 +00:00
Mike Frysinger
efac2223c4 sim: bfin: allow pushing of SP
The hardware respects this insn, and some code (like the on-chip bootrom)
uses it, so allow it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-14 16:00:37 +00:00
Mike Frysinger
0427acfba0 sim: bfin: use store buffer with more 32bit insns
A bunch of 32bit insns were not using the store buffer, so when they were
used in parallel insns, they would incorrectly clobber a register early.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-16 17:37:55 +00:00
Mike Frysinger
d2cfa400a1 sim: bfin: handle implicit DISALGNEXCPT with video insns
When most video related insns are used in parallel with Ireg loads, the
DISALGNEXCPT insn behavior is implicitly in effect.

Reported-by: Anton Shokurov <shokurov.anton.v@yandex.ru>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-15 01:21:21 +00:00
Mike Frysinger
1a3af0bfc3 sim: bfin: fix sign extension with 16bit acc add insns
The current implementation attempts to handle the 16bit sign extension
itself.  Unfortunately, it gets it right in some cases.  So rather than
fix that logic, just drop it in favor of using 16bit signed casts.  Now
gcc will take care of getting the logic right.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-29 01:41:49 +00:00
Mike Frysinger
36aef94270 sim: bfin: handle saturation with RND12 sub insns
The current handling of the subtraction insn with the RND12 modifier
works when saturation isn't involved.  So add handling for this edge
case to match the hardware.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-27 04:03:05 +00:00
Mike Frysinger
fcd1ee07d3 sim: bfin: add missing VS set with add/sub insns
The 16bit add/sub insns missed setting the VS bit in ASTAT whenever the
V bit was also set.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-26 06:02:41 +00:00
Mike Frysinger
8e670c0a3f sim: bfin: update VIT_MAX behavior to match hardware when Acc.X bits are set
The Blackfin PRM says that the top 8 bits of the accumulator must be
cleared when using the VIT_MAX insn, so the sim has followed this spec.
Matching the hardware behavior though when the high bits are not cleared
is easy to do and doesn't break existing behavior, so go for it.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:14:20 +00:00
Mike Frysinger
de0addfbef sim: bfin: always do 16bit sign extension with the SEARCH insn
The Blackfin PRM does not cover this case, but the hardware is clear: even
if the search criteria is not met (and thus a new 16bit value is loaded up
into the accumulator), the accumulator undergoes 16bit sign extension.  So
simply reload the low signed 16bits in that case.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:13:32 +00:00
Mike Frysinger
beb378a5f2 sim: bfin: update AV and AC ASTAT bits with acc negation
The Acc=-Acc insn can overflow or carry with edge values, so make sure
we update the ASTAT bits accordingly to match the hardware.  Also fix
a thinko where we always updated AC0 even when working with A1 regs.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:12:16 +00:00
Mike Frysinger
8d8a97461a sim: bfin: allow byteop[123]p src regs to be the same
The hardware allows the byteop[123]p insns to use the same src reg pair,
so remove the combination check in the sim.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:08:15 +00:00
Mike Frysinger
227d265839 sim: bfin: handle AZ updates with 16bit adds/subs
We weren't updating AZ when doing a 16bit add or sub insn.  Implement it.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15 20:10:40 +00:00
Mike Frysinger
e3809a37d4 sim: bfin: skip acc/ASTAT updates for moves
No point in moving unchanged acc values to the acc regs, and avoid
updating the acc ASTAT bits when only reading.  This fixes incorrect
changing of the ASTAT bits when they're only being read.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15 20:10:12 +00:00
Mike Frysinger
86d3d8de68 sim: bfin: handle AN (negative overflows) in dsp mult insns
The current dsp mult handler does not take care of overflows which turn
values negative (and thus set AN in ASTAT).  So implement it.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15 20:09:39 +00:00
Mike Frysinger
9b7509d900 sim: bfin: handle V overflows in dsp mult insns
The current dsp mult handler does not take care of overflows and updating
the V ASTAT bit.  So implement it.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15 20:09:09 +00:00
Mike Frysinger
bf416ccded sim: bfin: decode ASTAT on failure
When testing ASTAT regs, specific bit differences carry a lot more meaning
than when checking the value of a data register.  So automatically decode
the bits of the two values and print things out so that people don't have
to manually do it themselves every time.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15 20:08:27 +00:00
Mike Frysinger
c9329594d4 sim: bfin: handle saturation with fract multiplications
The saturation behavior with fract modes differs from non-fract modes.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15 20:04:04 +00:00
Mike Frysinger
ef016f835f sim: bfin: new port
This can boot Das U-Boot and a Linux kernel.  It also supports Linux
userspace FLAT and FDPIC (dynamic and static) ELFs.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-06 00:20:21 +00:00